Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16712499	1			T1	11994		T4	751		T5	1672
all_pins[1]	16712499	1			T1	11994		T4	751		T5	1672
all_pins[2]	16712499	1			T1	11994		T4	751		T5	1672

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42759642	1			T1	31935		T4	1895		T5	4391
values[0x1]	7377855	1			T1	4047		T4	358		T5	625
transitions[0x0=>0x1]	7377709	1			T1	4047		T4	358		T5	625
transitions[0x1=>0x0]	7377720	1			T1	4047		T4	358		T5	625

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16693382	1			T1	11977		T4	740		T5	1649
all_pins[0]	values[0x1]	19117	1			T1	17		T4	11		T5	23
all_pins[0]	transitions[0x0=>0x1]	19066	1			T1	17		T4	11		T5	23
all_pins[0]	transitions[0x1=>0x0]	7358381	1			T1	4030		T4	347		T5	602
all_pins[1]	values[0x0]	16712182	1			T1	11994		T4	751		T5	1672
all_pins[1]	values[0x1]	317	1			T27	10		T28	6		T12	1
all_pins[1]	transitions[0x0=>0x1]	270	1			T27	10		T28	6		T12	1
all_pins[1]	transitions[0x1=>0x0]	19070	1			T1	17		T4	11		T5	23
all_pins[2]	values[0x0]	9354078	1			T1	7964		T4	404		T5	1070
all_pins[2]	values[0x1]	7358421	1			T1	4030		T4	347		T5	602
all_pins[2]	transitions[0x0=>0x1]	7358373	1			T1	4030		T4	347		T5	602
all_pins[2]	transitions[0x1=>0x0]	269	1			T27	10		T28	6		T29	3