Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 893 1 T12 4 T18 7 T31 10
all_values[1] 893 1 T12 4 T18 7 T31 10
all_values[2] 893 1 T12 4 T18 7 T31 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1384 1 T12 2 T18 9 T31 15
auto[1] 1295 1 T12 10 T18 12 T31 15


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1012 1 T12 6 T18 3 T31 13
auto[1] 1667 1 T12 6 T18 18 T31 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1551 1 T12 8 T18 10 T31 18
auto[1] 1128 1 T12 4 T18 11 T31 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 186 1 T12 2 T18 1 T31 2
all_values[0] auto[0] auto[0] auto[1] 76 1 T18 1 T77 4 T133 2
all_values[0] auto[0] auto[1] auto[0] 177 1 T12 2 T18 2 T31 4
all_values[0] auto[0] auto[1] auto[1] 78 1 T15 1 T134 1 T97 2
all_values[0] auto[1] auto[0] auto[1] 191 1 T18 1 T31 3 T19 1
all_values[0] auto[1] auto[1] auto[1] 185 1 T18 2 T31 1 T32 1
all_values[1] auto[0] auto[0] auto[0] 156 1 T31 3 T15 6 T77 2
all_values[1] auto[0] auto[0] auto[1] 100 1 T31 1 T15 2 T77 3
all_values[1] auto[0] auto[1] auto[0] 137 1 T12 2 T32 2 T19 2
all_values[1] auto[0] auto[1] auto[1] 123 1 T12 1 T18 3 T31 1
all_values[1] auto[1] auto[0] auto[1] 196 1 T18 2 T31 2 T15 6
all_values[1] auto[1] auto[1] auto[1] 181 1 T12 1 T18 2 T31 3
all_values[2] auto[0] auto[0] auto[0] 189 1 T19 1 T15 2 T135 5
all_values[2] auto[0] auto[0] auto[1] 96 1 T18 1 T31 2 T32 1
all_values[2] auto[0] auto[1] auto[0] 167 1 T31 4 T32 2 T15 8
all_values[2] auto[0] auto[1] auto[1] 66 1 T12 1 T18 2 T31 1
all_values[2] auto[1] auto[0] auto[1] 194 1 T18 3 T31 2 T15 4
all_values[2] auto[1] auto[1] auto[1] 181 1 T12 3 T18 1 T31 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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