Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3886	1			T1	2		T4	5		T5	8
sha2_none	3826	1			T1	2		T4	3		T5	9
sha2_512	7295	1			T1	5		T5	8		T6	2
sha2_384	6648	1			T1	6		T4	8		T5	4
sha2_256	5891	1			T1	5		T4	3		T5	5

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17526

1

T1

8

T4

11

T5

16

auto[1]

10351

1

T1

12

T4

8

T5

19

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10368

1

T1

7

T4

9

T5

25

auto[1]

17509

1

T1

13

T4

10

T5

10

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14646

1

T1

12

T4

13

T5

20

disabled

13231

1

T1

8

T4

6

T5

15

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4214	1			T1	4		T4	3		T5	3
key_none	7194	1			T1	1		T4	5		T5	6
key_1024	4209	1			T1	5		T4	3		T5	4
key_512	3541	1			T1	1		T4	4		T5	7
key_384	3180	1			T1	1		T4	2		T5	10
key_256	2757	1			T1	5		T4	2		T5	3
key_128	2709	1			T1	3		T5	2		T6	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17589

1

T1

8

T4

13

T5

15

auto[1]

10288

1

T1

12

T4

6

T5

20

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27672

1

T1

20

T4

19

T5

35

disabled

205

1

T60

2

T61

1

T62

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1489

1

T4

2

T5

4

T25

2

enabled

auto[0]

auto[0]

auto[1]

1506

1

T4

1

T5

2

T6

1

enabled

auto[0]

auto[1]

auto[0]

1441

1

T1

2

T4

3

T5

3

enabled

auto[0]

auto[1]

auto[1]

1508

1

T1

4

T5

4

T6

1

enabled

auto[1]

auto[0]

auto[0]

4216

1

T1

2

T4

5

T25

2

enabled

auto[1]

auto[0]

auto[1]

1456

1

T1

3

T5

3

T6

1

enabled

auto[1]

auto[1]

auto[0]

1602

1

T5

1

T25

2

T24

1

enabled

auto[1]

auto[1]

auto[1]

1428

1

T1

1

T4

2

T5

3

disabled

auto[0]

auto[0]

auto[0]

1113

1

T5

1

T6

1

T25

2

disabled

auto[0]

auto[0]

auto[1]

1091

1

T1

1

T4

1

T5

6

disabled

auto[0]

auto[1]

auto[0]

1099

1

T4

1

T5

5

T8

1

disabled

auto[0]

auto[1]

auto[1]

1121

1

T4

1

T6

2

T25

3

disabled

auto[1]

auto[0]

auto[0]

5579

1

T1

1

T4

2

T6

4

disabled

auto[1]

auto[0]

auto[1]

1076

1

T1

1

T6

2

T25

3

disabled

auto[1]

auto[1]

auto[0]

1050

1

T1

3

T5

1

T6

3

disabled

auto[1]

auto[1]

auto[1]

1102

1

T1

2

T4

1

T5

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14583

1

T1

12

T4

13

T5

20

enabled

disabled

63

1

T60

1

T63

1

T147

1

disabled

disabled

142

1

T60

1

T61

1

T62

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13089

1

T1

8

T4

6

T5

15

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1051	1			T4	1		T5	2		T25	1
key_invalid	sha2_none	781	1			T1	1		T4	2		T6	2
key_invalid	sha2_512	766	1			T1	2		T25	1		T7	1
key_invalid	sha2_384	788	1			T5	1		T25	2		T24	1
key_invalid	sha2_256	740	1			T1	1		T6	3		T25	3
key_none	sha2_invalid	466	1			T4	1		T5	2		T6	1
key_none	sha2_none	519	1			T5	2		T6	2		T24	2
key_none	sha2_512	2516	1			T1	1		T5	1		T10	1
key_none	sha2_384	2112	1			T4	1		T6	2		T25	1
key_none	sha2_256	1533	1			T4	3		T5	1		T8	1
key_1024	sha2_invalid	497	1			T1	2		T6	1		T25	1
key_1024	sha2_none	543	1			T5	2		T60	1		T26	1
key_1024	sha2_512	1705	1			T5	2		T7	1		T9	1
key_1024	sha2_384	867	1			T1	1		T4	3		T25	1
key_512	sha2_invalid	454	1			T4	1		T5	3		T25	1
key_512	sha2_none	484	1			T4	1		T5	2		T25	2
key_512	sha2_512	579	1			T5	1		T8	1		T56	1
key_512	sha2_384	1172	1			T1	1		T4	2		T8	1
key_512	sha2_256	807	1			T5	1		T7	2		T10	1
key_384	sha2_invalid	484	1			T4	2		T5	1		T6	1
key_384	sha2_none	513	1			T5	1		T25	1		T56	1
key_384	sha2_512	564	1			T5	3		T6	2		T7	1
key_384	sha2_384	571	1			T5	2		T6	2		T7	1
key_384	sha2_256	1010	1			T1	1		T5	3		T25	1
key_256	sha2_invalid	445	1			T25	1		T7	1		T9	1
key_256	sha2_none	496	1			T1	1		T5	1		T6	1
key_256	sha2_512	561	1			T1	1		T25	1		T7	1
key_256	sha2_384	544	1			T1	3		T4	2		T5	1
key_256	sha2_256	677	1			T25	1		T8	1		T7	2
key_128	sha2_invalid	474	1			T6	2		T7	1		T9	1
key_128	sha2_none	481	1			T5	1		T6	1		T25	4
key_128	sha2_512	586	1			T1	1		T5	1		T25	1
key_128	sha2_384	573	1			T1	1		T25	1		T7	1
key_128	sha2_256	562	1			T1	1		T25	1		T7	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

553

1

T1

2

T25

1

T7

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1051	1			T4	1		T5	2		T25	1
key_invalid	sha2_none	781	1			T1	1		T4	2		T6	2
key_invalid	sha2_512	766	1			T1	2		T25	1		T7	1
key_invalid	sha2_384	788	1			T5	1		T25	2		T24	1
key_invalid	sha2_256	740	1			T1	1		T6	3		T25	3
key_none	sha2_invalid	466	1			T4	1		T5	2		T6	1
key_none	sha2_none	519	1			T5	2		T6	2		T24	2
key_none	sha2_512	2516	1			T1	1		T5	1		T10	1
key_none	sha2_384	2112	1			T4	1		T6	2		T25	1
key_none	sha2_256	1533	1			T4	3		T5	1		T8	1
key_1024	sha2_invalid	497	1			T1	2		T6	1		T25	1
key_1024	sha2_none	543	1			T5	2		T60	1		T26	1
key_1024	sha2_512	1705	1			T5	2		T7	1		T9	1
key_1024	sha2_384	867	1			T1	1		T4	3		T25	1
key_1024	sha2_256	553	1			T1	2		T25	1		T7	2
key_512	sha2_invalid	454	1			T4	1		T5	3		T25	1
key_512	sha2_none	484	1			T4	1		T5	2		T25	2
key_512	sha2_512	579	1			T5	1		T8	1		T56	1
key_512	sha2_384	1172	1			T1	1		T4	2		T8	1
key_512	sha2_256	807	1			T5	1		T7	2		T10	1
key_384	sha2_invalid	484	1			T4	2		T5	1		T6	1
key_384	sha2_none	513	1			T5	1		T25	1		T56	1
key_384	sha2_512	564	1			T5	3		T6	2		T7	1
key_384	sha2_384	571	1			T5	2		T6	2		T7	1
key_384	sha2_256	1010	1			T1	1		T5	3		T25	1
key_256	sha2_invalid	445	1			T25	1		T7	1		T9	1
key_256	sha2_none	496	1			T1	1		T5	1		T6	1
key_256	sha2_512	561	1			T1	1		T25	1		T7	1
key_256	sha2_384	544	1			T1	3		T4	2		T5	1
key_256	sha2_256	677	1			T25	1		T8	1		T7	2
key_128	sha2_invalid	474	1			T6	2		T7	1		T9	1
key_128	sha2_none	481	1			T5	1		T6	1		T25	4
key_128	sha2_512	586	1			T1	1		T5	1		T25	1
key_128	sha2_384	573	1			T1	1		T25	1		T7	1
key_128	sha2_256	562	1			T1	1		T25	1		T7	2