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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 95.26 97.27 100.00 97.06 98.12 97.97 99.85


Total test records in report: 656
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T537 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3870311457 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:35 AM UTC 24 102524478 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1225873378 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:35 AM UTC 24 122121528 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2262576335 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:36 AM UTC 24 183286394 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.970680511 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:36 AM UTC 24 52985350 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2931372788 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:36 AM UTC 24 16072743 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2616970373 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:36 AM UTC 24 29855040 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2609189984 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:36 AM UTC 24 35197716 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3511753276 Aug 25 04:07:34 AM UTC 24 Aug 25 04:07:36 AM UTC 24 20559204 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3117650461 Aug 25 04:07:34 AM UTC 24 Aug 25 04:07:36 AM UTC 24 19580689 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.2329795803 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:37 AM UTC 24 1682991213 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1979351211 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:37 AM UTC 24 112164457 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2516788116 Aug 25 04:07:34 AM UTC 24 Aug 25 04:07:37 AM UTC 24 20928862 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1887226159 Aug 25 04:07:47 AM UTC 24 Aug 25 04:07:49 AM UTC 24 12414099 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.2802229003 Aug 25 04:07:28 AM UTC 24 Aug 25 04:07:37 AM UTC 24 482720191 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3106625114 Aug 25 04:07:30 AM UTC 24 Aug 25 04:07:37 AM UTC 24 124085796 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2222777526 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:37 AM UTC 24 572339080 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.1830981382 Aug 25 04:07:36 AM UTC 24 Aug 25 04:07:37 AM UTC 24 68448310 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2013784854 Aug 25 04:07:34 AM UTC 24 Aug 25 04:07:38 AM UTC 24 32908381 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.4052873062 Aug 25 04:07:30 AM UTC 24 Aug 25 04:07:38 AM UTC 24 2090808644 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.1847979023 Aug 25 04:07:36 AM UTC 24 Aug 25 04:07:38 AM UTC 24 116104783 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.1759221245 Aug 25 04:07:37 AM UTC 24 Aug 25 04:07:39 AM UTC 24 32767426 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.964613824 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:39 AM UTC 24 1322497383 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1361774964 Aug 25 04:07:36 AM UTC 24 Aug 25 04:07:39 AM UTC 24 108478869 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1781424446 Aug 25 04:07:34 AM UTC 24 Aug 25 04:07:40 AM UTC 24 478366662 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3735536062 Aug 25 04:07:37 AM UTC 24 Aug 25 04:07:40 AM UTC 24 43210197 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.4111236420 Aug 25 04:07:30 AM UTC 24 Aug 25 04:07:40 AM UTC 24 199247403 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.3802189588 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:40 AM UTC 24 46904828 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.3434513459 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:40 AM UTC 24 40246746 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1349199287 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:40 AM UTC 24 56421336 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.2803029378 Aug 25 04:07:36 AM UTC 24 Aug 25 04:07:40 AM UTC 24 312715673 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.4088771655 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:41 AM UTC 24 12952218 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1797945576 Aug 25 04:07:37 AM UTC 24 Aug 25 04:07:41 AM UTC 24 530646031 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2376510550 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:41 AM UTC 24 25666761 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1703700551 Aug 25 04:07:39 AM UTC 24 Aug 25 04:07:41 AM UTC 24 85375963 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.1464287745 Aug 25 04:07:31 AM UTC 24 Aug 25 04:07:41 AM UTC 24 343520907 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3911851681 Aug 25 04:07:40 AM UTC 24 Aug 25 04:07:42 AM UTC 24 32661503 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1876168872 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:42 AM UTC 24 156002766 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3896276806 Aug 25 04:07:40 AM UTC 24 Aug 25 04:07:42 AM UTC 24 37872017 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.3251953833 Aug 25 04:07:37 AM UTC 24 Aug 25 04:07:42 AM UTC 24 56376975 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.732911210 Aug 25 04:07:37 AM UTC 24 Aug 25 04:07:43 AM UTC 24 120068885 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1773128536 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:43 AM UTC 24 25441554 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.4169276918 Aug 25 04:07:45 AM UTC 24 Aug 25 04:07:49 AM UTC 24 121756277 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1740316488 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:43 AM UTC 24 116216186 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.363935929 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:43 AM UTC 24 70158138 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.563190085 Aug 25 04:07:38 AM UTC 24 Aug 25 04:07:43 AM UTC 24 157838203 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2868280822 Aug 25 04:07:40 AM UTC 24 Aug 25 04:07:43 AM UTC 24 400672636 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.246104383 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:44 AM UTC 24 377288836 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4006050872 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:44 AM UTC 24 40726899 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.3981248562 Aug 25 04:07:42 AM UTC 24 Aug 25 04:07:45 AM UTC 24 171318340 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1862784812 Aug 25 04:07:43 AM UTC 24 Aug 25 04:07:49 AM UTC 24 853259832 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2252728428 Aug 25 04:07:40 AM UTC 24 Aug 25 04:07:45 AM UTC 24 567976485 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.765913674 Aug 25 04:07:43 AM UTC 24 Aug 25 04:07:45 AM UTC 24 16392129 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.479226122 Aug 25 04:07:40 AM UTC 24 Aug 25 04:07:45 AM UTC 24 521133285 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.401301925 Aug 25 04:07:42 AM UTC 24 Aug 25 04:07:45 AM UTC 24 72195835 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2577378352 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:46 AM UTC 24 2623734656 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1967139772 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:46 AM UTC 24 98716769 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.509365933 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:46 AM UTC 24 94640180 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.607563784 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:46 AM UTC 24 58198935 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3191797799 Aug 25 04:07:42 AM UTC 24 Aug 25 04:07:46 AM UTC 24 1082584852 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.298474471 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:46 AM UTC 24 16568522 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.1101168374 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:46 AM UTC 24 24321200 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3278782283 Aug 25 04:07:40 AM UTC 24 Aug 25 04:07:46 AM UTC 24 62393834 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.1691628111 Aug 25 04:07:43 AM UTC 24 Aug 25 04:07:47 AM UTC 24 647845096 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1452112106 Aug 25 04:07:34 AM UTC 24 Aug 25 04:07:47 AM UTC 24 157363033 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3244824249 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:47 AM UTC 24 168161708 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.4182757337 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:47 AM UTC 24 161809300 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2308404134 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:47 AM UTC 24 686998318 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3542743707 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:47 AM UTC 24 42528775 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1202552854 Aug 25 04:07:42 AM UTC 24 Aug 25 04:07:47 AM UTC 24 162648891 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1281714186 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:47 AM UTC 24 76685845 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3647594708 Aug 25 04:07:45 AM UTC 24 Aug 25 04:07:47 AM UTC 24 24762052 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1258294462 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:48 AM UTC 24 245294401 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.2043328189 Aug 25 04:07:45 AM UTC 24 Aug 25 04:07:48 AM UTC 24 13850358 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2075925215 Aug 25 04:07:45 AM UTC 24 Aug 25 04:07:48 AM UTC 24 143304529 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.2815192754 Aug 25 04:07:41 AM UTC 24 Aug 25 04:07:49 AM UTC 24 920369460 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.2388026963 Aug 25 04:07:47 AM UTC 24 Aug 25 04:07:49 AM UTC 24 49375074 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2265751425 Aug 25 04:07:31 AM UTC 24 Aug 25 04:07:49 AM UTC 24 1097422825 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1153288886 Aug 25 04:07:47 AM UTC 24 Aug 25 04:07:49 AM UTC 24 120620560 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1787073264 Aug 25 04:07:44 AM UTC 24 Aug 25 04:07:49 AM UTC 24 711558036 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.365394440 Aug 25 04:07:46 AM UTC 24 Aug 25 04:07:49 AM UTC 24 34469075 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2764824185 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:50 AM UTC 24 122469190 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.650483574 Aug 25 04:07:46 AM UTC 24 Aug 25 04:07:50 AM UTC 24 227098150 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2554531988 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:50 AM UTC 24 15302392 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.3559662475 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:50 AM UTC 24 29222227 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2397413920 Aug 25 04:07:46 AM UTC 24 Aug 25 04:07:51 AM UTC 24 104432562 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3289174149 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:51 AM UTC 24 23488452 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1747178263 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:51 AM UTC 24 114358332 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.494637415 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:51 AM UTC 24 12316481 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1046825075 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:51 AM UTC 24 466203665 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.71990934 Aug 25 04:07:50 AM UTC 24 Aug 25 04:07:52 AM UTC 24 49325675 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.639801364 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:52 AM UTC 24 29578209 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4149433161 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:52 AM UTC 24 71024306 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.3309042521 Aug 25 04:07:46 AM UTC 24 Aug 25 04:07:52 AM UTC 24 127347167 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1375236429 Aug 25 04:07:45 AM UTC 24 Aug 25 04:07:52 AM UTC 24 257610258 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1118272444 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:52 AM UTC 24 76293766 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3099554117 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:53 AM UTC 24 30565492 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.4247276051 Aug 25 04:07:50 AM UTC 24 Aug 25 04:07:53 AM UTC 24 66618260 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.560890243 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:53 AM UTC 24 117556015 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1944633839 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:53 AM UTC 24 148120031 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1182372050 Aug 25 04:07:33 AM UTC 24 Aug 25 04:07:53 AM UTC 24 3913075267 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.1739907605 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:53 AM UTC 24 29191265 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2192072945 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:53 AM UTC 24 177369277 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3863019234 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:53 AM UTC 24 81694970 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.731787798 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:54 AM UTC 24 39266447 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4222146050 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:54 AM UTC 24 272990552 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.990882064 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:54 AM UTC 24 42665962 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2414933838 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:54 AM UTC 24 539190172 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1436468458 Aug 25 04:07:53 AM UTC 24 Aug 25 04:07:54 AM UTC 24 28859696 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.3256127699 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:54 AM UTC 24 85105513 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2629658794 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:54 AM UTC 24 111715099 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2626638601 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:54 AM UTC 24 11939256 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.292112759 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:55 AM UTC 24 328731709 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.915066665 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:55 AM UTC 24 286129073 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1368902527 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:55 AM UTC 24 177952833 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2823152283 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:55 AM UTC 24 573423562 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3237890025 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:55 AM UTC 24 14126311 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2215472354 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:55 AM UTC 24 21110795 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2246741807 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 14489723 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1629695830 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 71130124 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.419069613 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 48725674 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3239215291 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 16771875 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3466817805 Aug 25 04:07:48 AM UTC 24 Aug 25 04:07:56 AM UTC 24 926705143 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3679782977 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 56219329 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.595103600 Aug 25 04:07:49 AM UTC 24 Aug 25 04:07:56 AM UTC 24 234129807 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.4140788020 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 22301401 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2588520928 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 28168557 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1287329416 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 48719319 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2320098832 Aug 25 04:07:54 AM UTC 24 Aug 25 04:07:56 AM UTC 24 11635701 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.1656153341 Aug 25 04:07:50 AM UTC 24 Aug 25 04:07:56 AM UTC 24 451403375 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.407198013 Aug 25 04:07:51 AM UTC 24 Aug 25 04:07:56 AM UTC 24 452487109 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3186975345 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:56 AM UTC 24 536468701 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1721603586 Aug 25 04:07:37 AM UTC 24 Aug 25 04:07:57 AM UTC 24 315512241 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2780495494 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:57 AM UTC 24 110073526 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4182419869 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:57 AM UTC 24 93671245 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1286968322 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 14754194 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2518701176 Aug 25 04:07:52 AM UTC 24 Aug 25 04:07:57 AM UTC 24 688239949 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.1738793214 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 42948506 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3957207945 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 21167035 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2015817691 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 40699362 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1146492804 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 13651989 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3813704180 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 13049626 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3865027679 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 17928624 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.310655679 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 10897772 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2794412153 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 15782307 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3846252373 Aug 25 04:07:55 AM UTC 24 Aug 25 04:07:57 AM UTC 24 17481108 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3083231570 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 25614966 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.975911413 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 12792499 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.1785926757 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 32564043 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.473909504 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 29585388 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1571351186 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 13905567 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3369935231 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 19222955 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3838481586 Aug 25 04:07:34 AM UTC 24 Aug 25 04:08:00 AM UTC 24 26243414656 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1567409077 Aug 25 04:07:50 AM UTC 24 Aug 25 04:10:33 AM UTC 24 64267330509 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.961118787 Aug 25 04:07:48 AM UTC 24 Aug 25 04:16:14 AM UTC 24 571358864135 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.764417326 Aug 25 04:07:37 AM UTC 24 Aug 25 04:27:13 AM UTC 24 192882895622 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.262737753 Aug 25 04:07:35 AM UTC 24 Aug 25 04:56:24 AM UTC 24 1155288338866 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_smoke.667135950
Short name T5
Test name
Test status
Simulation time 852346635 ps
CPU time 9.24 seconds
Started Aug 25 06:54:14 AM UTC 24
Finished Aug 25 06:54:34 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667135950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.667135950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_stress_all_with_rand_reset.982651586
Short name T11
Test name
Test status
Simulation time 3698158433 ps
CPU time 54.43 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:55:24 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98265158
6 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.982651586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.796202782
Short name T28
Test name
Test status
Simulation time 1013505748 ps
CPU time 63.49 seconds
Started Aug 25 06:54:17 AM UTC 24
Finished Aug 25 06:55:34 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796202782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.796202782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_stress_all_with_rand_reset.2089116725
Short name T18
Test name
Test status
Simulation time 7573711968 ps
CPU time 178.04 seconds
Started Aug 25 06:56:09 AM UTC 24
Finished Aug 25 06:59:11 AM UTC 24
Peak memory 268836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20891167
25 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2089116725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.3192676938
Short name T22
Test name
Test status
Simulation time 1491526891 ps
CPU time 1.54 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 06:54:32 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192676938 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3192676938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2747846762
Short name T174
Test name
Test status
Simulation time 5327186842 ps
CPU time 180.86 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:57:28 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747846762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2747846762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.186770042
Short name T1
Test name
Test status
Simulation time 5234562639 ps
CPU time 94.83 seconds
Started Aug 25 06:55:41 AM UTC 24
Finished Aug 25 06:57:19 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186770042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.186770042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3174329025
Short name T32
Test name
Test status
Simulation time 5139464092 ps
CPU time 337.03 seconds
Started Aug 25 06:55:46 AM UTC 24
Finished Aug 25 07:01:28 AM UTC 24
Peak memory 684584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31743290
25 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3174329025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3106625114
Short name T70
Test name
Test status
Simulation time 124085796 ps
CPU time 5.39 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106625114 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3106625114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_stress_all.175292166
Short name T15
Test name
Test status
Simulation time 82209380319 ps
CPU time 762.43 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 07:07:18 AM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175292166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.175292166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1223521497
Short name T99
Test name
Test status
Simulation time 30702289 ps
CPU time 1.14 seconds
Started Aug 25 04:07:31 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223521497 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1223521497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_error.2232532437
Short name T63
Test name
Test status
Simulation time 26327843135 ps
CPU time 156.07 seconds
Started Aug 25 06:54:15 AM UTC 24
Finished Aug 25 06:57:07 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232532437 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2232532437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.1607694258
Short name T54
Test name
Test status
Simulation time 3519314081 ps
CPU time 60.65 seconds
Started Aug 25 06:54:15 AM UTC 24
Finished Aug 25 06:55:30 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607694258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1607694258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.3776111616
Short name T29
Test name
Test status
Simulation time 660659646 ps
CPU time 41.37 seconds
Started Aug 25 06:57:54 AM UTC 24
Finished Aug 25 06:58:37 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776111616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3776111616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_stress_all.879230660
Short name T97
Test name
Test status
Simulation time 34876483471 ps
CPU time 1431.17 seconds
Started Aug 25 06:55:43 AM UTC 24
Finished Aug 25 07:19:53 AM UTC 24
Peak memory 665672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879230660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.879230660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.3539774384
Short name T85
Test name
Test status
Simulation time 2638253015 ps
CPU time 88.89 seconds
Started Aug 25 06:56:32 AM UTC 24
Finished Aug 25 06:58:03 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539774384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3539774384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1781424446
Short name T71
Test name
Test status
Simulation time 478366662 ps
CPU time 3.99 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781424446 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1781424446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_alert_test.1485681031
Short name T2
Test name
Test status
Simulation time 39146740 ps
CPU time 0.56 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:54:25 AM UTC 24
Peak memory 204528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485681031 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1485681031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_smoke.786085758
Short name T30
Test name
Test status
Simulation time 206497339 ps
CPU time 11.76 seconds
Started Aug 25 06:56:12 AM UTC 24
Finished Aug 25 06:56:25 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786085758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.786085758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1375236429
Short name T141
Test name
Test status
Simulation time 257610258 ps
CPU time 5.94 seconds
Started Aug 25 04:07:45 AM UTC 24
Finished Aug 25 04:07:52 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375236429 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1375236429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2823152283
Short name T616
Test name
Test status
Simulation time 573423562 ps
CPU time 5.54 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:55 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823152283 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2823152283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.2112223017
Short name T314
Test name
Test status
Simulation time 101020683500 ps
CPU time 881.39 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 07:09:23 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112223017 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2112223017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_error.233295736
Short name T192
Test name
Test status
Simulation time 1444534414 ps
CPU time 22.91 seconds
Started Aug 25 06:57:23 AM UTC 24
Finished Aug 25 06:57:48 AM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233295736 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.233295736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.4111236420
Short name T103
Test name
Test status
Simulation time 199247403 ps
CPU time 7.87 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 207596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111236420 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4111236420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.4052873062
Short name T542
Test name
Test status
Simulation time 2090808644 ps
CPU time 6.15 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:38 AM UTC 24
Peak memory 207832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052873062 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4052873062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.730382109
Short name T535
Test name
Test status
Simulation time 61742924 ps
CPU time 1.09 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:33 AM UTC 24
Peak memory 205864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730382109 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.730382109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3656765776
Short name T72
Test name
Test status
Simulation time 76413844 ps
CPU time 1.97 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3656765776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.3656765776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.1033532985
Short name T112
Test name
Test status
Simulation time 45031892 ps
CPU time 0.97 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:33 AM UTC 24
Peak memory 205392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033532985 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1033532985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.1148378123
Short name T534
Test name
Test status
Simulation time 29780094 ps
CPU time 0.86 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:33 AM UTC 24
Peak memory 204716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148378123 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1148378123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.462059307
Short name T113
Test name
Test status
Simulation time 79781559 ps
CPU time 2.44 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 207884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462059307 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.462059307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.2802229003
Short name T540
Test name
Test status
Simulation time 482720191 ps
CPU time 5.94 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802229003 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2802229003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.2329795803
Short name T68
Test name
Test status
Simulation time 1682991213 ps
CPU time 6.05 seconds
Started Aug 25 04:07:28 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329795803 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2329795803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.1464287745
Short name T104
Test name
Test status
Simulation time 343520907 ps
CPU time 8.44 seconds
Started Aug 25 04:07:31 AM UTC 24
Finished Aug 25 04:07:41 AM UTC 24
Peak memory 207920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464287745 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1464287745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2265751425
Short name T584
Test name
Test status
Simulation time 1097422825 ps
CPU time 15.97 seconds
Started Aug 25 04:07:31 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 207864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265751425 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2265751425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.902985690
Short name T536
Test name
Test status
Simulation time 36442421 ps
CPU time 1.45 seconds
Started Aug 25 04:07:31 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902985690 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.902985690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.970680511
Short name T74
Test name
Test status
Simulation time 52985350 ps
CPU time 1.7 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 206664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=970680511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_re
set.970680511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.707167401
Short name T82
Test name
Test status
Simulation time 15897758 ps
CPU time 0.91 seconds
Started Aug 25 04:07:31 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 203400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707167401 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.707167401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2262576335
Short name T114
Test name
Test status
Simulation time 183286394 ps
CPU time 1.65 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 206796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262576335 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.2262576335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2342998058
Short name T73
Test name
Test status
Simulation time 324012210 ps
CPU time 2.43 seconds
Started Aug 25 04:07:30 AM UTC 24
Finished Aug 25 04:07:34 AM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342998058 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2342998058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1258294462
Short name T580
Test name
Test status
Simulation time 245294401 ps
CPU time 2.47 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:48 AM UTC 24
Peak memory 217956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1258294462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.1258294462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.607563784
Short name T568
Test name
Test status
Simulation time 58198935 ps
CPU time 1.03 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607563784 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.607563784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.765913674
Short name T564
Test name
Test status
Simulation time 16392129 ps
CPU time 0.92 seconds
Started Aug 25 04:07:43 AM UTC 24
Finished Aug 25 04:07:45 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765913674 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.765913674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3244824249
Short name T574
Test name
Test status
Simulation time 168161708 ps
CPU time 1.71 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244824249 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.3244824249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1862784812
Short name T562
Test name
Test status
Simulation time 853259832 ps
CPU time 5.4 seconds
Started Aug 25 04:07:43 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862784812 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1862784812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.1691628111
Short name T572
Test name
Test status
Simulation time 647845096 ps
CPU time 2.54 seconds
Started Aug 25 04:07:43 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691628111 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1691628111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2075925215
Short name T582
Test name
Test status
Simulation time 143304529 ps
CPU time 1.83 seconds
Started Aug 25 04:07:45 AM UTC 24
Finished Aug 25 04:07:48 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2075925215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.2075925215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.1101168374
Short name T109
Test name
Test status
Simulation time 24321200 ps
CPU time 1.04 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101168374 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1101168374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.298474471
Short name T570
Test name
Test status
Simulation time 16568522 ps
CPU time 0.95 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298474471 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.298474471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3542743707
Short name T576
Test name
Test status
Simulation time 42528775 ps
CPU time 1.62 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 206792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542743707 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.3542743707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1281714186
Short name T578
Test name
Test status
Simulation time 76685845 ps
CPU time 2.25 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281714186 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1281714186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1787073264
Short name T586
Test name
Test status
Simulation time 711558036 ps
CPU time 4.01 seconds
Started Aug 25 04:07:44 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787073264 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1787073264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.365394440
Short name T587
Test name
Test status
Simulation time 34469075 ps
CPU time 1.59 seconds
Started Aug 25 04:07:46 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 206664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=365394440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_r
eset.365394440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.2043328189
Short name T581
Test name
Test status
Simulation time 13850358 ps
CPU time 0.99 seconds
Started Aug 25 04:07:45 AM UTC 24
Finished Aug 25 04:07:48 AM UTC 24
Peak memory 206948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043328189 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2043328189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3647594708
Short name T579
Test name
Test status
Simulation time 24762052 ps
CPU time 0.84 seconds
Started Aug 25 04:07:45 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647594708 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3647594708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.650483574
Short name T589
Test name
Test status
Simulation time 227098150 ps
CPU time 2.55 seconds
Started Aug 25 04:07:46 AM UTC 24
Finished Aug 25 04:07:50 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650483574 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.650483574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.4169276918
Short name T555
Test name
Test status
Simulation time 121756277 ps
CPU time 2.29 seconds
Started Aug 25 04:07:45 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169276918 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.4169276918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.961118787
Short name T654
Test name
Test status
Simulation time 571358864135 ps
CPU time 499 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:16:14 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=961118787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_r
eset.961118787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1887226159
Short name T116
Test name
Test status
Simulation time 12414099 ps
CPU time 0.98 seconds
Started Aug 25 04:07:47 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887226159 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1887226159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.2388026963
Short name T583
Test name
Test status
Simulation time 49375074 ps
CPU time 0.9 seconds
Started Aug 25 04:07:47 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388026963 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2388026963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1153288886
Short name T585
Test name
Test status
Simulation time 120620560 ps
CPU time 1.24 seconds
Started Aug 25 04:07:47 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 206672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153288886 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.1153288886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2397413920
Short name T591
Test name
Test status
Simulation time 104432562 ps
CPU time 2.67 seconds
Started Aug 25 04:07:46 AM UTC 24
Finished Aug 25 04:07:51 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397413920 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2397413920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.3309042521
Short name T143
Test name
Test status
Simulation time 127347167 ps
CPU time 4.37 seconds
Started Aug 25 04:07:46 AM UTC 24
Finished Aug 25 04:07:52 AM UTC 24
Peak memory 208000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309042521 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3309042521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1118272444
Short name T597
Test name
Test status
Simulation time 76293766 ps
CPU time 3.5 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:52 AM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1118272444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.1118272444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.3559662475
Short name T110
Test name
Test status
Simulation time 29222227 ps
CPU time 1.29 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:50 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559662475 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3559662475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2764824185
Short name T588
Test name
Test status
Simulation time 122469190 ps
CPU time 0.81 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:50 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764824185 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2764824185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3289174149
Short name T592
Test name
Test status
Simulation time 23488452 ps
CPU time 1.61 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:51 AM UTC 24
Peak memory 206548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289174149 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.3289174149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1747178263
Short name T593
Test name
Test status
Simulation time 114358332 ps
CPU time 2.06 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:51 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747178263 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1747178263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1046825075
Short name T137
Test name
Test status
Simulation time 466203665 ps
CPU time 2.58 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:51 AM UTC 24
Peak memory 207920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046825075 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1046825075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3863019234
Short name T604
Test name
Test status
Simulation time 81694970 ps
CPU time 2.79 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 218348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3863019234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.3863019234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.639801364
Short name T596
Test name
Test status
Simulation time 29578209 ps
CPU time 1.24 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:52 AM UTC 24
Peak memory 206472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639801364 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.639801364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2554531988
Short name T590
Test name
Test status
Simulation time 15302392 ps
CPU time 0.86 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:50 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554531988 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2554531988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4222146050
Short name T606
Test name
Test status
Simulation time 272990552 ps
CPU time 3.25 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222146050 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.4222146050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3466817805
Short name T623
Test name
Test status
Simulation time 926705143 ps
CPU time 6.41 seconds
Started Aug 25 04:07:48 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 207832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466817805 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3466817805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1567409077
Short name T653
Test name
Test status
Simulation time 64267330509 ps
CPU time 160.26 seconds
Started Aug 25 04:07:50 AM UTC 24
Finished Aug 25 04:10:33 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1567409077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.1567409077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4149433161
Short name T111
Test name
Test status
Simulation time 71024306 ps
CPU time 1.23 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:52 AM UTC 24
Peak memory 206320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149433161 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4149433161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.494637415
Short name T594
Test name
Test status
Simulation time 12316481 ps
CPU time 0.89 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:51 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494637415 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.494637415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.560890243
Short name T600
Test name
Test status
Simulation time 117556015 ps
CPU time 2.33 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560890243 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.560890243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.595103600
Short name T625
Test name
Test status
Simulation time 234129807 ps
CPU time 5.17 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595103600 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.595103600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1944633839
Short name T144
Test name
Test status
Simulation time 148120031 ps
CPU time 2.45 seconds
Started Aug 25 04:07:49 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944633839 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1944633839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.731787798
Short name T605
Test name
Test status
Simulation time 39266447 ps
CPU time 1.73 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=731787798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_r
eset.731787798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.1739907605
Short name T602
Test name
Test status
Simulation time 29191265 ps
CPU time 1.36 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739907605 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1739907605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.71990934
Short name T595
Test name
Test status
Simulation time 49325675 ps
CPU time 0.76 seconds
Started Aug 25 04:07:50 AM UTC 24
Finished Aug 25 04:07:52 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71990934 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.71990934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.915066665
Short name T614
Test name
Test status
Simulation time 286129073 ps
CPU time 2.9 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:55 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915066665 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.915066665
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.4247276051
Short name T599
Test name
Test status
Simulation time 66618260 ps
CPU time 2.13 seconds
Started Aug 25 04:07:50 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 207808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247276051 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4247276051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.1656153341
Short name T139
Test name
Test status
Simulation time 451403375 ps
CPU time 5.28 seconds
Started Aug 25 04:07:50 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656153341 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1656153341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1368902527
Short name T615
Test name
Test status
Simulation time 177952833 ps
CPU time 2.66 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:55 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1368902527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.1368902527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2192072945
Short name T603
Test name
Test status
Simulation time 177369277 ps
CPU time 1.16 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192072945 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2192072945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3099554117
Short name T598
Test name
Test status
Simulation time 30565492 ps
CPU time 0.77 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099554117 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3099554117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.292112759
Short name T613
Test name
Test status
Simulation time 328731709 ps
CPU time 2.56 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:55 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292112759 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.292112759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2414933838
Short name T608
Test name
Test status
Simulation time 539190172 ps
CPU time 2.21 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 207596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414933838 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2414933838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.407198013
Short name T630
Test name
Test status
Simulation time 452487109 ps
CPU time 4.27 seconds
Started Aug 25 04:07:51 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407198013 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.407198013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4182419869
Short name T634
Test name
Test status
Simulation time 93671245 ps
CPU time 3.37 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4182419869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.4182419869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2629658794
Short name T611
Test name
Test status
Simulation time 111715099 ps
CPU time 1 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 205656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629658794 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2629658794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.990882064
Short name T607
Test name
Test status
Simulation time 42665962 ps
CPU time 0.84 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990882064 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.990882064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2780495494
Short name T633
Test name
Test status
Simulation time 110073526 ps
CPU time 3.27 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780495494 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.2780495494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3186975345
Short name T631
Test name
Test status
Simulation time 536468701 ps
CPU time 3.02 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186975345 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3186975345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2518701176
Short name T636
Test name
Test status
Simulation time 688239949 ps
CPU time 3.54 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518701176 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2518701176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.246104383
Short name T107
Test name
Test status
Simulation time 377288836 ps
CPU time 8.96 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:44 AM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246104383 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.246104383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1182372050
Short name T601
Test name
Test status
Simulation time 3913075267 ps
CPU time 18.64 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:53 AM UTC 24
Peak memory 207800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182372050 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1182372050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1225873378
Short name T83
Test name
Test status
Simulation time 122121528 ps
CPU time 1.31 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:35 AM UTC 24
Peak memory 206972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225873378 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1225873378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2609189984
Short name T538
Test name
Test status
Simulation time 35197716 ps
CPU time 1.71 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2609189984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.2609189984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2931372788
Short name T100
Test name
Test status
Simulation time 16072743 ps
CPU time 1.3 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 206192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931372788 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2931372788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3870311457
Short name T537
Test name
Test status
Simulation time 102524478 ps
CPU time 0.87 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:35 AM UTC 24
Peak memory 203584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870311457 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3870311457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2222777526
Short name T117
Test name
Test status
Simulation time 572339080 ps
CPU time 2.82 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222777526 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.2222777526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2616970373
Short name T84
Test name
Test status
Simulation time 29855040 ps
CPU time 1.7 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616970373 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2616970373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1979351211
Short name T69
Test name
Test status
Simulation time 112164457 ps
CPU time 2.61 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979351211 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1979351211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.3256127699
Short name T610
Test name
Test status
Simulation time 85105513 ps
CPU time 0.84 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 203356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256127699 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3256127699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2626638601
Short name T612
Test name
Test status
Simulation time 11939256 ps
CPU time 0.9 seconds
Started Aug 25 04:07:52 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626638601 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2626638601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1436468458
Short name T609
Test name
Test status
Simulation time 28859696 ps
CPU time 0.75 seconds
Started Aug 25 04:07:53 AM UTC 24
Finished Aug 25 04:07:54 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436468458 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1436468458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2215472354
Short name T618
Test name
Test status
Simulation time 21110795 ps
CPU time 0.86 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:55 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215472354 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2215472354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3237890025
Short name T617
Test name
Test status
Simulation time 14126311 ps
CPU time 0.8 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:55 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237890025 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3237890025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1629695830
Short name T620
Test name
Test status
Simulation time 71130124 ps
CPU time 0.9 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629695830 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1629695830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.419069613
Short name T621
Test name
Test status
Simulation time 48725674 ps
CPU time 0.96 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419069613 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.419069613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2246741807
Short name T619
Test name
Test status
Simulation time 14489723 ps
CPU time 0.82 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246741807 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2246741807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3239215291
Short name T622
Test name
Test status
Simulation time 16771875 ps
CPU time 0.9 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239215291 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3239215291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3679782977
Short name T624
Test name
Test status
Simulation time 56219329 ps
CPU time 0.83 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679782977 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3679782977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1452112106
Short name T573
Test name
Test status
Simulation time 157363033 ps
CPU time 10.87 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452112106 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1452112106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3838481586
Short name T652
Test name
Test status
Simulation time 26243414656 ps
CPU time 23.86 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:08:00 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838481586 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3838481586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2516788116
Short name T101
Test name
Test status
Simulation time 20928862 ps
CPU time 1.43 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516788116 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2516788116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.262737753
Short name T656
Test name
Test status
Simulation time 1155288338866 ps
CPU time 2888.77 seconds
Started Aug 25 04:07:35 AM UTC 24
Finished Aug 25 04:56:24 AM UTC 24
Peak memory 243932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=262737753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_re
set.262737753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3117650461
Short name T115
Test name
Test status
Simulation time 19580689 ps
CPU time 1.05 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117650461 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3117650461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3511753276
Short name T539
Test name
Test status
Simulation time 20559204 ps
CPU time 0.9 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:07:36 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511753276 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3511753276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2013784854
Short name T118
Test name
Test status
Simulation time 32908381 ps
CPU time 2.21 seconds
Started Aug 25 04:07:34 AM UTC 24
Finished Aug 25 04:07:38 AM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013784854 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.2013784854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.964613824
Short name T544
Test name
Test status
Simulation time 1322497383 ps
CPU time 4.64 seconds
Started Aug 25 04:07:33 AM UTC 24
Finished Aug 25 04:07:39 AM UTC 24
Peak memory 208000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964613824 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.964613824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.4140788020
Short name T626
Test name
Test status
Simulation time 22301401 ps
CPU time 0.84 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140788020 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4140788020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2588520928
Short name T627
Test name
Test status
Simulation time 28168557 ps
CPU time 0.85 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588520928 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2588520928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1287329416
Short name T628
Test name
Test status
Simulation time 48719319 ps
CPU time 0.91 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287329416 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1287329416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2320098832
Short name T629
Test name
Test status
Simulation time 11635701 ps
CPU time 0.86 seconds
Started Aug 25 04:07:54 AM UTC 24
Finished Aug 25 04:07:56 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320098832 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2320098832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1286968322
Short name T635
Test name
Test status
Simulation time 14754194 ps
CPU time 0.8 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286968322 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1286968322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3957207945
Short name T638
Test name
Test status
Simulation time 21167035 ps
CPU time 0.88 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957207945 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3957207945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.1738793214
Short name T637
Test name
Test status
Simulation time 42948506 ps
CPU time 0.86 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738793214 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1738793214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1146492804
Short name T640
Test name
Test status
Simulation time 13651989 ps
CPU time 0.85 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146492804 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1146492804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2015817691
Short name T639
Test name
Test status
Simulation time 40699362 ps
CPU time 0.84 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015817691 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2015817691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3865027679
Short name T642
Test name
Test status
Simulation time 17928624 ps
CPU time 0.91 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865027679 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3865027679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.3251953833
Short name T106
Test name
Test status
Simulation time 56376975 ps
CPU time 4.41 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:07:42 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251953833 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3251953833
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1721603586
Short name T632
Test name
Test status
Simulation time 315512241 ps
CPU time 18.55 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721603586 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1721603586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.1847979023
Short name T102
Test name
Test status
Simulation time 116104783 ps
CPU time 1.24 seconds
Started Aug 25 04:07:36 AM UTC 24
Finished Aug 25 04:07:38 AM UTC 24
Peak memory 206836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847979023 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1847979023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.764417326
Short name T655
Test name
Test status
Simulation time 192882895622 ps
CPU time 1160.88 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:27:13 AM UTC 24
Peak memory 240180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=764417326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_re
set.764417326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.1759221245
Short name T543
Test name
Test status
Simulation time 32767426 ps
CPU time 1 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:07:39 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759221245 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1759221245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.1830981382
Short name T541
Test name
Test status
Simulation time 68448310 ps
CPU time 0.84 seconds
Started Aug 25 04:07:36 AM UTC 24
Finished Aug 25 04:07:37 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830981382 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1830981382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3735536062
Short name T119
Test name
Test status
Simulation time 43210197 ps
CPU time 1.58 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735536062 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.3735536062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.2803029378
Short name T548
Test name
Test status
Simulation time 312715673 ps
CPU time 3.85 seconds
Started Aug 25 04:07:36 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803029378 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2803029378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1361774964
Short name T138
Test name
Test status
Simulation time 108478869 ps
CPU time 2.66 seconds
Started Aug 25 04:07:36 AM UTC 24
Finished Aug 25 04:07:39 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361774964 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1361774964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3813704180
Short name T641
Test name
Test status
Simulation time 13049626 ps
CPU time 0.85 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813704180 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3813704180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.310655679
Short name T643
Test name
Test status
Simulation time 10897772 ps
CPU time 0.78 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310655679 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.310655679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3846252373
Short name T645
Test name
Test status
Simulation time 17481108 ps
CPU time 0.95 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846252373 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3846252373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2794412153
Short name T644
Test name
Test status
Simulation time 15782307 ps
CPU time 0.79 seconds
Started Aug 25 04:07:55 AM UTC 24
Finished Aug 25 04:07:57 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794412153 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2794412153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.1785926757
Short name T648
Test name
Test status
Simulation time 32564043 ps
CPU time 0.89 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785926757 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1785926757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.975911413
Short name T647
Test name
Test status
Simulation time 12792499 ps
CPU time 0.85 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975911413 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.975911413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3083231570
Short name T646
Test name
Test status
Simulation time 25614966 ps
CPU time 0.88 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083231570 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3083231570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.473909504
Short name T649
Test name
Test status
Simulation time 29585388 ps
CPU time 0.84 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473909504 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.473909504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1571351186
Short name T650
Test name
Test status
Simulation time 13905567 ps
CPU time 0.86 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571351186 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1571351186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3369935231
Short name T651
Test name
Test status
Simulation time 19222955 ps
CPU time 0.96 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369935231 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3369935231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1740316488
Short name T556
Test name
Test status
Simulation time 116216186 ps
CPU time 3.71 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:43 AM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1740316488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.1740316488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.3434513459
Short name T546
Test name
Test status
Simulation time 40246746 ps
CPU time 1.01 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434513459 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3434513459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.3802189588
Short name T545
Test name
Test status
Simulation time 46904828 ps
CPU time 0.91 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802189588 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3802189588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2376510550
Short name T550
Test name
Test status
Simulation time 25666761 ps
CPU time 1.63 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:41 AM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376510550 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.2376510550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.732911210
Short name T553
Test name
Test status
Simulation time 120068885 ps
CPU time 4.4 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:07:43 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732911210 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.732911210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1797945576
Short name T142
Test name
Test status
Simulation time 530646031 ps
CPU time 2.63 seconds
Started Aug 25 04:07:37 AM UTC 24
Finished Aug 25 04:07:41 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797945576 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1797945576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3278782283
Short name T571
Test name
Test status
Simulation time 62393834 ps
CPU time 5.47 seconds
Started Aug 25 04:07:40 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3278782283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.3278782283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.4088771655
Short name T549
Test name
Test status
Simulation time 12952218 ps
CPU time 1.01 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:41 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088771655 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4088771655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1349199287
Short name T547
Test name
Test status
Simulation time 56421336 ps
CPU time 0.87 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:40 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349199287 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1349199287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1703700551
Short name T551
Test name
Test status
Simulation time 85375963 ps
CPU time 1.66 seconds
Started Aug 25 04:07:39 AM UTC 24
Finished Aug 25 04:07:41 AM UTC 24
Peak memory 206736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703700551 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.1703700551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.563190085
Short name T558
Test name
Test status
Simulation time 157838203 ps
CPU time 3.9 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:43 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563190085 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.563190085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1876168872
Short name T145
Test name
Test status
Simulation time 156002766 ps
CPU time 2.49 seconds
Started Aug 25 04:07:38 AM UTC 24
Finished Aug 25 04:07:42 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876168872 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1876168872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4006050872
Short name T560
Test name
Test status
Simulation time 40726899 ps
CPU time 1.83 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:44 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4006050872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.4006050872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3896276806
Short name T105
Test name
Test status
Simulation time 37872017 ps
CPU time 1.16 seconds
Started Aug 25 04:07:40 AM UTC 24
Finished Aug 25 04:07:42 AM UTC 24
Peak memory 206892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896276806 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3896276806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3911851681
Short name T552
Test name
Test status
Simulation time 32661503 ps
CPU time 0.83 seconds
Started Aug 25 04:07:40 AM UTC 24
Finished Aug 25 04:07:42 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911851681 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3911851681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2868280822
Short name T559
Test name
Test status
Simulation time 400672636 ps
CPU time 2.35 seconds
Started Aug 25 04:07:40 AM UTC 24
Finished Aug 25 04:07:43 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868280822 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.2868280822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2252728428
Short name T563
Test name
Test status
Simulation time 567976485 ps
CPU time 3.77 seconds
Started Aug 25 04:07:40 AM UTC 24
Finished Aug 25 04:07:45 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252728428 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2252728428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.479226122
Short name T136
Test name
Test status
Simulation time 521133285 ps
CPU time 4.12 seconds
Started Aug 25 04:07:40 AM UTC 24
Finished Aug 25 04:07:45 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479226122 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.479226122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.509365933
Short name T567
Test name
Test status
Simulation time 94640180 ps
CPU time 3.46 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=509365933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_re
set.509365933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.363935929
Short name T557
Test name
Test status
Simulation time 70158138 ps
CPU time 1.07 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:43 AM UTC 24
Peak memory 206656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363935929 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.363935929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1773128536
Short name T554
Test name
Test status
Simulation time 25441554 ps
CPU time 0.87 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:43 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773128536 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1773128536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2577378352
Short name T565
Test name
Test status
Simulation time 2623734656 ps
CPU time 3.33 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 208128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577378352 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.2577378352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.4182757337
Short name T575
Test name
Test status
Simulation time 161809300 ps
CPU time 4.75 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182757337 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4182757337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.2815192754
Short name T140
Test name
Test status
Simulation time 920369460 ps
CPU time 6.42 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:49 AM UTC 24
Peak memory 208048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815192754 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2815192754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3191797799
Short name T569
Test name
Test status
Simulation time 1082584852 ps
CPU time 2.37 seconds
Started Aug 25 04:07:42 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3191797799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3191797799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.401301925
Short name T108
Test name
Test status
Simulation time 72195835 ps
CPU time 1.29 seconds
Started Aug 25 04:07:42 AM UTC 24
Finished Aug 25 04:07:45 AM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401301925 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.401301925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.3981248562
Short name T561
Test name
Test status
Simulation time 171318340 ps
CPU time 0.89 seconds
Started Aug 25 04:07:42 AM UTC 24
Finished Aug 25 04:07:45 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981248562 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3981248562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1202552854
Short name T577
Test name
Test status
Simulation time 162648891 ps
CPU time 3.6 seconds
Started Aug 25 04:07:42 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202552854 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.1202552854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1967139772
Short name T566
Test name
Test status
Simulation time 98716769 ps
CPU time 3.41 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:46 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967139772 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1967139772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2308404134
Short name T146
Test name
Test status
Simulation time 686998318 ps
CPU time 4.5 seconds
Started Aug 25 04:07:41 AM UTC 24
Finished Aug 25 04:07:47 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308404134 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2308404134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.1966858960
Short name T160
Test name
Test status
Simulation time 1117611949 ps
CPU time 83.06 seconds
Started Aug 25 06:54:14 AM UTC 24
Finished Aug 25 06:55:49 AM UTC 24
Peak memory 207368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966858960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1966858960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.4099093627
Short name T156
Test name
Test status
Simulation time 1095000783 ps
CPU time 277.74 seconds
Started Aug 25 06:54:14 AM UTC 24
Finished Aug 25 06:58:56 AM UTC 24
Peak memory 629164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099093627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4099093627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_long_msg.970554557
Short name T193
Test name
Test status
Simulation time 12984477869 ps
CPU time 221.06 seconds
Started Aug 25 06:54:14 AM UTC 24
Finished Aug 25 06:57:59 AM UTC 24
Peak memory 215756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970554557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.970554557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.2104514127
Short name T3
Test name
Test status
Simulation time 36517915 ps
CPU time 0.79 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:54:25 AM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104514127 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2104514127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_stress_all.1107945669
Short name T508
Test name
Test status
Simulation time 47752560626 ps
CPU time 2937.18 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 07:43:55 AM UTC 24
Peak memory 789028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107945669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1107945669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.467056252
Short name T12
Test name
Test status
Simulation time 5466548715 ps
CPU time 69.15 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:55:34 AM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46705625
2 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.467056252
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.342307033
Short name T182
Test name
Test status
Simulation time 7470604670 ps
CPU time 109.13 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:56:21 AM UTC 24
Peak memory 206852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342307033 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.342307033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2560813377
Short name T173
Test name
Test status
Simulation time 3800831982 ps
CPU time 76.06 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:55:41 AM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560813377 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2560813377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.2498502496
Short name T65
Test name
Test status
Simulation time 8358015078 ps
CPU time 102.34 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:56:08 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498502496 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2498502496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.2886462009
Short name T522
Test name
Test status
Simulation time 186801039893 ps
CPU time 3423.49 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 07:52:21 AM UTC 24
Peak memory 221308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886462009 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2886462009
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.1978390862
Short name T132
Test name
Test status
Simulation time 14456246253 ps
CPU time 89.32 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:56:01 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978390862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1978390862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_alert_test.2173752057
Short name T14
Test name
Test status
Simulation time 18030731 ps
CPU time 0.75 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173752057 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2173752057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.3914751487
Short name T55
Test name
Test status
Simulation time 2445532953 ps
CPU time 98.93 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:56:05 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914751487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3914751487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.3772542380
Short name T282
Test name
Test status
Simulation time 10775630864 ps
CPU time 695.99 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 07:06:10 AM UTC 24
Peak memory 729364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772542380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3772542380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_error.2820348987
Short name T199
Test name
Test status
Simulation time 49418148730 ps
CPU time 275.15 seconds
Started Aug 25 06:54:17 AM UTC 24
Finished Aug 25 06:59:09 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820348987 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2820348987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.3399153146
Short name T20
Test name
Test status
Simulation time 74638780 ps
CPU time 1.32 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399153146 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3399153146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_smoke.1355739096
Short name T4
Test name
Test status
Simulation time 1876038516 ps
CPU time 6.24 seconds
Started Aug 25 06:54:16 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355739096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1355739096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.176448159
Short name T58
Test name
Test status
Simulation time 1739059929 ps
CPU time 97.8 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:56:08 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176448159 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.176448159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.1429652581
Short name T183
Test name
Test status
Simulation time 16025414101 ps
CPU time 114.31 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:56:22 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429652581 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1429652581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.294082738
Short name T180
Test name
Test status
Simulation time 21929869920 ps
CPU time 105.42 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:56:16 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294082738 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.294082738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.489307619
Short name T304
Test name
Test status
Simulation time 99155858623 ps
CPU time 852.55 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 07:08:53 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489307619 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.489307619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.3928423594
Short name T509
Test name
Test status
Simulation time 165643812481 ps
CPU time 2983.57 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 07:44:52 AM UTC 24
Peak memory 215884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928423594 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3928423594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.1705282784
Short name T506
Test name
Test status
Simulation time 72100383727 ps
CPU time 2836.79 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 07:42:24 AM UTC 24
Peak memory 223000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705282784 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1705282784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.3971350987
Short name T26
Test name
Test status
Simulation time 2223228917 ps
CPU time 39.03 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:55:09 AM UTC 24
Peak memory 206856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971350987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3971350987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_alert_test.992648739
Short name T191
Test name
Test status
Simulation time 25284614 ps
CPU time 0.83 seconds
Started Aug 25 06:57:35 AM UTC 24
Finished Aug 25 06:57:37 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992648739 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.992648739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.2622086718
Short name T206
Test name
Test status
Simulation time 6554183044 ps
CPU time 133.26 seconds
Started Aug 25 06:57:20 AM UTC 24
Finished Aug 25 06:59:36 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622086718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2622086718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.530972306
Short name T190
Test name
Test status
Simulation time 247998900 ps
CPU time 6.05 seconds
Started Aug 25 06:57:22 AM UTC 24
Finished Aug 25 06:57:29 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530972306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.530972306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.3718229380
Short name T351
Test name
Test status
Simulation time 77067420169 ps
CPU time 980.22 seconds
Started Aug 25 06:57:22 AM UTC 24
Finished Aug 25 07:13:55 AM UTC 24
Peak memory 746012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718229380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3718229380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_long_msg.1385330776
Short name T87
Test name
Test status
Simulation time 8966969868 ps
CPU time 59.1 seconds
Started Aug 25 06:57:16 AM UTC 24
Finished Aug 25 06:58:17 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385330776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1385330776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_smoke.1770866337
Short name T172
Test name
Test status
Simulation time 164477474 ps
CPU time 5.23 seconds
Started Aug 25 06:57:16 AM UTC 24
Finished Aug 25 06:57:22 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770866337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1770866337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_stress_all.214511861
Short name T310
Test name
Test status
Simulation time 14054658133 ps
CPU time 690.15 seconds
Started Aug 25 06:57:30 AM UTC 24
Finished Aug 25 07:09:10 AM UTC 24
Peak memory 712928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214511861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.214511861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.205530493
Short name T128
Test name
Test status
Simulation time 3796814554 ps
CPU time 24.13 seconds
Started Aug 25 06:57:29 AM UTC 24
Finished Aug 25 06:57:55 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205530493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.205530493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_alert_test.577086948
Short name T88
Test name
Test status
Simulation time 13672468 ps
CPU time 0.85 seconds
Started Aug 25 06:58:18 AM UTC 24
Finished Aug 25 06:58:20 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577086948 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.577086948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.2580116148
Short name T198
Test name
Test status
Simulation time 4532131162 ps
CPU time 78.38 seconds
Started Aug 25 06:57:46 AM UTC 24
Finished Aug 25 06:59:06 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580116148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2580116148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.365201993
Short name T278
Test name
Test status
Simulation time 1925652997 ps
CPU time 473.14 seconds
Started Aug 25 06:57:49 AM UTC 24
Finished Aug 25 07:05:49 AM UTC 24
Peak memory 469368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365201993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.365201993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_error.3543828995
Short name T238
Test name
Test status
Simulation time 12220491222 ps
CPU time 243.38 seconds
Started Aug 25 06:57:56 AM UTC 24
Finished Aug 25 07:02:04 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543828995 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3543828995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_long_msg.738859211
Short name T222
Test name
Test status
Simulation time 12910795906 ps
CPU time 158.21 seconds
Started Aug 25 06:57:45 AM UTC 24
Finished Aug 25 07:00:27 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738859211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.738859211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_smoke.3200873188
Short name T151
Test name
Test status
Simulation time 875545363 ps
CPU time 13.35 seconds
Started Aug 25 06:57:38 AM UTC 24
Finished Aug 25 06:57:53 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200873188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3200873188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_stress_all.288404287
Short name T518
Test name
Test status
Simulation time 24575322575 ps
CPU time 3056.5 seconds
Started Aug 25 06:58:04 AM UTC 24
Finished Aug 25 07:49:40 AM UTC 24
Peak memory 805088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288404287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.288404287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.456940780
Short name T92
Test name
Test status
Simulation time 625517102 ps
CPU time 41.31 seconds
Started Aug 25 06:58:01 AM UTC 24
Finished Aug 25 06:58:44 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456940780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.456940780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_alert_test.871276848
Short name T194
Test name
Test status
Simulation time 14498357 ps
CPU time 0.87 seconds
Started Aug 25 06:58:57 AM UTC 24
Finished Aug 25 06:58:59 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871276848 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.871276848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.2400698740
Short name T208
Test name
Test status
Simulation time 6648163778 ps
CPU time 66.46 seconds
Started Aug 25 06:58:30 AM UTC 24
Finished Aug 25 06:59:39 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400698740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2400698740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.2373656362
Short name T205
Test name
Test status
Simulation time 10676476860 ps
CPU time 50 seconds
Started Aug 25 06:58:37 AM UTC 24
Finished Aug 25 06:59:29 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373656362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2373656362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.3967447714
Short name T431
Test name
Test status
Simulation time 19356570373 ps
CPU time 1397.28 seconds
Started Aug 25 06:58:31 AM UTC 24
Finished Aug 25 07:22:06 AM UTC 24
Peak memory 795056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967447714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3967447714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_error.3626004284
Short name T251
Test name
Test status
Simulation time 7027912646 ps
CPU time 250.15 seconds
Started Aug 25 06:58:42 AM UTC 24
Finished Aug 25 07:02:56 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626004284 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3626004284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2863954884
Short name T214
Test name
Test status
Simulation time 4750181425 ps
CPU time 100.62 seconds
Started Aug 25 06:58:21 AM UTC 24
Finished Aug 25 07:00:04 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863954884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2863954884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_smoke.4184898067
Short name T90
Test name
Test status
Simulation time 1636460048 ps
CPU time 11.29 seconds
Started Aug 25 06:58:18 AM UTC 24
Finished Aug 25 06:58:30 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184898067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4184898067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_stress_all.2860409123
Short name T453
Test name
Test status
Simulation time 17915253869 ps
CPU time 1529.26 seconds
Started Aug 25 06:58:44 AM UTC 24
Finished Aug 25 07:24:35 AM UTC 24
Peak memory 721152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860409123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2860409123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.434382894
Short name T48
Test name
Test status
Simulation time 15049716539 ps
CPU time 137.4 seconds
Started Aug 25 06:58:43 AM UTC 24
Finished Aug 25 07:01:03 AM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434382894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.434382894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_alert_test.2703978158
Short name T201
Test name
Test status
Simulation time 14676661 ps
CPU time 0.92 seconds
Started Aug 25 06:59:13 AM UTC 24
Finished Aug 25 06:59:15 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703978158 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2703978158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.2923925050
Short name T219
Test name
Test status
Simulation time 836902415 ps
CPU time 68 seconds
Started Aug 25 06:59:09 AM UTC 24
Finished Aug 25 07:00:19 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923925050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2923925050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.3212257623
Short name T166
Test name
Test status
Simulation time 4388001955 ps
CPU time 79.72 seconds
Started Aug 25 06:59:09 AM UTC 24
Finished Aug 25 07:00:31 AM UTC 24
Peak memory 215948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212257623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3212257623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.319968204
Short name T260
Test name
Test status
Simulation time 3964321293 ps
CPU time 263.85 seconds
Started Aug 25 06:59:09 AM UTC 24
Finished Aug 25 07:03:37 AM UTC 24
Peak memory 449004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319968204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.319968204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_error.2203782457
Short name T200
Test name
Test status
Simulation time 64791698 ps
CPU time 1.7 seconds
Started Aug 25 06:59:09 AM UTC 24
Finished Aug 25 06:59:12 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203782457 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2203782457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_long_msg.674765900
Short name T202
Test name
Test status
Simulation time 408742675 ps
CPU time 14.49 seconds
Started Aug 25 06:59:09 AM UTC 24
Finished Aug 25 06:59:25 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674765900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.674765900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_smoke.2291805175
Short name T196
Test name
Test status
Simulation time 187045065 ps
CPU time 4.31 seconds
Started Aug 25 06:59:00 AM UTC 24
Finished Aug 25 06:59:05 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291805175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2291805175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_stress_all.396779638
Short name T354
Test name
Test status
Simulation time 89932318352 ps
CPU time 907.84 seconds
Started Aug 25 06:59:13 AM UTC 24
Finished Aug 25 07:14:33 AM UTC 24
Peak memory 223588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396779638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.396779638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.463863961
Short name T129
Test name
Test status
Simulation time 6056453351 ps
CPU time 169.08 seconds
Started Aug 25 06:59:11 AM UTC 24
Finished Aug 25 07:02:04 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463863961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.463863961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_alert_test.4011166350
Short name T210
Test name
Test status
Simulation time 12528864 ps
CPU time 0.87 seconds
Started Aug 25 06:59:42 AM UTC 24
Finished Aug 25 06:59:44 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011166350 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4011166350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.2376077296
Short name T34
Test name
Test status
Simulation time 1287146764 ps
CPU time 94.45 seconds
Started Aug 25 06:59:19 AM UTC 24
Finished Aug 25 07:00:56 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376077296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2376077296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.1338163370
Short name T226
Test name
Test status
Simulation time 3792656541 ps
CPU time 72.95 seconds
Started Aug 25 06:59:30 AM UTC 24
Finished Aug 25 07:00:45 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338163370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1338163370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.1684115122
Short name T401
Test name
Test status
Simulation time 4553635258 ps
CPU time 1227.93 seconds
Started Aug 25 06:59:25 AM UTC 24
Finished Aug 25 07:20:09 AM UTC 24
Peak memory 712988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684115122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1684115122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_error.521182806
Short name T220
Test name
Test status
Simulation time 19457750621 ps
CPU time 49.79 seconds
Started Aug 25 06:59:30 AM UTC 24
Finished Aug 25 07:00:22 AM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521182806 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.521182806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_long_msg.196099904
Short name T224
Test name
Test status
Simulation time 4536901652 ps
CPU time 82.3 seconds
Started Aug 25 06:59:16 AM UTC 24
Finished Aug 25 07:00:40 AM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196099904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.196099904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_smoke.2480354670
Short name T204
Test name
Test status
Simulation time 2741796713 ps
CPU time 12.24 seconds
Started Aug 25 06:59:15 AM UTC 24
Finished Aug 25 06:59:29 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480354670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2480354670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_stress_all.2108188826
Short name T78
Test name
Test status
Simulation time 98694507460 ps
CPU time 2188.74 seconds
Started Aug 25 06:59:38 AM UTC 24
Finished Aug 25 07:36:35 AM UTC 24
Peak memory 741608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108188826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2108188826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.2214323074
Short name T50
Test name
Test status
Simulation time 5508403406 ps
CPU time 95.25 seconds
Started Aug 25 06:59:30 AM UTC 24
Finished Aug 25 07:01:08 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214323074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2214323074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_alert_test.275506519
Short name T215
Test name
Test status
Simulation time 43381455 ps
CPU time 0.87 seconds
Started Aug 25 07:00:09 AM UTC 24
Finished Aug 25 07:00:11 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275506519 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.275506519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.2134434056
Short name T227
Test name
Test status
Simulation time 3242254460 ps
CPU time 64.19 seconds
Started Aug 25 06:59:42 AM UTC 24
Finished Aug 25 07:00:49 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134434056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2134434056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.3722706481
Short name T165
Test name
Test status
Simulation time 159655697 ps
CPU time 10.89 seconds
Started Aug 25 06:59:49 AM UTC 24
Finished Aug 25 07:00:01 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722706481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3722706481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2905914488
Short name T369
Test name
Test status
Simulation time 9451777891 ps
CPU time 986.7 seconds
Started Aug 25 06:59:45 AM UTC 24
Finished Aug 25 07:16:25 AM UTC 24
Peak memory 733412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905914488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2905914488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_error.2789992667
Short name T259
Test name
Test status
Simulation time 6636265487 ps
CPU time 214.8 seconds
Started Aug 25 06:59:56 AM UTC 24
Finished Aug 25 07:03:34 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789992667 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2789992667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_long_msg.822153704
Short name T211
Test name
Test status
Simulation time 103914965 ps
CPU time 4.11 seconds
Started Aug 25 06:59:42 AM UTC 24
Finished Aug 25 06:59:48 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822153704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.822153704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_smoke.4143143498
Short name T213
Test name
Test status
Simulation time 1796254621 ps
CPU time 18.33 seconds
Started Aug 25 06:59:42 AM UTC 24
Finished Aug 25 07:00:02 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143143498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4143143498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_stress_all.2068869907
Short name T458
Test name
Test status
Simulation time 79878567036 ps
CPU time 1467.03 seconds
Started Aug 25 07:00:09 AM UTC 24
Finished Aug 25 07:24:56 AM UTC 24
Peak memory 717156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068869907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2068869907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.3995477092
Short name T52
Test name
Test status
Simulation time 11119979133 ps
CPU time 73.43 seconds
Started Aug 25 07:00:02 AM UTC 24
Finished Aug 25 07:01:23 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995477092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3995477092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_alert_test.2338790550
Short name T223
Test name
Test status
Simulation time 57506907 ps
CPU time 0.89 seconds
Started Aug 25 07:00:32 AM UTC 24
Finished Aug 25 07:00:34 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338790550 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2338790550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.3705075602
Short name T236
Test name
Test status
Simulation time 5375202039 ps
CPU time 95.28 seconds
Started Aug 25 07:00:15 AM UTC 24
Finished Aug 25 07:01:52 AM UTC 24
Peak memory 207368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705075602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3705075602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.681699120
Short name T225
Test name
Test status
Simulation time 1092934003 ps
CPU time 21.34 seconds
Started Aug 25 07:00:21 AM UTC 24
Finished Aug 25 07:00:44 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681699120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.681699120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.1141607411
Short name T484
Test name
Test status
Simulation time 27637047682 ps
CPU time 1705.3 seconds
Started Aug 25 07:00:16 AM UTC 24
Finished Aug 25 07:29:03 AM UTC 24
Peak memory 754064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141607411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1141607411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_error.1549247041
Short name T231
Test name
Test status
Simulation time 2834017680 ps
CPU time 68.89 seconds
Started Aug 25 07:00:23 AM UTC 24
Finished Aug 25 07:01:34 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549247041 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1549247041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_long_msg.85243937
Short name T233
Test name
Test status
Simulation time 4525329250 ps
CPU time 80.43 seconds
Started Aug 25 07:00:14 AM UTC 24
Finished Aug 25 07:01:37 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85243937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.85243937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_smoke.577046148
Short name T221
Test name
Test status
Simulation time 2164080728 ps
CPU time 10.11 seconds
Started Aug 25 07:00:14 AM UTC 24
Finished Aug 25 07:00:26 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577046148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.577046148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2155340703
Short name T405
Test name
Test status
Simulation time 14036471368 ps
CPU time 1182.37 seconds
Started Aug 25 07:00:29 AM UTC 24
Finished Aug 25 07:20:27 AM UTC 24
Peak memory 635136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155340703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2155340703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.3897818327
Short name T130
Test name
Test status
Simulation time 5168168014 ps
CPU time 129.16 seconds
Started Aug 25 07:00:27 AM UTC 24
Finished Aug 25 07:02:39 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897818327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3897818327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_alert_test.2712029015
Short name T49
Test name
Test status
Simulation time 14296619 ps
CPU time 0.96 seconds
Started Aug 25 07:01:05 AM UTC 24
Finished Aug 25 07:01:07 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712029015 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2712029015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.712557831
Short name T46
Test name
Test status
Simulation time 146941732 ps
CPU time 11.53 seconds
Started Aug 25 07:00:45 AM UTC 24
Finished Aug 25 07:00:57 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712557831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.712557831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.2921667091
Short name T237
Test name
Test status
Simulation time 4266742548 ps
CPU time 62.06 seconds
Started Aug 25 07:00:50 AM UTC 24
Finished Aug 25 07:01:54 AM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921667091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2921667091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.2629687893
Short name T492
Test name
Test status
Simulation time 26328861100 ps
CPU time 1900.99 seconds
Started Aug 25 07:00:47 AM UTC 24
Finished Aug 25 07:32:52 AM UTC 24
Peak memory 760304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629687893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2629687893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_error.796820279
Short name T245
Test name
Test status
Simulation time 8438363319 ps
CPU time 105.99 seconds
Started Aug 25 07:00:55 AM UTC 24
Finished Aug 25 07:02:44 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796820279 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.796820279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_long_msg.2899483586
Short name T229
Test name
Test status
Simulation time 2994830501 ps
CPU time 46.24 seconds
Started Aug 25 07:00:42 AM UTC 24
Finished Aug 25 07:01:29 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899483586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2899483586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_smoke.1971210537
Short name T228
Test name
Test status
Simulation time 559205500 ps
CPU time 18.31 seconds
Started Aug 25 07:00:35 AM UTC 24
Finished Aug 25 07:00:55 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971210537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1971210537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_stress_all.1051567498
Short name T529
Test name
Test status
Simulation time 134234864570 ps
CPU time 4435.8 seconds
Started Aug 25 07:00:59 AM UTC 24
Finished Aug 25 08:15:48 AM UTC 24
Peak memory 813432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051567498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1051567498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.1641249076
Short name T241
Test name
Test status
Simulation time 3572479767 ps
CPU time 72.35 seconds
Started Aug 25 07:00:58 AM UTC 24
Finished Aug 25 07:02:14 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641249076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1641249076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_alert_test.3847719137
Short name T232
Test name
Test status
Simulation time 15408382 ps
CPU time 0.9 seconds
Started Aug 25 07:01:32 AM UTC 24
Finished Aug 25 07:01:34 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847719137 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3847719137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.407977850
Short name T247
Test name
Test status
Simulation time 6998983886 ps
CPU time 93.52 seconds
Started Aug 25 07:01:09 AM UTC 24
Finished Aug 25 07:02:46 AM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407977850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.407977850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.3077899763
Short name T53
Test name
Test status
Simulation time 134445612 ps
CPU time 1.28 seconds
Started Aug 25 07:01:24 AM UTC 24
Finished Aug 25 07:01:26 AM UTC 24
Peak memory 206696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077899763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3077899763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.599816057
Short name T289
Test name
Test status
Simulation time 5241266804 ps
CPU time 330.16 seconds
Started Aug 25 07:01:11 AM UTC 24
Finished Aug 25 07:06:47 AM UTC 24
Peak memory 639204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599816057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.599816057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_error.1947051583
Short name T279
Test name
Test status
Simulation time 3821123280 ps
CPU time 261.64 seconds
Started Aug 25 07:01:27 AM UTC 24
Finished Aug 25 07:05:53 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947051583 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1947051583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_long_msg.1225382905
Short name T242
Test name
Test status
Simulation time 2964160349 ps
CPU time 73.99 seconds
Started Aug 25 07:01:08 AM UTC 24
Finished Aug 25 07:02:24 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225382905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1225382905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_smoke.3045344871
Short name T51
Test name
Test status
Simulation time 263227751 ps
CPU time 4.23 seconds
Started Aug 25 07:01:05 AM UTC 24
Finished Aug 25 07:01:10 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045344871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3045344871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2552747930
Short name T500
Test name
Test status
Simulation time 57825642857 ps
CPU time 2211.47 seconds
Started Aug 25 07:01:32 AM UTC 24
Finished Aug 25 07:38:52 AM UTC 24
Peak memory 776420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552747930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2552747930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.3629313730
Short name T235
Test name
Test status
Simulation time 2766486400 ps
CPU time 14.7 seconds
Started Aug 25 07:01:30 AM UTC 24
Finished Aug 25 07:01:46 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629313730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3629313730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_alert_test.800476974
Short name T239
Test name
Test status
Simulation time 14889906 ps
CPU time 0.92 seconds
Started Aug 25 07:02:06 AM UTC 24
Finished Aug 25 07:02:08 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800476974 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.800476974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.3756598337
Short name T240
Test name
Test status
Simulation time 2236113029 ps
CPU time 31.37 seconds
Started Aug 25 07:01:38 AM UTC 24
Finished Aug 25 07:02:11 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756598337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3756598337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.586120764
Short name T254
Test name
Test status
Simulation time 3026704426 ps
CPU time 82.65 seconds
Started Aug 25 07:01:47 AM UTC 24
Finished Aug 25 07:03:12 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586120764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.586120764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.320116452
Short name T494
Test name
Test status
Simulation time 13437010631 ps
CPU time 1921.13 seconds
Started Aug 25 07:01:40 AM UTC 24
Finished Aug 25 07:34:06 AM UTC 24
Peak memory 786800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320116452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.320116452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_error.1489540723
Short name T246
Test name
Test status
Simulation time 1777956739 ps
CPU time 49.63 seconds
Started Aug 25 07:01:53 AM UTC 24
Finished Aug 25 07:02:45 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489540723 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1489540723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_long_msg.930416465
Short name T257
Test name
Test status
Simulation time 18212751683 ps
CPU time 106.01 seconds
Started Aug 25 07:01:36 AM UTC 24
Finished Aug 25 07:03:25 AM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930416465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.930416465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_smoke.1683097536
Short name T234
Test name
Test status
Simulation time 264307671 ps
CPU time 3.25 seconds
Started Aug 25 07:01:35 AM UTC 24
Finished Aug 25 07:01:40 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683097536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1683097536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_stress_all.2177774614
Short name T530
Test name
Test status
Simulation time 234401835196 ps
CPU time 4497.08 seconds
Started Aug 25 07:02:06 AM UTC 24
Finished Aug 25 08:17:57 AM UTC 24
Peak memory 860292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177774614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2177774614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.3294990059
Short name T93
Test name
Test status
Simulation time 1147387174 ps
CPU time 57.08 seconds
Started Aug 25 07:01:55 AM UTC 24
Finished Aug 25 07:02:54 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294990059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3294990059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2677346201
Short name T21
Test name
Test status
Simulation time 40606268 ps
CPU time 0.82 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 202820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677346201 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2677346201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.4244421647
Short name T9
Test name
Test status
Simulation time 378996649 ps
CPU time 28.35 seconds
Started Aug 25 06:54:19 AM UTC 24
Finished Aug 25 06:54:59 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244421647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4244421647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.2971078035
Short name T27
Test name
Test status
Simulation time 1628086824 ps
CPU time 60.84 seconds
Started Aug 25 06:54:26 AM UTC 24
Finished Aug 25 06:55:32 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971078035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2971078035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.1009362439
Short name T284
Test name
Test status
Simulation time 2917723036 ps
CPU time 705.05 seconds
Started Aug 25 06:54:26 AM UTC 24
Finished Aug 25 07:06:24 AM UTC 24
Peak memory 537072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009362439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1009362439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_error.2266306730
Short name T60
Test name
Test status
Simulation time 1350954929 ps
CPU time 32.76 seconds
Started Aug 25 06:54:26 AM UTC 24
Finished Aug 25 06:55:04 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266306730 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2266306730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_long_msg.1762637894
Short name T76
Test name
Test status
Simulation time 3437976512 ps
CPU time 68.35 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:55:38 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762637894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1762637894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_smoke.621155331
Short name T6
Test name
Test status
Simulation time 542137256 ps
CPU time 9.89 seconds
Started Aug 25 06:54:18 AM UTC 24
Finished Aug 25 06:54:39 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621155331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.621155331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_stress_all.2498072924
Short name T528
Test name
Test status
Simulation time 72295444994 ps
CPU time 4707.04 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 08:13:53 AM UTC 24
Peak memory 788596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498072924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2498072924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.593561167
Short name T13
Test name
Test status
Simulation time 19832999183 ps
CPU time 119.06 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 06:56:31 AM UTC 24
Peak memory 223248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59356116
7 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.593561167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.3705469065
Short name T57
Test name
Test status
Simulation time 9028910387 ps
CPU time 86.03 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 06:55:57 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705469065 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3705469065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.2570235466
Short name T181
Test name
Test status
Simulation time 24287353280 ps
CPU time 107.38 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 06:56:19 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570235466 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2570235466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.2441805590
Short name T178
Test name
Test status
Simulation time 6939531089 ps
CPU time 98.64 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 06:56:10 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441805590 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2441805590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.878127190
Short name T300
Test name
Test status
Simulation time 45931199809 ps
CPU time 839.22 seconds
Started Aug 25 06:54:28 AM UTC 24
Finished Aug 25 07:08:40 AM UTC 24
Peak memory 206996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878127190 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.878127190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1194231588
Short name T515
Test name
Test status
Simulation time 516749149346 ps
CPU time 3197.74 seconds
Started Aug 25 06:54:28 AM UTC 24
Finished Aug 25 07:48:32 AM UTC 24
Peak memory 227380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194231588 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1194231588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1096326760
Short name T514
Test name
Test status
Simulation time 161357901652 ps
CPU time 3185.85 seconds
Started Aug 25 06:54:29 AM UTC 24
Finished Aug 25 07:48:17 AM UTC 24
Peak memory 225368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096326760 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1096326760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.3429654191
Short name T24
Test name
Test status
Simulation time 461315364 ps
CPU time 25.56 seconds
Started Aug 25 06:54:28 AM UTC 24
Finished Aug 25 06:54:56 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429654191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3429654191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_alert_test.832025819
Short name T249
Test name
Test status
Simulation time 37015319 ps
CPU time 0.89 seconds
Started Aug 25 07:02:46 AM UTC 24
Finished Aug 25 07:02:47 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832025819 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.832025819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.3452083211
Short name T263
Test name
Test status
Simulation time 1238640880 ps
CPU time 94.1 seconds
Started Aug 25 07:02:15 AM UTC 24
Finished Aug 25 07:03:52 AM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452083211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3452083211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.2508787532
Short name T248
Test name
Test status
Simulation time 5730562255 ps
CPU time 15.07 seconds
Started Aug 25 07:02:30 AM UTC 24
Finished Aug 25 07:02:46 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508787532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2508787532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.960849869
Short name T485
Test name
Test status
Simulation time 24108867541 ps
CPU time 1579.21 seconds
Started Aug 25 07:02:26 AM UTC 24
Finished Aug 25 07:29:04 AM UTC 24
Peak memory 796960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960849869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.960849869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_error.2218568313
Short name T256
Test name
Test status
Simulation time 5357374321 ps
CPU time 51.31 seconds
Started Aug 25 07:02:31 AM UTC 24
Finished Aug 25 07:03:24 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218568313 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2218568313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_long_msg.1323113476
Short name T243
Test name
Test status
Simulation time 190616036 ps
CPU time 15.79 seconds
Started Aug 25 07:02:12 AM UTC 24
Finished Aug 25 07:02:29 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323113476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1323113476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_smoke.66450637
Short name T244
Test name
Test status
Simulation time 4494021736 ps
CPU time 18.95 seconds
Started Aug 25 07:02:10 AM UTC 24
Finished Aug 25 07:02:30 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66450637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 20.hmac_smoke.66450637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_stress_all.3440784829
Short name T77
Test name
Test status
Simulation time 53949405850 ps
CPU time 417.57 seconds
Started Aug 25 07:02:45 AM UTC 24
Finished Aug 25 07:09:50 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440784829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3440784829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.773158478
Short name T253
Test name
Test status
Simulation time 2893110870 ps
CPU time 29.02 seconds
Started Aug 25 07:02:41 AM UTC 24
Finished Aug 25 07:03:11 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773158478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.773158478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_alert_test.1930256222
Short name T255
Test name
Test status
Simulation time 24133927 ps
CPU time 0.83 seconds
Started Aug 25 07:03:13 AM UTC 24
Finished Aug 25 07:03:15 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930256222 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1930256222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.1632791439
Short name T252
Test name
Test status
Simulation time 141889006 ps
CPU time 9.89 seconds
Started Aug 25 07:02:49 AM UTC 24
Finished Aug 25 07:03:00 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632791439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1632791439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.3957488375
Short name T266
Test name
Test status
Simulation time 4787804359 ps
CPU time 60.95 seconds
Started Aug 25 07:02:55 AM UTC 24
Finished Aug 25 07:03:58 AM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957488375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3957488375
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3061301124
Short name T489
Test name
Test status
Simulation time 5989956566 ps
CPU time 1726.02 seconds
Started Aug 25 07:02:53 AM UTC 24
Finished Aug 25 07:32:02 AM UTC 24
Peak memory 770332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061301124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3061301124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_error.2223664916
Short name T280
Test name
Test status
Simulation time 2446456497 ps
CPU time 172.23 seconds
Started Aug 25 07:02:58 AM UTC 24
Finished Aug 25 07:05:54 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223664916 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2223664916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_long_msg.3093555018
Short name T269
Test name
Test status
Simulation time 6985744917 ps
CPU time 119.19 seconds
Started Aug 25 07:02:48 AM UTC 24
Finished Aug 25 07:04:49 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093555018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3093555018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_smoke.44211271
Short name T250
Test name
Test status
Simulation time 112148466 ps
CPU time 3.18 seconds
Started Aug 25 07:02:47 AM UTC 24
Finished Aug 25 07:02:52 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44211271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.hmac_smoke.44211271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_stress_all.2501796971
Short name T524
Test name
Test status
Simulation time 22632259724 ps
CPU time 3574.72 seconds
Started Aug 25 07:03:12 AM UTC 24
Finished Aug 25 08:03:32 AM UTC 24
Peak memory 831772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501796971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2501796971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.301898534
Short name T94
Test name
Test status
Simulation time 2180852716 ps
CPU time 135.41 seconds
Started Aug 25 07:03:00 AM UTC 24
Finished Aug 25 07:05:19 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301898534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.301898534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_alert_test.396972343
Short name T264
Test name
Test status
Simulation time 17066932 ps
CPU time 0.84 seconds
Started Aug 25 07:03:51 AM UTC 24
Finished Aug 25 07:03:53 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396972343 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.396972343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.2591521249
Short name T262
Test name
Test status
Simulation time 280384627 ps
CPU time 22.45 seconds
Started Aug 25 07:03:26 AM UTC 24
Finished Aug 25 07:03:50 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591521249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2591521249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.3468967190
Short name T267
Test name
Test status
Simulation time 10812628667 ps
CPU time 55.76 seconds
Started Aug 25 07:03:31 AM UTC 24
Finished Aug 25 07:04:29 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468967190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3468967190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.1295075733
Short name T373
Test name
Test status
Simulation time 6769889956 ps
CPU time 787.4 seconds
Started Aug 25 07:03:31 AM UTC 24
Finished Aug 25 07:16:50 AM UTC 24
Peak memory 471516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295075733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1295075733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_error.2066436779
Short name T261
Test name
Test status
Simulation time 29535756 ps
CPU time 1.48 seconds
Started Aug 25 07:03:36 AM UTC 24
Finished Aug 25 07:03:39 AM UTC 24
Peak memory 206280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066436779 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2066436779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_long_msg.3677795527
Short name T271
Test name
Test status
Simulation time 6273402667 ps
CPU time 88.36 seconds
Started Aug 25 07:03:26 AM UTC 24
Finished Aug 25 07:04:57 AM UTC 24
Peak memory 207116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677795527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3677795527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_smoke.3365993523
Short name T258
Test name
Test status
Simulation time 539146303 ps
CPU time 12.26 seconds
Started Aug 25 07:03:16 AM UTC 24
Finished Aug 25 07:03:29 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365993523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3365993523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_stress_all.2973540547
Short name T521
Test name
Test status
Simulation time 67166598895 ps
CPU time 2850.51 seconds
Started Aug 25 07:03:39 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 778792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973540547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2973540547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.1024315539
Short name T276
Test name
Test status
Simulation time 50275305632 ps
CPU time 101.21 seconds
Started Aug 25 07:03:38 AM UTC 24
Finished Aug 25 07:05:22 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024315539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1024315539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_alert_test.3846293193
Short name T272
Test name
Test status
Simulation time 16671333 ps
CPU time 0.91 seconds
Started Aug 25 07:04:58 AM UTC 24
Finished Aug 25 07:05:00 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846293193 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3846293193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.126113472
Short name T273
Test name
Test status
Simulation time 1265598269 ps
CPU time 63.31 seconds
Started Aug 25 07:03:57 AM UTC 24
Finished Aug 25 07:05:02 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126113472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.126113472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.3480836671
Short name T268
Test name
Test status
Simulation time 1439187190 ps
CPU time 7.89 seconds
Started Aug 25 07:04:30 AM UTC 24
Finished Aug 25 07:04:39 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480836671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3480836671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.3381635551
Short name T37
Test name
Test status
Simulation time 957633103 ps
CPU time 197.77 seconds
Started Aug 25 07:03:59 AM UTC 24
Finished Aug 25 07:07:20 AM UTC 24
Peak memory 700492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381635551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3381635551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_error.976001210
Short name T274
Test name
Test status
Simulation time 690416441 ps
CPU time 25.97 seconds
Started Aug 25 07:04:40 AM UTC 24
Finished Aug 25 07:05:07 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976001210 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.976001210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_long_msg.2543552290
Short name T270
Test name
Test status
Simulation time 3158844378 ps
CPU time 59.74 seconds
Started Aug 25 07:03:54 AM UTC 24
Finished Aug 25 07:04:55 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543552290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2543552290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_smoke.1826973121
Short name T265
Test name
Test status
Simulation time 37420485 ps
CPU time 1.47 seconds
Started Aug 25 07:03:53 AM UTC 24
Finished Aug 25 07:03:56 AM UTC 24
Peak memory 206516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826973121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1826973121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_stress_all.3256824556
Short name T516
Test name
Test status
Simulation time 25480707563 ps
CPU time 2596.59 seconds
Started Aug 25 07:04:56 AM UTC 24
Finished Aug 25 07:48:47 AM UTC 24
Peak memory 803044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256824556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3256824556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.2431318103
Short name T131
Test name
Test status
Simulation time 1987818865 ps
CPU time 138.13 seconds
Started Aug 25 07:04:51 AM UTC 24
Finished Aug 25 07:07:12 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431318103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2431318103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_alert_test.1032440631
Short name T281
Test name
Test status
Simulation time 29115425 ps
CPU time 0.93 seconds
Started Aug 25 07:05:56 AM UTC 24
Finished Aug 25 07:05:58 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032440631 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1032440631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.545512312
Short name T286
Test name
Test status
Simulation time 6245619492 ps
CPU time 86.21 seconds
Started Aug 25 07:05:09 AM UTC 24
Finished Aug 25 07:06:37 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545512312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.545512312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2836992370
Short name T283
Test name
Test status
Simulation time 1945521157 ps
CPU time 54.37 seconds
Started Aug 25 07:05:21 AM UTC 24
Finished Aug 25 07:06:17 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836992370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2836992370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.2039733220
Short name T340
Test name
Test status
Simulation time 1817992881 ps
CPU time 434.79 seconds
Started Aug 25 07:05:18 AM UTC 24
Finished Aug 25 07:12:39 AM UTC 24
Peak memory 665808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039733220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2039733220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_error.2659280034
Short name T277
Test name
Test status
Simulation time 786103215 ps
CPU time 15.32 seconds
Started Aug 25 07:05:23 AM UTC 24
Finished Aug 25 07:05:40 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659280034 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2659280034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_long_msg.1545265907
Short name T285
Test name
Test status
Simulation time 3102945375 ps
CPU time 80 seconds
Started Aug 25 07:05:03 AM UTC 24
Finished Aug 25 07:06:26 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545265907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1545265907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_smoke.3287581427
Short name T275
Test name
Test status
Simulation time 3134839023 ps
CPU time 14.93 seconds
Started Aug 25 07:05:01 AM UTC 24
Finished Aug 25 07:05:17 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287581427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3287581427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_stress_all.3061829199
Short name T133
Test name
Test status
Simulation time 3457378439 ps
CPU time 254.25 seconds
Started Aug 25 07:05:50 AM UTC 24
Finished Aug 25 07:10:09 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061829199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3061829199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.3780150685
Short name T43
Test name
Test status
Simulation time 24029238182 ps
CPU time 132.19 seconds
Started Aug 25 07:05:40 AM UTC 24
Finished Aug 25 07:07:55 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780150685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3780150685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_alert_test.1333151020
Short name T287
Test name
Test status
Simulation time 25965312 ps
CPU time 0.92 seconds
Started Aug 25 07:06:44 AM UTC 24
Finished Aug 25 07:06:46 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333151020 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1333151020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.3292582496
Short name T44
Test name
Test status
Simulation time 3661466215 ps
CPU time 108.25 seconds
Started Aug 25 07:06:12 AM UTC 24
Finished Aug 25 07:08:02 AM UTC 24
Peak memory 223648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292582496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3292582496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.4180600857
Short name T288
Test name
Test status
Simulation time 2001688698 ps
CPU time 26.83 seconds
Started Aug 25 07:06:18 AM UTC 24
Finished Aug 25 07:06:46 AM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180600857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4180600857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2817209701
Short name T408
Test name
Test status
Simulation time 6797235397 ps
CPU time 861.3 seconds
Started Aug 25 07:06:16 AM UTC 24
Finished Aug 25 07:20:48 AM UTC 24
Peak memory 682340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817209701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2817209701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_error.1539170066
Short name T323
Test name
Test status
Simulation time 3446662876 ps
CPU time 255.14 seconds
Started Aug 25 07:06:27 AM UTC 24
Finished Aug 25 07:10:47 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539170066 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1539170066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3655218500
Short name T316
Test name
Test status
Simulation time 33099140531 ps
CPU time 208.32 seconds
Started Aug 25 07:05:59 AM UTC 24
Finished Aug 25 07:09:31 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655218500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3655218500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_smoke.919589572
Short name T155
Test name
Test status
Simulation time 5346306858 ps
CPU time 16.9 seconds
Started Aug 25 07:05:56 AM UTC 24
Finished Aug 25 07:06:14 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919589572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.919589572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_stress_all.4117383286
Short name T80
Test name
Test status
Simulation time 202240028779 ps
CPU time 2260.11 seconds
Started Aug 25 07:06:38 AM UTC 24
Finished Aug 25 07:44:49 AM UTC 24
Peak memory 725216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117383286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4117383286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.1401133538
Short name T293
Test name
Test status
Simulation time 1653316646 ps
CPU time 46.5 seconds
Started Aug 25 07:06:27 AM UTC 24
Finished Aug 25 07:07:15 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401133538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1401133538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_alert_test.1916379173
Short name T39
Test name
Test status
Simulation time 16123533 ps
CPU time 0.86 seconds
Started Aug 25 07:07:23 AM UTC 24
Finished Aug 25 07:07:25 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916379173 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1916379173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.1233246060
Short name T291
Test name
Test status
Simulation time 380654264 ps
CPU time 7.88 seconds
Started Aug 25 07:06:49 AM UTC 24
Finished Aug 25 07:06:58 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233246060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1233246060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.713155891
Short name T42
Test name
Test status
Simulation time 1870885486 ps
CPU time 39.72 seconds
Started Aug 25 07:06:59 AM UTC 24
Finished Aug 25 07:07:40 AM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713155891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.713155891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.3654748490
Short name T370
Test name
Test status
Simulation time 2244046641 ps
CPU time 572.48 seconds
Started Aug 25 07:06:59 AM UTC 24
Finished Aug 25 07:16:39 AM UTC 24
Peak memory 711148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654748490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3654748490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_error.3933067623
Short name T41
Test name
Test status
Simulation time 676566375 ps
CPU time 26.63 seconds
Started Aug 25 07:07:07 AM UTC 24
Finished Aug 25 07:07:36 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933067623 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3933067623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_long_msg.471864913
Short name T45
Test name
Test status
Simulation time 907327906 ps
CPU time 77.7 seconds
Started Aug 25 07:06:47 AM UTC 24
Finished Aug 25 07:08:07 AM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471864913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.471864913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_smoke.3454867098
Short name T290
Test name
Test status
Simulation time 138520908 ps
CPU time 8.9 seconds
Started Aug 25 07:06:47 AM UTC 24
Finished Aug 25 07:06:57 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454867098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3454867098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_stress_all.3561955352
Short name T297
Test name
Test status
Simulation time 2471065425 ps
CPU time 60.19 seconds
Started Aug 25 07:07:17 AM UTC 24
Finished Aug 25 07:08:19 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561955352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3561955352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.3212934982
Short name T306
Test name
Test status
Simulation time 5173772563 ps
CPU time 107.36 seconds
Started Aug 25 07:07:13 AM UTC 24
Finished Aug 25 07:09:03 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212934982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3212934982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_alert_test.1479200676
Short name T294
Test name
Test status
Simulation time 13259945 ps
CPU time 0.85 seconds
Started Aug 25 07:08:08 AM UTC 24
Finished Aug 25 07:08:10 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479200676 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1479200676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3143191639
Short name T296
Test name
Test status
Simulation time 2357277036 ps
CPU time 45.97 seconds
Started Aug 25 07:07:28 AM UTC 24
Finished Aug 25 07:08:16 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143191639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3143191639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.2755284218
Short name T299
Test name
Test status
Simulation time 6638339969 ps
CPU time 60.76 seconds
Started Aug 25 07:07:37 AM UTC 24
Finished Aug 25 07:08:39 AM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755284218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2755284218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.3074436135
Short name T355
Test name
Test status
Simulation time 10912640209 ps
CPU time 418.8 seconds
Started Aug 25 07:07:34 AM UTC 24
Finished Aug 25 07:14:39 AM UTC 24
Peak memory 637412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074436135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3074436135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_error.2183004170
Short name T295
Test name
Test status
Simulation time 1669478202 ps
CPU time 28.97 seconds
Started Aug 25 07:07:41 AM UTC 24
Finished Aug 25 07:08:11 AM UTC 24
Peak memory 207112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183004170 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2183004170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_long_msg.704885394
Short name T313
Test name
Test status
Simulation time 30316289397 ps
CPU time 105.57 seconds
Started Aug 25 07:07:28 AM UTC 24
Finished Aug 25 07:09:16 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704885394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.704885394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_smoke.3892569287
Short name T40
Test name
Test status
Simulation time 165266484 ps
CPU time 9.89 seconds
Started Aug 25 07:07:23 AM UTC 24
Finished Aug 25 07:07:34 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892569287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3892569287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_stress_all.3356443371
Short name T478
Test name
Test status
Simulation time 159163538526 ps
CPU time 1141.23 seconds
Started Aug 25 07:08:05 AM UTC 24
Finished Aug 25 07:27:20 AM UTC 24
Peak memory 682320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356443371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3356443371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.2671937413
Short name T327
Test name
Test status
Simulation time 44080692457 ps
CPU time 184.6 seconds
Started Aug 25 07:07:56 AM UTC 24
Finished Aug 25 07:11:05 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671937413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2671937413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_alert_test.4209907179
Short name T303
Test name
Test status
Simulation time 14110409 ps
CPU time 0.84 seconds
Started Aug 25 07:08:50 AM UTC 24
Finished Aug 25 07:08:52 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209907179 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4209907179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.3329279316
Short name T301
Test name
Test status
Simulation time 331236829 ps
CPU time 28.13 seconds
Started Aug 25 07:08:18 AM UTC 24
Finished Aug 25 07:08:47 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329279316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3329279316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.2705697052
Short name T307
Test name
Test status
Simulation time 2360783051 ps
CPU time 39.74 seconds
Started Aug 25 07:08:23 AM UTC 24
Finished Aug 25 07:09:04 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705697052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2705697052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.2329627536
Short name T439
Test name
Test status
Simulation time 6025679356 ps
CPU time 872.64 seconds
Started Aug 25 07:08:20 AM UTC 24
Finished Aug 25 07:23:04 AM UTC 24
Peak memory 657632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329627536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2329627536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_error.913091392
Short name T302
Test name
Test status
Simulation time 405447431 ps
CPU time 8.19 seconds
Started Aug 25 07:08:40 AM UTC 24
Finished Aug 25 07:08:50 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913091392 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.913091392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_long_msg.3293770745
Short name T305
Test name
Test status
Simulation time 7234295247 ps
CPU time 46.18 seconds
Started Aug 25 07:08:12 AM UTC 24
Finished Aug 25 07:09:00 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293770745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3293770745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_smoke.3836140197
Short name T298
Test name
Test status
Simulation time 386654426 ps
CPU time 9.68 seconds
Started Aug 25 07:08:11 AM UTC 24
Finished Aug 25 07:08:22 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836140197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3836140197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_stress_all.3293034857
Short name T510
Test name
Test status
Simulation time 15349847853 ps
CPU time 2212.93 seconds
Started Aug 25 07:08:48 AM UTC 24
Finished Aug 25 07:46:10 AM UTC 24
Peak memory 764336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293034857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3293034857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.1768659436
Short name T308
Test name
Test status
Simulation time 5490258234 ps
CPU time 19.81 seconds
Started Aug 25 07:08:44 AM UTC 24
Finished Aug 25 07:09:05 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768659436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1768659436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_alert_test.1004690461
Short name T312
Test name
Test status
Simulation time 55688262 ps
CPU time 0.85 seconds
Started Aug 25 07:09:14 AM UTC 24
Finished Aug 25 07:09:16 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004690461 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1004690461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.3377681699
Short name T309
Test name
Test status
Simulation time 179667851 ps
CPU time 4.37 seconds
Started Aug 25 07:09:01 AM UTC 24
Finished Aug 25 07:09:06 AM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377681699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3377681699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.2701436163
Short name T168
Test name
Test status
Simulation time 2924842390 ps
CPU time 46.26 seconds
Started Aug 25 07:09:05 AM UTC 24
Finished Aug 25 07:09:53 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701436163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2701436163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.1511832972
Short name T419
Test name
Test status
Simulation time 3042323881 ps
CPU time 734.28 seconds
Started Aug 25 07:09:04 AM UTC 24
Finished Aug 25 07:21:29 AM UTC 24
Peak memory 754156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511832972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1511832972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_error.2825533212
Short name T346
Test name
Test status
Simulation time 53909191715 ps
CPU time 237.94 seconds
Started Aug 25 07:09:07 AM UTC 24
Finished Aug 25 07:13:09 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825533212 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2825533212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_long_msg.246048862
Short name T322
Test name
Test status
Simulation time 2586275479 ps
CPU time 102.05 seconds
Started Aug 25 07:08:58 AM UTC 24
Finished Aug 25 07:10:42 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246048862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.246048862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_smoke.592967748
Short name T311
Test name
Test status
Simulation time 769548861 ps
CPU time 17.97 seconds
Started Aug 25 07:08:54 AM UTC 24
Finished Aug 25 07:09:13 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592967748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.592967748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_stress_all.1066663717
Short name T532
Test name
Test status
Simulation time 198198203388 ps
CPU time 4475.61 seconds
Started Aug 25 07:09:13 AM UTC 24
Finished Aug 25 08:24:47 AM UTC 24
Peak memory 786552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066663717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1066663717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.2131088324
Short name T328
Test name
Test status
Simulation time 24270397768 ps
CPU time 119.33 seconds
Started Aug 25 07:09:07 AM UTC 24
Finished Aug 25 07:11:09 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131088324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2131088324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_alert_test.2644170564
Short name T23
Test name
Test status
Simulation time 37454514 ps
CPU time 0.86 seconds
Started Aug 25 06:54:36 AM UTC 24
Finished Aug 25 06:54:38 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644170564 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2644170564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.1301057983
Short name T56
Test name
Test status
Simulation time 2996271512 ps
CPU time 55.29 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 06:55:28 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301057983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1301057983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.1492235888
Short name T164
Test name
Test status
Simulation time 21945764299 ps
CPU time 102.26 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 06:56:16 AM UTC 24
Peak memory 207204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492235888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1492235888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.380058954
Short name T432
Test name
Test status
Simulation time 23891006814 ps
CPU time 1634.33 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 07:22:06 AM UTC 24
Peak memory 760108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380058954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.380058954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_error.997911524
Short name T61
Test name
Test status
Simulation time 5202408795 ps
CPU time 117.12 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 06:56:31 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997911524 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.997911524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_long_msg.95114896
Short name T8
Test name
Test status
Simulation time 1142885280 ps
CPU time 24.16 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 06:54:57 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95114896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.95114896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.3958378421
Short name T66
Test name
Test status
Simulation time 1089328217 ps
CPU time 1.6 seconds
Started Aug 25 06:54:36 AM UTC 24
Finished Aug 25 06:54:39 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958378421 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3958378421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_smoke.2468888780
Short name T7
Test name
Test status
Simulation time 5465968929 ps
CPU time 25.02 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 06:54:57 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468888780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2468888780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_stress_all.1984873217
Short name T38
Test name
Test status
Simulation time 31313933236 ps
CPU time 757.49 seconds
Started Aug 25 06:54:34 AM UTC 24
Finished Aug 25 07:07:22 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984873217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1984873217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.2689667701
Short name T19
Test name
Test status
Simulation time 29714611079 ps
CPU time 526.98 seconds
Started Aug 25 06:54:34 AM UTC 24
Finished Aug 25 07:03:29 AM UTC 24
Peak memory 502176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26896677
01 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2689667701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3660156751
Short name T59
Test name
Test status
Simulation time 25066159002 ps
CPU time 98.9 seconds
Started Aug 25 06:54:33 AM UTC 24
Finished Aug 25 06:56:15 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660156751 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3660156751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.3981002778
Short name T126
Test name
Test status
Simulation time 23706154306 ps
CPU time 119.11 seconds
Started Aug 25 06:54:34 AM UTC 24
Finished Aug 25 06:56:35 AM UTC 24
Peak memory 207532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981002778 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3981002778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.339719189
Short name T122
Test name
Test status
Simulation time 5065984032 ps
CPU time 111.03 seconds
Started Aug 25 06:54:34 AM UTC 24
Finished Aug 25 06:56:28 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339719189 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.339719189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.244565394
Short name T321
Test name
Test status
Simulation time 176277054796 ps
CPU time 942.81 seconds
Started Aug 25 06:54:33 AM UTC 24
Finished Aug 25 07:10:30 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244565394 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.244565394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.582965125
Short name T512
Test name
Test status
Simulation time 155364076243 ps
CPU time 3102.7 seconds
Started Aug 25 06:54:33 AM UTC 24
Finished Aug 25 07:46:59 AM UTC 24
Peak memory 215892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582965125 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.582965125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.3845232425
Short name T513
Test name
Test status
Simulation time 282850580678 ps
CPU time 3108.24 seconds
Started Aug 25 06:54:33 AM UTC 24
Finished Aug 25 07:47:01 AM UTC 24
Peak memory 215888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845232425 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3845232425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.3868374603
Short name T120
Test name
Test status
Simulation time 9972805201 ps
CPU time 111.12 seconds
Started Aug 25 06:54:31 AM UTC 24
Finished Aug 25 06:56:25 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868374603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3868374603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_alert_test.2527543929
Short name T318
Test name
Test status
Simulation time 121518810 ps
CPU time 0.87 seconds
Started Aug 25 07:09:56 AM UTC 24
Finished Aug 25 07:09:58 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527543929 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2527543929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.1846306103
Short name T331
Test name
Test status
Simulation time 1397866359 ps
CPU time 105.64 seconds
Started Aug 25 07:09:27 AM UTC 24
Finished Aug 25 07:11:15 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846306103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1846306103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.1557343931
Short name T319
Test name
Test status
Simulation time 5703422779 ps
CPU time 27.77 seconds
Started Aug 25 07:09:33 AM UTC 24
Finished Aug 25 07:10:03 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557343931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1557343931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.2120691589
Short name T392
Test name
Test status
Simulation time 10148627942 ps
CPU time 566.02 seconds
Started Aug 25 07:09:28 AM UTC 24
Finished Aug 25 07:19:02 AM UTC 24
Peak memory 692652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120691589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2120691589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_error.3598001386
Short name T317
Test name
Test status
Simulation time 719575286 ps
CPU time 14.92 seconds
Started Aug 25 07:09:39 AM UTC 24
Finished Aug 25 07:09:55 AM UTC 24
Peak memory 207128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598001386 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3598001386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_long_msg.3227624877
Short name T325
Test name
Test status
Simulation time 2147013079 ps
CPU time 92.39 seconds
Started Aug 25 07:09:17 AM UTC 24
Finished Aug 25 07:10:52 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227624877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3227624877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_smoke.1600506039
Short name T315
Test name
Test status
Simulation time 340768290 ps
CPU time 6.97 seconds
Started Aug 25 07:09:17 AM UTC 24
Finished Aug 25 07:09:25 AM UTC 24
Peak memory 207368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600506039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1600506039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_stress_all.2379212667
Short name T531
Test name
Test status
Simulation time 281432650689 ps
CPU time 4204.98 seconds
Started Aug 25 07:09:55 AM UTC 24
Finished Aug 25 08:20:50 AM UTC 24
Peak memory 815444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379212667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2379212667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.3566978874
Short name T349
Test name
Test status
Simulation time 7959294010 ps
CPU time 200.59 seconds
Started Aug 25 07:09:52 AM UTC 24
Finished Aug 25 07:13:17 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566978874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3566978874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_alert_test.945737591
Short name T324
Test name
Test status
Simulation time 32072286 ps
CPU time 0.88 seconds
Started Aug 25 07:10:48 AM UTC 24
Finished Aug 25 07:10:50 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945737591 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.945737591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.2205427490
Short name T342
Test name
Test status
Simulation time 1811412685 ps
CPU time 152.95 seconds
Started Aug 25 07:10:11 AM UTC 24
Finished Aug 25 07:12:48 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205427490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2205427490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.4152646530
Short name T329
Test name
Test status
Simulation time 11569452513 ps
CPU time 47.58 seconds
Started Aug 25 07:10:21 AM UTC 24
Finished Aug 25 07:11:11 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152646530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4152646530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.524068609
Short name T407
Test name
Test status
Simulation time 10808358448 ps
CPU time 612.54 seconds
Started Aug 25 07:10:18 AM UTC 24
Finished Aug 25 07:20:40 AM UTC 24
Peak memory 688352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524068609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.524068609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_error.4025670129
Short name T347
Test name
Test status
Simulation time 8594851637 ps
CPU time 169.68 seconds
Started Aug 25 07:10:22 AM UTC 24
Finished Aug 25 07:13:16 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025670129 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4025670129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_long_msg.102121626
Short name T326
Test name
Test status
Simulation time 4515152131 ps
CPU time 49.82 seconds
Started Aug 25 07:10:04 AM UTC 24
Finished Aug 25 07:10:55 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102121626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.102121626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_smoke.667139101
Short name T320
Test name
Test status
Simulation time 873253213 ps
CPU time 21.72 seconds
Started Aug 25 07:09:59 AM UTC 24
Finished Aug 25 07:10:22 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667139101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.667139101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_stress_all.2005932119
Short name T517
Test name
Test status
Simulation time 44679996134 ps
CPU time 2275.75 seconds
Started Aug 25 07:10:44 AM UTC 24
Finished Aug 25 07:49:09 AM UTC 24
Peak memory 792844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005932119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2005932119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1138367662
Short name T338
Test name
Test status
Simulation time 1903520894 ps
CPU time 113.73 seconds
Started Aug 25 07:10:33 AM UTC 24
Finished Aug 25 07:12:30 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138367662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1138367662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_alert_test.1885754073
Short name T332
Test name
Test status
Simulation time 131590731 ps
CPU time 0.92 seconds
Started Aug 25 07:11:19 AM UTC 24
Finished Aug 25 07:11:22 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885754073 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1885754073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.1099441894
Short name T344
Test name
Test status
Simulation time 6371400830 ps
CPU time 124.35 seconds
Started Aug 25 07:10:56 AM UTC 24
Finished Aug 25 07:13:03 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099441894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1099441894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.2217143794
Short name T335
Test name
Test status
Simulation time 3437396985 ps
CPU time 49.15 seconds
Started Aug 25 07:11:11 AM UTC 24
Finished Aug 25 07:12:02 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217143794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2217143794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.3770457071
Short name T487
Test name
Test status
Simulation time 16960061633 ps
CPU time 1118.63 seconds
Started Aug 25 07:11:06 AM UTC 24
Finished Aug 25 07:30:00 AM UTC 24
Peak memory 733412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770457071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3770457071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_error.181940316
Short name T367
Test name
Test status
Simulation time 55036576335 ps
CPU time 299.72 seconds
Started Aug 25 07:11:12 AM UTC 24
Finished Aug 25 07:16:17 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181940316 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.181940316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_long_msg.28240182
Short name T333
Test name
Test status
Simulation time 1092244417 ps
CPU time 29.57 seconds
Started Aug 25 07:10:54 AM UTC 24
Finished Aug 25 07:11:25 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28240182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.28240182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_smoke.3908977932
Short name T330
Test name
Test status
Simulation time 264368318 ps
CPU time 18.76 seconds
Started Aug 25 07:10:51 AM UTC 24
Finished Aug 25 07:11:11 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908977932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3908977932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_stress_all.3395110487
Short name T170
Test name
Test status
Simulation time 11655007448 ps
CPU time 1766.4 seconds
Started Aug 25 07:11:17 AM UTC 24
Finished Aug 25 07:41:05 AM UTC 24
Peak memory 790832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395110487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3395110487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.2593328969
Short name T336
Test name
Test status
Simulation time 2384957455 ps
CPU time 62.41 seconds
Started Aug 25 07:11:12 AM UTC 24
Finished Aug 25 07:12:16 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593328969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2593328969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_alert_test.3413340103
Short name T339
Test name
Test status
Simulation time 51685434 ps
CPU time 0.92 seconds
Started Aug 25 07:12:31 AM UTC 24
Finished Aug 25 07:12:33 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413340103 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3413340103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.429061984
Short name T16
Test name
Test status
Simulation time 706708630 ps
CPU time 45.97 seconds
Started Aug 25 07:11:39 AM UTC 24
Finished Aug 25 07:12:26 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429061984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.429061984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.4276343568
Short name T337
Test name
Test status
Simulation time 380081218 ps
CPU time 10.8 seconds
Started Aug 25 07:12:10 AM UTC 24
Finished Aug 25 07:12:23 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276343568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4276343568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.1108177596
Short name T361
Test name
Test status
Simulation time 696767237 ps
CPU time 172.1 seconds
Started Aug 25 07:12:03 AM UTC 24
Finished Aug 25 07:14:58 AM UTC 24
Peak memory 438428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108177596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1108177596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_error.3957171454
Short name T341
Test name
Test status
Simulation time 433612280 ps
CPU time 25.48 seconds
Started Aug 25 07:12:18 AM UTC 24
Finished Aug 25 07:12:45 AM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957171454 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3957171454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_long_msg.3647197235
Short name T364
Test name
Test status
Simulation time 68432670146 ps
CPU time 258.48 seconds
Started Aug 25 07:11:26 AM UTC 24
Finished Aug 25 07:15:49 AM UTC 24
Peak memory 218008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647197235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3647197235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_smoke.2473227234
Short name T334
Test name
Test status
Simulation time 194934096 ps
CPU time 11.89 seconds
Started Aug 25 07:11:23 AM UTC 24
Finished Aug 25 07:11:38 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473227234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2473227234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_stress_all.859582000
Short name T526
Test name
Test status
Simulation time 242913438265 ps
CPU time 3256.61 seconds
Started Aug 25 07:12:28 AM UTC 24
Finished Aug 25 08:07:25 AM UTC 24
Peak memory 756000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859582000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.859582000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.3095106906
Short name T362
Test name
Test status
Simulation time 6862808518 ps
CPU time 184.92 seconds
Started Aug 25 07:12:24 AM UTC 24
Finished Aug 25 07:15:32 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095106906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3095106906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_alert_test.2692154339
Short name T348
Test name
Test status
Simulation time 51614552 ps
CPU time 0.82 seconds
Started Aug 25 07:13:14 AM UTC 24
Finished Aug 25 07:13:16 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692154339 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2692154339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.714199512
Short name T345
Test name
Test status
Simulation time 482329005 ps
CPU time 17.46 seconds
Started Aug 25 07:12:46 AM UTC 24
Finished Aug 25 07:13:05 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714199512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.714199512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.2906450940
Short name T352
Test name
Test status
Simulation time 4762856411 ps
CPU time 62.26 seconds
Started Aug 25 07:12:50 AM UTC 24
Finished Aug 25 07:13:55 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906450940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2906450940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.3264253739
Short name T490
Test name
Test status
Simulation time 4279014372 ps
CPU time 1140.76 seconds
Started Aug 25 07:12:49 AM UTC 24
Finished Aug 25 07:32:06 AM UTC 24
Peak memory 713184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264253739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3264253739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_error.1486168266
Short name T353
Test name
Test status
Simulation time 891102513 ps
CPU time 71.79 seconds
Started Aug 25 07:13:04 AM UTC 24
Finished Aug 25 07:14:18 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486168266 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1486168266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_long_msg.1304288620
Short name T377
Test name
Test status
Simulation time 14030526810 ps
CPU time 253.55 seconds
Started Aug 25 07:12:41 AM UTC 24
Finished Aug 25 07:16:59 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304288620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1304288620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_smoke.1613143435
Short name T343
Test name
Test status
Simulation time 2255447932 ps
CPU time 13.96 seconds
Started Aug 25 07:12:34 AM UTC 24
Finished Aug 25 07:12:49 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613143435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1613143435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_stress_all.421631858
Short name T135
Test name
Test status
Simulation time 37182018 ps
CPU time 0.93 seconds
Started Aug 25 07:13:11 AM UTC 24
Finished Aug 25 07:13:13 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421631858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.421631858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.4212123769
Short name T96
Test name
Test status
Simulation time 2635207726 ps
CPU time 161.47 seconds
Started Aug 25 07:13:06 AM UTC 24
Finished Aug 25 07:15:50 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212123769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4212123769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_alert_test.2008158721
Short name T357
Test name
Test status
Simulation time 45143111 ps
CPU time 0.86 seconds
Started Aug 25 07:14:41 AM UTC 24
Finished Aug 25 07:14:43 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008158721 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2008158721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.955014187
Short name T359
Test name
Test status
Simulation time 1148074171 ps
CPU time 86.58 seconds
Started Aug 25 07:13:20 AM UTC 24
Finished Aug 25 07:14:49 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955014187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.955014187
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.139026505
Short name T358
Test name
Test status
Simulation time 1842569053 ps
CPU time 45.05 seconds
Started Aug 25 07:13:58 AM UTC 24
Finished Aug 25 07:14:45 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139026505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.139026505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.2069097246
Short name T503
Test name
Test status
Simulation time 5942601829 ps
CPU time 1579.81 seconds
Started Aug 25 07:13:30 AM UTC 24
Finished Aug 25 07:40:11 AM UTC 24
Peak memory 774444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069097246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2069097246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_error.2163084494
Short name T387
Test name
Test status
Simulation time 23544356562 ps
CPU time 260.97 seconds
Started Aug 25 07:13:58 AM UTC 24
Finished Aug 25 07:18:24 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163084494 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2163084494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_long_msg.649451940
Short name T365
Test name
Test status
Simulation time 7314327469 ps
CPU time 150.18 seconds
Started Aug 25 07:13:18 AM UTC 24
Finished Aug 25 07:15:51 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649451940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.649451940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_smoke.4261239473
Short name T350
Test name
Test status
Simulation time 1833076539 ps
CPU time 10.53 seconds
Started Aug 25 07:13:18 AM UTC 24
Finished Aug 25 07:13:29 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261239473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4261239473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_stress_all.3980657733
Short name T134
Test name
Test status
Simulation time 1962353433 ps
CPU time 32.41 seconds
Started Aug 25 07:14:38 AM UTC 24
Finished Aug 25 07:15:12 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980657733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3980657733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.4213677676
Short name T95
Test name
Test status
Simulation time 2400373941 ps
CPU time 50.6 seconds
Started Aug 25 07:14:19 AM UTC 24
Finished Aug 25 07:15:12 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213677676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4213677676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_alert_test.904427760
Short name T363
Test name
Test status
Simulation time 24262578 ps
CPU time 0.8 seconds
Started Aug 25 07:15:34 AM UTC 24
Finished Aug 25 07:15:36 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904427760 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.904427760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.1558898425
Short name T371
Test name
Test status
Simulation time 3026161145 ps
CPU time 112.11 seconds
Started Aug 25 07:14:46 AM UTC 24
Finished Aug 25 07:16:40 AM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558898425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1558898425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.2065119509
Short name T368
Test name
Test status
Simulation time 20808249875 ps
CPU time 92.53 seconds
Started Aug 25 07:14:50 AM UTC 24
Finished Aug 25 07:16:25 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065119509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2065119509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.3383865485
Short name T434
Test name
Test status
Simulation time 12033387293 ps
CPU time 439.92 seconds
Started Aug 25 07:14:50 AM UTC 24
Finished Aug 25 07:22:17 AM UTC 24
Peak memory 653864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383865485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3383865485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_error.1010455898
Short name T378
Test name
Test status
Simulation time 16403389728 ps
CPU time 119.08 seconds
Started Aug 25 07:15:00 AM UTC 24
Finished Aug 25 07:17:02 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010455898 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1010455898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_long_msg.607433798
Short name T379
Test name
Test status
Simulation time 11472911762 ps
CPU time 140.67 seconds
Started Aug 25 07:14:44 AM UTC 24
Finished Aug 25 07:17:07 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607433798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.607433798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_smoke.2506278948
Short name T360
Test name
Test status
Simulation time 77137127 ps
CPU time 4.72 seconds
Started Aug 25 07:14:44 AM UTC 24
Finished Aug 25 07:14:49 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506278948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2506278948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_stress_all.131641732
Short name T523
Test name
Test status
Simulation time 197113845661 ps
CPU time 2594.99 seconds
Started Aug 25 07:15:13 AM UTC 24
Finished Aug 25 07:59:01 AM UTC 24
Peak memory 780512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131641732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.131641732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.2900659996
Short name T374
Test name
Test status
Simulation time 1503017884 ps
CPU time 93.97 seconds
Started Aug 25 07:15:13 AM UTC 24
Finished Aug 25 07:16:50 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900659996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2900659996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_alert_test.2129513467
Short name T372
Test name
Test status
Simulation time 13450856 ps
CPU time 0.93 seconds
Started Aug 25 07:16:43 AM UTC 24
Finished Aug 25 07:16:45 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129513467 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2129513467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.829859623
Short name T17
Test name
Test status
Simulation time 1778200931 ps
CPU time 160.27 seconds
Started Aug 25 07:15:53 AM UTC 24
Finished Aug 25 07:18:36 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829859623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.829859623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.1748014691
Short name T376
Test name
Test status
Simulation time 10435669195 ps
CPU time 57.9 seconds
Started Aug 25 07:15:54 AM UTC 24
Finished Aug 25 07:16:54 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748014691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1748014691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.2150798803
Short name T403
Test name
Test status
Simulation time 1209091152 ps
CPU time 261.02 seconds
Started Aug 25 07:15:53 AM UTC 24
Finished Aug 25 07:20:18 AM UTC 24
Peak memory 633044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150798803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2150798803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_error.2911329865
Short name T385
Test name
Test status
Simulation time 1583154454 ps
CPU time 115.06 seconds
Started Aug 25 07:16:18 AM UTC 24
Finished Aug 25 07:18:16 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911329865 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2911329865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_long_msg.605711871
Short name T390
Test name
Test status
Simulation time 4837226444 ps
CPU time 181.46 seconds
Started Aug 25 07:15:53 AM UTC 24
Finished Aug 25 07:18:58 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605711871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.605711871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_smoke.1534642694
Short name T366
Test name
Test status
Simulation time 6523891192 ps
CPU time 14.15 seconds
Started Aug 25 07:15:37 AM UTC 24
Finished Aug 25 07:15:53 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534642694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1534642694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_stress_all.3405665736
Short name T79
Test name
Test status
Simulation time 59288612855 ps
CPU time 1383.59 seconds
Started Aug 25 07:16:28 AM UTC 24
Finished Aug 25 07:39:52 AM UTC 24
Peak memory 690400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405665736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3405665736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.992081772
Short name T389
Test name
Test status
Simulation time 21746776559 ps
CPU time 132.93 seconds
Started Aug 25 07:16:28 AM UTC 24
Finished Aug 25 07:18:45 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992081772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.992081772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_alert_test.92654089
Short name T380
Test name
Test status
Simulation time 13099176 ps
CPU time 0.85 seconds
Started Aug 25 07:17:09 AM UTC 24
Finished Aug 25 07:17:11 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92654089 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.92654089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.2805672972
Short name T383
Test name
Test status
Simulation time 583446662 ps
CPU time 48.69 seconds
Started Aug 25 07:16:53 AM UTC 24
Finished Aug 25 07:17:43 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805672972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2805672972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.1993596118
Short name T386
Test name
Test status
Simulation time 16179422537 ps
CPU time 84.14 seconds
Started Aug 25 07:16:54 AM UTC 24
Finished Aug 25 07:18:21 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993596118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1993596118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2754366044
Short name T499
Test name
Test status
Simulation time 5222876455 ps
CPU time 1276.28 seconds
Started Aug 25 07:16:53 AM UTC 24
Finished Aug 25 07:38:26 AM UTC 24
Peak memory 715040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754366044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2754366044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_error.2305278744
Short name T425
Test name
Test status
Simulation time 13757560780 ps
CPU time 278.43 seconds
Started Aug 25 07:16:55 AM UTC 24
Finished Aug 25 07:21:39 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305278744 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2305278744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_long_msg.1567787843
Short name T381
Test name
Test status
Simulation time 1190301024 ps
CPU time 24.56 seconds
Started Aug 25 07:16:46 AM UTC 24
Finished Aug 25 07:17:12 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567787843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1567787843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_smoke.2178719629
Short name T375
Test name
Test status
Simulation time 585401487 ps
CPU time 8.68 seconds
Started Aug 25 07:16:43 AM UTC 24
Finished Aug 25 07:16:53 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178719629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2178719629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_stress_all.2972076039
Short name T498
Test name
Test status
Simulation time 182916178156 ps
CPU time 1196.74 seconds
Started Aug 25 07:17:03 AM UTC 24
Finished Aug 25 07:37:16 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972076039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2972076039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.1869614005
Short name T394
Test name
Test status
Simulation time 41864822174 ps
CPU time 129.27 seconds
Started Aug 25 07:17:01 AM UTC 24
Finished Aug 25 07:19:13 AM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869614005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1869614005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_alert_test.2349191770
Short name T388
Test name
Test status
Simulation time 39993934 ps
CPU time 0.78 seconds
Started Aug 25 07:18:38 AM UTC 24
Finished Aug 25 07:18:40 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349191770 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2349191770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.1883827520
Short name T384
Test name
Test status
Simulation time 471061775 ps
CPU time 36.54 seconds
Started Aug 25 07:17:37 AM UTC 24
Finished Aug 25 07:18:15 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883827520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1883827520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.3774143376
Short name T169
Test name
Test status
Simulation time 1252390811 ps
CPU time 49.17 seconds
Started Aug 25 07:18:17 AM UTC 24
Finished Aug 25 07:19:08 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774143376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3774143376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.2100021698
Short name T393
Test name
Test status
Simulation time 496732558 ps
CPU time 86.15 seconds
Started Aug 25 07:17:44 AM UTC 24
Finished Aug 25 07:19:13 AM UTC 24
Peak memory 387432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100021698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2100021698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_error.121424731
Short name T411
Test name
Test status
Simulation time 20739824053 ps
CPU time 162.98 seconds
Started Aug 25 07:18:17 AM UTC 24
Finished Aug 25 07:21:04 AM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121424731 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.121424731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_long_msg.2250078268
Short name T417
Test name
Test status
Simulation time 11556648188 ps
CPU time 244.47 seconds
Started Aug 25 07:17:13 AM UTC 24
Finished Aug 25 07:21:22 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250078268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2250078268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_smoke.2060532691
Short name T382
Test name
Test status
Simulation time 6690089748 ps
CPU time 21.9 seconds
Started Aug 25 07:17:12 AM UTC 24
Finished Aug 25 07:17:36 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060532691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2060532691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_stress_all.1916523135
Short name T481
Test name
Test status
Simulation time 14429297435 ps
CPU time 578.37 seconds
Started Aug 25 07:18:25 AM UTC 24
Finished Aug 25 07:28:13 AM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916523135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1916523135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.4035371228
Short name T410
Test name
Test status
Simulation time 2273086974 ps
CPU time 151.12 seconds
Started Aug 25 07:18:21 AM UTC 24
Finished Aug 25 07:20:56 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035371228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4035371228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_alert_test.8836879
Short name T75
Test name
Test status
Simulation time 19748487 ps
CPU time 0.9 seconds
Started Aug 25 06:55:31 AM UTC 24
Finished Aug 25 06:55:33 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8836879 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.8836879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.4239236409
Short name T10
Test name
Test status
Simulation time 1770909506 ps
CPU time 20.31 seconds
Started Aug 25 06:54:40 AM UTC 24
Finished Aug 25 06:55:02 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239236409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4239236409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.1099185509
Short name T33
Test name
Test status
Simulation time 757547020 ps
CPU time 25.78 seconds
Started Aug 25 06:54:58 AM UTC 24
Finished Aug 25 06:55:25 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099185509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1099185509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.2619235154
Short name T186
Test name
Test status
Simulation time 2101442631 ps
CPU time 113.35 seconds
Started Aug 25 06:54:55 AM UTC 24
Finished Aug 25 06:56:51 AM UTC 24
Peak memory 430512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619235154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2619235154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_error.2743962844
Short name T147
Test name
Test status
Simulation time 3493014561 ps
CPU time 243.38 seconds
Started Aug 25 06:54:58 AM UTC 24
Finished Aug 25 06:59:05 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743962844 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2743962844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_long_msg.833127660
Short name T207
Test name
Test status
Simulation time 16689599589 ps
CPU time 293.18 seconds
Started Aug 25 06:54:40 AM UTC 24
Finished Aug 25 06:59:38 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833127660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.833127660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.2204232567
Short name T67
Test name
Test status
Simulation time 38297264 ps
CPU time 1.26 seconds
Started Aug 25 06:55:29 AM UTC 24
Finished Aug 25 06:55:31 AM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204232567 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2204232567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_smoke.3849541912
Short name T25
Test name
Test status
Simulation time 581852290 ps
CPU time 13.49 seconds
Started Aug 25 06:54:40 AM UTC 24
Finished Aug 25 06:54:55 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849541912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3849541912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_stress_all.2677761953
Short name T505
Test name
Test status
Simulation time 202587994139 ps
CPU time 2770.49 seconds
Started Aug 25 06:55:25 AM UTC 24
Finished Aug 25 07:42:11 AM UTC 24
Peak memory 778536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677761953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2677761953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.4268082785
Short name T31
Test name
Test status
Simulation time 2838300898 ps
CPU time 223.97 seconds
Started Aug 25 06:55:25 AM UTC 24
Finished Aug 25 06:59:13 AM UTC 24
Peak memory 217996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42680827
85 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.4268082785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.230151094
Short name T185
Test name
Test status
Simulation time 12539475592 ps
CPU time 96.17 seconds
Started Aug 25 06:55:05 AM UTC 24
Finished Aug 25 06:56:43 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230151094 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.230151094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.3539448363
Short name T188
Test name
Test status
Simulation time 5007557861 ps
CPU time 118.48 seconds
Started Aug 25 06:55:10 AM UTC 24
Finished Aug 25 06:57:11 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539448363 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3539448363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.591639733
Short name T187
Test name
Test status
Simulation time 9406374204 ps
CPU time 112.34 seconds
Started Aug 25 06:55:12 AM UTC 24
Finished Aug 25 06:57:07 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591639733 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.591639733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.2085446020
Short name T292
Test name
Test status
Simulation time 31917176148 ps
CPU time 714.84 seconds
Started Aug 25 06:54:59 AM UTC 24
Finished Aug 25 07:07:04 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085446020 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2085446020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.456272300
Short name T520
Test name
Test status
Simulation time 279922311396 ps
CPU time 3305.2 seconds
Started Aug 25 06:55:00 AM UTC 24
Finished Aug 25 07:50:49 AM UTC 24
Peak memory 223048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456272300 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.456272300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.2360094618
Short name T507
Test name
Test status
Simulation time 310129442057 ps
CPU time 2866.37 seconds
Started Aug 25 06:55:02 AM UTC 24
Finished Aug 25 07:43:29 AM UTC 24
Peak memory 215712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360094618 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2360094618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.1686096066
Short name T127
Test name
Test status
Simulation time 6929631241 ps
CPU time 137.17 seconds
Started Aug 25 06:54:59 AM UTC 24
Finished Aug 25 06:57:19 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686096066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1686096066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_alert_test.3679027406
Short name T396
Test name
Test status
Simulation time 13492449 ps
CPU time 0.86 seconds
Started Aug 25 07:19:30 AM UTC 24
Finished Aug 25 07:19:32 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679027406 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3679027406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.1570808045
Short name T397
Test name
Test status
Simulation time 3349050467 ps
CPU time 43.32 seconds
Started Aug 25 07:18:59 AM UTC 24
Finished Aug 25 07:19:44 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570808045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1570808045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.2917685126
Short name T400
Test name
Test status
Simulation time 6212159759 ps
CPU time 62.76 seconds
Started Aug 25 07:19:03 AM UTC 24
Finished Aug 25 07:20:08 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917685126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2917685126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.3883733284
Short name T495
Test name
Test status
Simulation time 23613374276 ps
CPU time 902.39 seconds
Started Aug 25 07:19:03 AM UTC 24
Finished Aug 25 07:34:19 AM UTC 24
Peak memory 727516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883733284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3883733284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_error.1758050698
Short name T422
Test name
Test status
Simulation time 15062061004 ps
CPU time 143.93 seconds
Started Aug 25 07:19:10 AM UTC 24
Finished Aug 25 07:21:36 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758050698 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1758050698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1913962883
Short name T414
Test name
Test status
Simulation time 25587305744 ps
CPU time 138 seconds
Started Aug 25 07:18:47 AM UTC 24
Finished Aug 25 07:21:09 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913962883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1913962883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_smoke.1127010924
Short name T391
Test name
Test status
Simulation time 927834206 ps
CPU time 19.1 seconds
Started Aug 25 07:18:41 AM UTC 24
Finished Aug 25 07:19:02 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127010924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1127010924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_stress_all.3249248325
Short name T533
Test name
Test status
Simulation time 507763723136 ps
CPU time 7395.62 seconds
Started Aug 25 07:19:14 AM UTC 24
Finished Aug 25 09:24:03 AM UTC 24
Peak memory 905536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249248325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3249248325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.3208118721
Short name T395
Test name
Test status
Simulation time 425199953 ps
CPU time 12.77 seconds
Started Aug 25 07:19:14 AM UTC 24
Finished Aug 25 07:19:29 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208118721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3208118721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_alert_test.2492441864
Short name T404
Test name
Test status
Simulation time 67378184 ps
CPU time 0.81 seconds
Started Aug 25 07:20:20 AM UTC 24
Finished Aug 25 07:20:22 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492441864 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2492441864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.2354533107
Short name T415
Test name
Test status
Simulation time 1605299278 ps
CPU time 80.85 seconds
Started Aug 25 07:19:47 AM UTC 24
Finished Aug 25 07:21:10 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354533107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2354533107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.1650117368
Short name T412
Test name
Test status
Simulation time 9210982971 ps
CPU time 60.76 seconds
Started Aug 25 07:20:03 AM UTC 24
Finished Aug 25 07:21:06 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650117368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1650117368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.815497566
Short name T399
Test name
Test status
Simulation time 45988270 ps
CPU time 1.84 seconds
Started Aug 25 07:19:59 AM UTC 24
Finished Aug 25 07:20:02 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815497566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.815497566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_error.3909201287
Short name T435
Test name
Test status
Simulation time 33943792111 ps
CPU time 149.59 seconds
Started Aug 25 07:20:09 AM UTC 24
Finished Aug 25 07:22:43 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909201287 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3909201287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_long_msg.95448101
Short name T402
Test name
Test status
Simulation time 3092620251 ps
CPU time 28.84 seconds
Started Aug 25 07:19:45 AM UTC 24
Finished Aug 25 07:20:16 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95448101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.95448101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_smoke.729790504
Short name T398
Test name
Test status
Simulation time 461230383 ps
CPU time 11.32 seconds
Started Aug 25 07:19:33 AM UTC 24
Finished Aug 25 07:19:46 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729790504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.729790504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_stress_all.3499542918
Short name T527
Test name
Test status
Simulation time 129192385403 ps
CPU time 2825.88 seconds
Started Aug 25 07:20:16 AM UTC 24
Finished Aug 25 08:07:59 AM UTC 24
Peak memory 813336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499542918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3499542918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.1637808006
Short name T98
Test name
Test status
Simulation time 7986858118 ps
CPU time 42.3 seconds
Started Aug 25 07:20:12 AM UTC 24
Finished Aug 25 07:20:56 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637808006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1637808006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_alert_test.3055921633
Short name T413
Test name
Test status
Simulation time 11265659 ps
CPU time 0.8 seconds
Started Aug 25 07:21:05 AM UTC 24
Finished Aug 25 07:21:07 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055921633 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3055921633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.1922342
Short name T409
Test name
Test status
Simulation time 801265238 ps
CPU time 12.71 seconds
Started Aug 25 07:20:36 AM UTC 24
Finished Aug 25 07:20:50 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM
_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1922342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.1163368951
Short name T167
Test name
Test status
Simulation time 1103983069 ps
CPU time 81.91 seconds
Started Aug 25 07:20:50 AM UTC 24
Finished Aug 25 07:22:14 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163368951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1163368951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.4084257306
Short name T491
Test name
Test status
Simulation time 2986859444 ps
CPU time 714.27 seconds
Started Aug 25 07:20:42 AM UTC 24
Finished Aug 25 07:32:45 AM UTC 24
Peak memory 510232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084257306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4084257306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_error.3474266997
Short name T427
Test name
Test status
Simulation time 710441541 ps
CPU time 54.67 seconds
Started Aug 25 07:20:51 AM UTC 24
Finished Aug 25 07:21:48 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474266997 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3474266997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_long_msg.994730505
Short name T420
Test name
Test status
Simulation time 827926775 ps
CPU time 53.36 seconds
Started Aug 25 07:20:33 AM UTC 24
Finished Aug 25 07:21:29 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994730505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.994730505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_smoke.2729327148
Short name T406
Test name
Test status
Simulation time 2106418381 ps
CPU time 11.22 seconds
Started Aug 25 07:20:23 AM UTC 24
Finished Aug 25 07:20:36 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729327148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2729327148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_stress_all.1693018902
Short name T496
Test name
Test status
Simulation time 67316838545 ps
CPU time 815.62 seconds
Started Aug 25 07:20:58 AM UTC 24
Finished Aug 25 07:34:46 AM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693018902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1693018902
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.254880479
Short name T424
Test name
Test status
Simulation time 5797185451 ps
CPU time 39.2 seconds
Started Aug 25 07:20:57 AM UTC 24
Finished Aug 25 07:21:38 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254880479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.254880479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_alert_test.3076065932
Short name T421
Test name
Test status
Simulation time 82615740 ps
CPU time 0.84 seconds
Started Aug 25 07:21:31 AM UTC 24
Finished Aug 25 07:21:33 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076065932 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3076065932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.2366988443
Short name T423
Test name
Test status
Simulation time 324356359 ps
CPU time 25.73 seconds
Started Aug 25 07:21:10 AM UTC 24
Finished Aug 25 07:21:37 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366988443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2366988443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.588541263
Short name T418
Test name
Test status
Simulation time 529120222 ps
CPU time 7.28 seconds
Started Aug 25 07:21:20 AM UTC 24
Finished Aug 25 07:21:28 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588541263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.588541263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.1137431707
Short name T488
Test name
Test status
Simulation time 2964911151 ps
CPU time 627.16 seconds
Started Aug 25 07:21:12 AM UTC 24
Finished Aug 25 07:31:48 AM UTC 24
Peak memory 749848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137431707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1137431707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_error.2392101543
Short name T450
Test name
Test status
Simulation time 2078216932 ps
CPU time 155.67 seconds
Started Aug 25 07:21:24 AM UTC 24
Finished Aug 25 07:24:03 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392101543 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2392101543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_long_msg.2505624623
Short name T449
Test name
Test status
Simulation time 13013565046 ps
CPU time 162.66 seconds
Started Aug 25 07:21:09 AM UTC 24
Finished Aug 25 07:23:55 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505624623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2505624623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_smoke.1894001433
Short name T416
Test name
Test status
Simulation time 7115880331 ps
CPU time 11.6 seconds
Started Aug 25 07:21:06 AM UTC 24
Finished Aug 25 07:21:19 AM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894001433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1894001433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_stress_all.1658471808
Short name T519
Test name
Test status
Simulation time 11237115865 ps
CPU time 1670.37 seconds
Started Aug 25 07:21:31 AM UTC 24
Finished Aug 25 07:49:44 AM UTC 24
Peak memory 743652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658471808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1658471808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2905351671
Short name T445
Test name
Test status
Simulation time 7544984392 ps
CPU time 118.4 seconds
Started Aug 25 07:21:31 AM UTC 24
Finished Aug 25 07:23:32 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905351671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2905351671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2491344640
Short name T429
Test name
Test status
Simulation time 15745151 ps
CPU time 0.91 seconds
Started Aug 25 07:21:49 AM UTC 24
Finished Aug 25 07:21:51 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491344640 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2491344640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.1875238811
Short name T443
Test name
Test status
Simulation time 1196937680 ps
CPU time 94.08 seconds
Started Aug 25 07:21:38 AM UTC 24
Finished Aug 25 07:23:15 AM UTC 24
Peak memory 206928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875238811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1875238811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.1680649101
Short name T433
Test name
Test status
Simulation time 1240932275 ps
CPU time 25.02 seconds
Started Aug 25 07:21:41 AM UTC 24
Finished Aug 25 07:22:07 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680649101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1680649101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.2006227830
Short name T497
Test name
Test status
Simulation time 46743836254 ps
CPU time 922.15 seconds
Started Aug 25 07:21:38 AM UTC 24
Finished Aug 25 07:37:14 AM UTC 24
Peak memory 713060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006227830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2006227830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_error.1880617225
Short name T444
Test name
Test status
Simulation time 3173277496 ps
CPU time 93.67 seconds
Started Aug 25 07:21:41 AM UTC 24
Finished Aug 25 07:23:17 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880617225 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1880617225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_long_msg.3532502508
Short name T428
Test name
Test status
Simulation time 99785989 ps
CPU time 8.88 seconds
Started Aug 25 07:21:38 AM UTC 24
Finished Aug 25 07:21:49 AM UTC 24
Peak memory 206768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532502508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3532502508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_smoke.1805405173
Short name T426
Test name
Test status
Simulation time 398827198 ps
CPU time 5.81 seconds
Started Aug 25 07:21:34 AM UTC 24
Finished Aug 25 07:21:42 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805405173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1805405173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_stress_all.2192925163
Short name T486
Test name
Test status
Simulation time 20041924968 ps
CPU time 468.5 seconds
Started Aug 25 07:21:49 AM UTC 24
Finished Aug 25 07:29:45 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192925163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2192925163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.3313722431
Short name T441
Test name
Test status
Simulation time 1194384207 ps
CPU time 82.56 seconds
Started Aug 25 07:21:43 AM UTC 24
Finished Aug 25 07:23:08 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313722431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3313722431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_alert_test.1918499143
Short name T437
Test name
Test status
Simulation time 13950840 ps
CPU time 0.78 seconds
Started Aug 25 07:22:57 AM UTC 24
Finished Aug 25 07:22:59 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918499143 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1918499143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.1869200100
Short name T440
Test name
Test status
Simulation time 5248055340 ps
CPU time 53.12 seconds
Started Aug 25 07:22:11 AM UTC 24
Finished Aug 25 07:23:06 AM UTC 24
Peak memory 215824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869200100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1869200100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.325880001
Short name T436
Test name
Test status
Simulation time 7261864388 ps
CPU time 43.21 seconds
Started Aug 25 07:22:11 AM UTC 24
Finished Aug 25 07:22:56 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325880001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.325880001
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.1756277303
Short name T493
Test name
Test status
Simulation time 5004532525 ps
CPU time 634.29 seconds
Started Aug 25 07:22:11 AM UTC 24
Finished Aug 25 07:32:54 AM UTC 24
Peak memory 739548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756277303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1756277303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_error.2233713153
Short name T448
Test name
Test status
Simulation time 24632942091 ps
CPU time 95.44 seconds
Started Aug 25 07:22:15 AM UTC 24
Finished Aug 25 07:23:53 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233713153 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2233713153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_long_msg.892122644
Short name T442
Test name
Test status
Simulation time 30454586019 ps
CPU time 69.85 seconds
Started Aug 25 07:22:00 AM UTC 24
Finished Aug 25 07:23:12 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892122644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.892122644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_smoke.2301490072
Short name T430
Test name
Test status
Simulation time 328771671 ps
CPU time 5.85 seconds
Started Aug 25 07:21:52 AM UTC 24
Finished Aug 25 07:22:00 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301490072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2301490072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_stress_all.1414839194
Short name T81
Test name
Test status
Simulation time 353871901420 ps
CPU time 1586.17 seconds
Started Aug 25 07:22:44 AM UTC 24
Finished Aug 25 07:49:33 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414839194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1414839194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.1790925810
Short name T464
Test name
Test status
Simulation time 19664143208 ps
CPU time 178.08 seconds
Started Aug 25 07:22:19 AM UTC 24
Finished Aug 25 07:25:21 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790925810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1790925810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_alert_test.1945190490
Short name T446
Test name
Test status
Simulation time 43436518 ps
CPU time 0.8 seconds
Started Aug 25 07:23:33 AM UTC 24
Finished Aug 25 07:23:35 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945190490 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1945190490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.3257205158
Short name T459
Test name
Test status
Simulation time 1426588876 ps
CPU time 110.46 seconds
Started Aug 25 07:23:07 AM UTC 24
Finished Aug 25 07:25:00 AM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257205158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3257205158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.1896274815
Short name T171
Test name
Test status
Simulation time 356350936 ps
CPU time 25.14 seconds
Started Aug 25 07:23:09 AM UTC 24
Finished Aug 25 07:23:36 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896274815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1896274815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.2588485840
Short name T461
Test name
Test status
Simulation time 3530325074 ps
CPU time 116.28 seconds
Started Aug 25 07:23:07 AM UTC 24
Finished Aug 25 07:25:06 AM UTC 24
Peak memory 442644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588485840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2588485840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_error.685435904
Short name T452
Test name
Test status
Simulation time 2309900280 ps
CPU time 76.57 seconds
Started Aug 25 07:23:13 AM UTC 24
Finished Aug 25 07:24:32 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685435904 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.685435904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_long_msg.3280847712
Short name T474
Test name
Test status
Simulation time 24822933070 ps
CPU time 216.71 seconds
Started Aug 25 07:23:04 AM UTC 24
Finished Aug 25 07:26:45 AM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280847712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3280847712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_smoke.235079500
Short name T438
Test name
Test status
Simulation time 184028443 ps
CPU time 2.14 seconds
Started Aug 25 07:23:00 AM UTC 24
Finished Aug 25 07:23:03 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235079500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.235079500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_stress_all.2158211606
Short name T36
Test name
Test status
Simulation time 183805850463 ps
CPU time 3214.7 seconds
Started Aug 25 07:23:19 AM UTC 24
Finished Aug 25 08:17:34 AM UTC 24
Peak memory 803248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158211606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2158211606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.3792277838
Short name T462
Test name
Test status
Simulation time 23274573619 ps
CPU time 108.94 seconds
Started Aug 25 07:23:16 AM UTC 24
Finished Aug 25 07:25:08 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792277838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3792277838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_alert_test.3923523283
Short name T456
Test name
Test status
Simulation time 10789752 ps
CPU time 0.93 seconds
Started Aug 25 07:24:42 AM UTC 24
Finished Aug 25 07:24:44 AM UTC 24
Peak memory 203176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923523283 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3923523283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.3732917702
Short name T454
Test name
Test status
Simulation time 3835445054 ps
CPU time 52.79 seconds
Started Aug 25 07:23:42 AM UTC 24
Finished Aug 25 07:24:37 AM UTC 24
Peak memory 207556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732917702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3732917702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.2791391232
Short name T460
Test name
Test status
Simulation time 53478948202 ps
CPU time 62.48 seconds
Started Aug 25 07:23:57 AM UTC 24
Finished Aug 25 07:25:01 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791391232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2791391232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2692623151
Short name T479
Test name
Test status
Simulation time 7121147257 ps
CPU time 238.61 seconds
Started Aug 25 07:23:54 AM UTC 24
Finished Aug 25 07:27:57 AM UTC 24
Peak memory 677952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692623151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2692623151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_error.1467088913
Short name T451
Test name
Test status
Simulation time 1158491076 ps
CPU time 22.59 seconds
Started Aug 25 07:24:04 AM UTC 24
Finished Aug 25 07:24:28 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467088913 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1467088913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_long_msg.4119143416
Short name T455
Test name
Test status
Simulation time 3341758747 ps
CPU time 63.36 seconds
Started Aug 25 07:23:36 AM UTC 24
Finished Aug 25 07:24:42 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119143416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4119143416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_smoke.1240697060
Short name T447
Test name
Test status
Simulation time 684170611 ps
CPU time 4.67 seconds
Started Aug 25 07:23:36 AM UTC 24
Finished Aug 25 07:23:42 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240697060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1240697060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2884388929
Short name T483
Test name
Test status
Simulation time 44550989253 ps
CPU time 260.89 seconds
Started Aug 25 07:24:33 AM UTC 24
Finished Aug 25 07:28:59 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884388929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2884388929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.2285401275
Short name T469
Test name
Test status
Simulation time 11343319264 ps
CPU time 81.6 seconds
Started Aug 25 07:24:30 AM UTC 24
Finished Aug 25 07:25:53 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285401275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2285401275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_alert_test.1917515682
Short name T463
Test name
Test status
Simulation time 41507258 ps
CPU time 0.91 seconds
Started Aug 25 07:25:09 AM UTC 24
Finished Aug 25 07:25:11 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917515682 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1917515682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.3325571579
Short name T467
Test name
Test status
Simulation time 2371034819 ps
CPU time 46.47 seconds
Started Aug 25 07:24:45 AM UTC 24
Finished Aug 25 07:25:33 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325571579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3325571579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.2148560073
Short name T473
Test name
Test status
Simulation time 7175361168 ps
CPU time 91.56 seconds
Started Aug 25 07:24:59 AM UTC 24
Finished Aug 25 07:26:32 AM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148560073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2148560073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.1981192651
Short name T511
Test name
Test status
Simulation time 5121662295 ps
CPU time 1299.87 seconds
Started Aug 25 07:24:52 AM UTC 24
Finished Aug 25 07:46:49 AM UTC 24
Peak memory 772352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981192651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1981192651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_error.2958518489
Short name T477
Test name
Test status
Simulation time 28171366787 ps
CPU time 132.1 seconds
Started Aug 25 07:25:03 AM UTC 24
Finished Aug 25 07:27:18 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958518489 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2958518489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_long_msg.3933408562
Short name T482
Test name
Test status
Simulation time 5337230984 ps
CPU time 219.97 seconds
Started Aug 25 07:24:43 AM UTC 24
Finished Aug 25 07:28:28 AM UTC 24
Peak memory 215888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933408562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3933408562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_smoke.1016767889
Short name T457
Test name
Test status
Simulation time 474644669 ps
CPU time 7.85 seconds
Started Aug 25 07:24:42 AM UTC 24
Finished Aug 25 07:24:51 AM UTC 24
Peak memory 206864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016767889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1016767889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_stress_all.126640907
Short name T501
Test name
Test status
Simulation time 11505283001 ps
CPU time 882.75 seconds
Started Aug 25 07:25:07 AM UTC 24
Finished Aug 25 07:40:03 AM UTC 24
Peak memory 645380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126640907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.126640907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.2847157541
Short name T470
Test name
Test status
Simulation time 1098543848 ps
CPU time 51 seconds
Started Aug 25 07:25:03 AM UTC 24
Finished Aug 25 07:25:55 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847157541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2847157541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_alert_test.2155083510
Short name T472
Test name
Test status
Simulation time 13000190 ps
CPU time 0.89 seconds
Started Aug 25 07:26:03 AM UTC 24
Finished Aug 25 07:26:05 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155083510 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2155083510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.165362887
Short name T468
Test name
Test status
Simulation time 234198036 ps
CPU time 18.33 seconds
Started Aug 25 07:25:26 AM UTC 24
Finished Aug 25 07:25:46 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165362887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.165362887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.1655844809
Short name T471
Test name
Test status
Simulation time 381957619 ps
CPU time 26.56 seconds
Started Aug 25 07:25:34 AM UTC 24
Finished Aug 25 07:26:02 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655844809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1655844809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.2567468885
Short name T502
Test name
Test status
Simulation time 3876538465 ps
CPU time 864.3 seconds
Started Aug 25 07:25:31 AM UTC 24
Finished Aug 25 07:40:07 AM UTC 24
Peak memory 749784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567468885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2567468885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_error.3960231606
Short name T475
Test name
Test status
Simulation time 3201230299 ps
CPU time 61.1 seconds
Started Aug 25 07:25:47 AM UTC 24
Finished Aug 25 07:26:50 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960231606 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3960231606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2603993724
Short name T476
Test name
Test status
Simulation time 2738627889 ps
CPU time 99.96 seconds
Started Aug 25 07:25:22 AM UTC 24
Finished Aug 25 07:27:05 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603993724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2603993724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_smoke.1012211071
Short name T466
Test name
Test status
Simulation time 264387247 ps
CPU time 16.45 seconds
Started Aug 25 07:25:12 AM UTC 24
Finished Aug 25 07:25:30 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012211071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1012211071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_stress_all.3138073597
Short name T525
Test name
Test status
Simulation time 59531475343 ps
CPU time 2388.29 seconds
Started Aug 25 07:25:57 AM UTC 24
Finished Aug 25 08:06:18 AM UTC 24
Peak memory 770328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138073597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3138073597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.1293096778
Short name T480
Test name
Test status
Simulation time 1746763142 ps
CPU time 126.12 seconds
Started Aug 25 07:25:54 AM UTC 24
Finished Aug 25 07:28:04 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293096778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1293096778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_alert_test.3751082663
Short name T177
Test name
Test status
Simulation time 14646775 ps
CPU time 0.93 seconds
Started Aug 25 06:55:48 AM UTC 24
Finished Aug 25 06:55:50 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751082663 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3751082663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.2115181126
Short name T162
Test name
Test status
Simulation time 2622586500 ps
CPU time 103.33 seconds
Started Aug 25 06:55:34 AM UTC 24
Finished Aug 25 06:57:20 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115181126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2115181126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3390910386
Short name T176
Test name
Test status
Simulation time 454904150 ps
CPU time 3.77 seconds
Started Aug 25 06:55:36 AM UTC 24
Finished Aug 25 06:55:41 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390910386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3390910386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.3135228782
Short name T195
Test name
Test status
Simulation time 1124806684 ps
CPU time 205.23 seconds
Started Aug 25 06:55:36 AM UTC 24
Finished Aug 25 06:59:05 AM UTC 24
Peak memory 641248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135228782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3135228782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_error.2424548502
Short name T230
Test name
Test status
Simulation time 20068891161 ps
CPU time 344.85 seconds
Started Aug 25 06:55:39 AM UTC 24
Finished Aug 25 07:01:30 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424548502 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2424548502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_long_msg.3059063739
Short name T159
Test name
Test status
Simulation time 760311552 ps
CPU time 16.38 seconds
Started Aug 25 06:55:33 AM UTC 24
Finished Aug 25 06:55:51 AM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059063739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3059063739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/5.hmac_smoke.331514713
Short name T148
Test name
Test status
Simulation time 787833177 ps
CPU time 13.6 seconds
Started Aug 25 06:55:32 AM UTC 24
Finished Aug 25 06:55:47 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331514713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.331514713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_alert_test.1489975625
Short name T179
Test name
Test status
Simulation time 33431470 ps
CPU time 0.81 seconds
Started Aug 25 06:56:09 AM UTC 24
Finished Aug 25 06:56:12 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489975625 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1489975625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.372757351
Short name T161
Test name
Test status
Simulation time 140211427 ps
CPU time 11.55 seconds
Started Aug 25 06:55:52 AM UTC 24
Finished Aug 25 06:56:05 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372757351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.372757351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.4127712873
Short name T163
Test name
Test status
Simulation time 169026181 ps
CPU time 8.44 seconds
Started Aug 25 06:56:02 AM UTC 24
Finished Aug 25 06:56:12 AM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127712873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4127712873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1875910830
Short name T152
Test name
Test status
Simulation time 2126088672 ps
CPU time 103.49 seconds
Started Aug 25 06:55:59 AM UTC 24
Finished Aug 25 06:57:44 AM UTC 24
Peak memory 415584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875910830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1875910830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_error.3593579344
Short name T62
Test name
Test status
Simulation time 11765383617 ps
CPU time 43.4 seconds
Started Aug 25 06:56:02 AM UTC 24
Finished Aug 25 06:56:47 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593579344 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3593579344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_long_msg.4219341038
Short name T209
Test name
Test status
Simulation time 35627026872 ps
CPU time 223.57 seconds
Started Aug 25 06:55:51 AM UTC 24
Finished Aug 25 06:59:39 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219341038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4219341038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_smoke.1772498270
Short name T154
Test name
Test status
Simulation time 3113472401 ps
CPU time 9.6 seconds
Started Aug 25 06:55:50 AM UTC 24
Finished Aug 25 06:56:01 AM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772498270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1772498270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_stress_all.3871255321
Short name T35
Test name
Test status
Simulation time 12233003108 ps
CPU time 2271.25 seconds
Started Aug 25 06:56:06 AM UTC 24
Finished Aug 25 07:34:25 AM UTC 24
Peak memory 809156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871255321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3871255321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.4224577969
Short name T124
Test name
Test status
Simulation time 255547056 ps
CPU time 22.37 seconds
Started Aug 25 06:56:06 AM UTC 24
Finished Aug 25 06:56:30 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224577969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4224577969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_alert_test.3100965890
Short name T123
Test name
Test status
Simulation time 34713950 ps
CPU time 0.92 seconds
Started Aug 25 06:56:26 AM UTC 24
Finished Aug 25 06:56:28 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100965890 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3100965890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.4028387259
Short name T157
Test name
Test status
Simulation time 988729012 ps
CPU time 77.64 seconds
Started Aug 25 06:56:13 AM UTC 24
Finished Aug 25 06:57:33 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028387259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4028387259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.2563069037
Short name T121
Test name
Test status
Simulation time 371747993 ps
CPU time 7.02 seconds
Started Aug 25 06:56:18 AM UTC 24
Finished Aug 25 06:56:26 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563069037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2563069037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.4150075715
Short name T356
Test name
Test status
Simulation time 14681337901 ps
CPU time 1090.39 seconds
Started Aug 25 06:56:16 AM UTC 24
Finished Aug 25 07:14:40 AM UTC 24
Peak memory 727540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150075715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4150075715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_error.3817908334
Short name T203
Test name
Test status
Simulation time 21566701921 ps
CPU time 186.89 seconds
Started Aug 25 06:56:18 AM UTC 24
Finished Aug 25 06:59:29 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817908334 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3817908334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_long_msg.663884513
Short name T212
Test name
Test status
Simulation time 45645892292 ps
CPU time 216.05 seconds
Started Aug 25 06:56:13 AM UTC 24
Finished Aug 25 06:59:53 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663884513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.663884513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_stress_all.20491521
Short name T504
Test name
Test status
Simulation time 31334343201 ps
CPU time 2695.22 seconds
Started Aug 25 06:56:22 AM UTC 24
Finished Aug 25 07:41:54 AM UTC 24
Peak memory 792860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20491521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.20491521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3766003142
Short name T125
Test name
Test status
Simulation time 2347380494 ps
CPU time 9.52 seconds
Started Aug 25 06:56:20 AM UTC 24
Finished Aug 25 06:56:30 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766003142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3766003142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_alert_test.621374194
Short name T184
Test name
Test status
Simulation time 37646496 ps
CPU time 0.9 seconds
Started Aug 25 06:56:40 AM UTC 24
Finished Aug 25 06:56:42 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621374194 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.621374194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.3968182223
Short name T89
Test name
Test status
Simulation time 4448983501 ps
CPU time 116.65 seconds
Started Aug 25 06:56:29 AM UTC 24
Finished Aug 25 06:58:28 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968182223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3968182223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.932385637
Short name T153
Test name
Test status
Simulation time 1181811885 ps
CPU time 29.13 seconds
Started Aug 25 06:56:32 AM UTC 24
Finished Aug 25 06:57:02 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932385637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.932385637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.3100959912
Short name T47
Test name
Test status
Simulation time 1141077792 ps
CPU time 269.02 seconds
Started Aug 25 06:56:29 AM UTC 24
Finished Aug 25 07:01:02 AM UTC 24
Peak memory 682152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100959912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3100959912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_error.1876137729
Short name T218
Test name
Test status
Simulation time 18120718231 ps
CPU time 218.28 seconds
Started Aug 25 06:56:32 AM UTC 24
Finished Aug 25 07:00:14 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876137729 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1876137729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_long_msg.368465690
Short name T217
Test name
Test status
Simulation time 2989305075 ps
CPU time 219.62 seconds
Started Aug 25 06:56:27 AM UTC 24
Finished Aug 25 07:00:11 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368465690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.368465690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_smoke.1784641921
Short name T149
Test name
Test status
Simulation time 482394778 ps
CPU time 11.83 seconds
Started Aug 25 06:56:26 AM UTC 24
Finished Aug 25 06:56:39 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784641921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1784641921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/8.hmac_stress_all.2511566940
Short name T64
Test name
Test status
Simulation time 7080485885 ps
CPU time 124.61 seconds
Started Aug 25 06:56:33 AM UTC 24
Finished Aug 25 06:58:41 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511566940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2511566940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_alert_test.1888058028
Short name T189
Test name
Test status
Simulation time 10963338 ps
CPU time 0.82 seconds
Started Aug 25 06:57:13 AM UTC 24
Finished Aug 25 06:57:15 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888058028 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1888058028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.2582847945
Short name T175
Test name
Test status
Simulation time 1225898368 ps
CPU time 21.49 seconds
Started Aug 25 06:56:48 AM UTC 24
Finished Aug 25 06:57:11 AM UTC 24
Peak memory 207124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582847945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2582847945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1106503044
Short name T158
Test name
Test status
Simulation time 1617170719 ps
CPU time 39.95 seconds
Started Aug 25 06:57:03 AM UTC 24
Finished Aug 25 06:57:44 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106503044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1106503044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.2780551382
Short name T465
Test name
Test status
Simulation time 26646059755 ps
CPU time 1688.15 seconds
Started Aug 25 06:56:53 AM UTC 24
Finished Aug 25 07:25:23 AM UTC 24
Peak memory 772404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780551382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2780551382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_error.568978180
Short name T197
Test name
Test status
Simulation time 6997701101 ps
CPU time 114.16 seconds
Started Aug 25 06:57:09 AM UTC 24
Finished Aug 25 06:59:06 AM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568978180 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.568978180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_long_msg.4248467380
Short name T216
Test name
Test status
Simulation time 2835189219 ps
CPU time 203.38 seconds
Started Aug 25 06:56:44 AM UTC 24
Finished Aug 25 07:00:11 AM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248467380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.4248467380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_smoke.1725313728
Short name T150
Test name
Test status
Simulation time 1323943829 ps
CPU time 22.99 seconds
Started Aug 25 06:56:43 AM UTC 24
Finished Aug 25 06:57:07 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725313728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1725313728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_stress_all.468808336
Short name T91
Test name
Test status
Simulation time 4239467949 ps
CPU time 90.45 seconds
Started Aug 25 06:57:09 AM UTC 24
Finished Aug 25 06:58:42 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468808336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.468808336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.994354484
Short name T86
Test name
Test status
Simulation time 2568519648 ps
CPU time 65.25 seconds
Started Aug 25 06:57:09 AM UTC 24
Finished Aug 25 06:58:16 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994354484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.994354484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/9.hmac_wipe_secret/latest
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