Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18720456	1			T1	825		T12	474		T4	50
all_values[1]	18720456	1			T1	825		T12	474		T4	50
all_values[2]	18720456	1			T1	825		T12	474		T4	50

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314546

1

T12

474

T7

145

T11

392

auto[1]

55846822

1

T1

2475

T12

948

T4

150

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47813158

1

T1

2036

T12

950

T4

114

auto[1]

8348210

1

T1

439

T12

472

T4

36

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	119600	1			T12	474		T23	359		T13	1
all_values[0]	auto[0]	auto[1]	326	1			T23	2		T41	3		T122	2
all_values[0]	auto[1]	auto[0]	18581336	1			T1	821		T4	50		T5	238
all_values[0]	auto[1]	auto[1]	19194	1			T1	4		T5	1		T6	4
all_values[1]	auto[0]	auto[0]	119834	1			T22	2		T33	881		T13	1
all_values[1]	auto[0]	auto[1]	194	1			T72	3		T73	4		T76	6
all_values[1]	auto[1]	auto[0]	18600135	1			T1	824		T12	474		T4	50
all_values[1]	auto[1]	auto[1]	293	1			T1	1		T28	3		T72	5
all_values[2]	auto[0]	auto[0]	38079	1			T7	1		T11	2		T33	224
all_values[2]	auto[0]	auto[1]	36513	1			T7	144		T11	390		T33	657
all_values[2]	auto[1]	auto[0]	10354174	1			T1	391		T12	2		T4	14
all_values[2]	auto[1]	auto[1]	8291690	1			T1	434		T12	472		T4	36