Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

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Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130173

1

T1

4

T5

154

T7

2

auto[1]

127934

1

T1

426

T4

2

T5

50

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	96173	1			T1	22		T6	3		T7	2
len_1026_2046	6039	1			T1	1		T9	3		T25	7
len_514_1022	5131	1			T8	5		T9	2		T22	6
len_2_510	4971	1			T1	190		T5	2		T8	7
len_2056	257	1			T8	2		T22	1		T145	1
len_2048	337	1			T9	1		T26	1		T144	2
len_2040	144	1			T8	1		T9	2		T22	6
len_1032	230	1			T8	2		T9	3		T22	2
len_1024	1831	1			T1	1		T9	5		T22	2
len_1016	177	1			T8	3		T9	4		T22	6
len_520	168	1			T22	5		T146	1		T145	2
len_512	321	1			T1	1		T8	3		T9	1
len_504	213	1			T8	2		T9	2		T22	4
len_8	1268	1			T8	1		T9	1		T13	4
len_0	11795	1			T4	1		T5	100		T11	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

120

1

T1

2

T10

2

T26

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	50440	1			T7	1		T11	2		T8	2
auto[0]	len_1026_2046	2904	1			T9	2		T25	5		T141	1
auto[0]	len_514_1022	2739	1			T8	2		T9	1		T22	2
auto[0]	len_2_510	3126	1			T1	2		T5	2		T8	7
auto[0]	len_2056	112	1			T8	1		T22	1		T42	3
auto[0]	len_2048	171	1			T26	1		T28	2		T147	3
auto[0]	len_2040	84	1			T9	1		T42	2		T14	1
auto[0]	len_1032	122	1			T8	1		T9	3		T22	2
auto[0]	len_1024	276	1			T9	4		T141	1		T28	1
auto[0]	len_1016	92	1			T9	2		T22	6		T14	2
auto[0]	len_520	92	1			T22	5		T145	1		T42	2
auto[0]	len_512	211	1			T8	1		T9	1		T22	2
auto[0]	len_504	152	1			T8	2		T9	2		T22	2
auto[0]	len_8	99	1			T8	1		T9	1		T146	2
auto[0]	len_0	4468	1			T5	75		T11	1		T8	10
auto[1]	len_2050_plus	45733	1			T1	22		T6	3		T7	1
auto[1]	len_1026_2046	3135	1			T1	1		T9	1		T25	2
auto[1]	len_514_1022	2392	1			T8	3		T9	1		T22	4
auto[1]	len_2_510	1845	1			T1	188		T9	3		T28	13
auto[1]	len_2056	145	1			T8	1		T145	1		T42	1
auto[1]	len_2048	166	1			T9	1		T144	2		T28	2
auto[1]	len_2040	60	1			T8	1		T9	1		T22	6
auto[1]	len_1032	108	1			T8	1		T141	1		T42	2
auto[1]	len_1024	1555	1			T1	1		T9	1		T22	2
auto[1]	len_1016	85	1			T8	3		T9	2		T145	3
auto[1]	len_520	76	1			T146	1		T145	1		T148	2
auto[1]	len_512	110	1			T1	1		T8	2		T22	2
auto[1]	len_504	61	1			T22	2		T14	1		T149	1
auto[1]	len_8	1169	1			T13	4		T146	1		T123	1
auto[1]	len_0	7327	1			T4	1		T5	25		T8	5

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

63

1

T26

2

T141

1

T55

1

auto[1]

len_upper

57

1

T1

2

T10

2

T55

1