Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::save_and_restore_cg

Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	9	0	9	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size_cp	3	0	3	100.00	100	1	1	0
save_and_restore_cp	3	0	3	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sar_type_x_digest_size	9	0	9	100.00	100	1	1	0

Summary for Variable digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for digest_size_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	221	1			T1	1		T7	1		T25	1
sha2_384	195	1			T26	1		T141	1		T28	2
sha2_256	189	1			T8	1		T9	1		T10	1

---

Summary for Variable save_and_restore_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for save_and_restore_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	213	1			T7	1		T25	1		T10	1
different_context	193	1			T1	1		T8	1		T9	1
same_context	199	1			T26	2		T28	1		T24	3

---

Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	9	0	9	100.00

Automatically Generated Cross Bins for sar_type_x_digest_size

Bins

save_and_restore_cp	digest_size_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	sha2_512	79	1			T7	1		T25	1		T28	1
stop_and_continue	sha2_384	66	1			T28	1		T57	1		T150	1
stop_and_continue	sha2_256	68	1			T10	1		T145	1		T16	1
different_context	sha2_512	75	1			T1	1		T10	1		T26	1
different_context	sha2_384	65	1			T141	1		T55	1		T43	2
different_context	sha2_256	53	1			T8	1		T9	1		T55	1
same_context	sha2_512	67	1			T26	1		T16	1		T14	1
same_context	sha2_384	64	1			T26	1		T28	1		T24	1
same_context	sha2_256	68	1			T24	2		T55	1		T147	1