Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4693595 1 T1 91 T12 1 T4 26
auto[1] 2946139 1 T1 1022 T5 108 T6 793


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2956456 1 T1 1057 T12 1 T5 42
auto[1] 4683278 1 T1 56 T4 26 T5 350


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3226115 1 T1 8 T12 1 T5 291
auto[1] 4413619 1 T1 1105 T4 26 T5 101


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4767998 1 T1 394 T12 1 T5 291
auto[1] 2871736 1 T1 719 T4 26 T5 101


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6869012 1 T1 852 T12 1 T4 26
fifo_depth[1] 122975 1 T1 3 T6 10 T8 7
fifo_depth[2] 98000 1 T1 5 T6 3 T8 2
fifo_depth[3] 80185 1 T1 4 T6 2 T11 1
fifo_depth[4] 73838 1 T9 1 T25 71 T63 169
fifo_depth[5] 59344 1 T1 4 T9 1 T25 8
fifo_depth[6] 48661 1 T1 3 T25 22 T63 65
fifo_depth[7] 32344 1 T1 1 T7 1 T25 5


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 770722 1 T1 261 T6 15 T7 1
auto[1] 6869012 1 T1 852 T12 1 T4 26


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7625222 1 T1 1019 T12 1 T4 26
auto[1] 14512 1 T1 94 T28 955 T24 20


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 27616 1 T9 6 T26 1 T141 17
auto[0] auto[0] auto[0] auto[0] auto[1] 41575 1 T7 1 T22 1 T26 1
auto[0] auto[0] auto[0] auto[1] auto[0] 40064 1 T23 16 T121 13 T24 1297
auto[0] auto[0] auto[0] auto[1] auto[1] 32117 1 T25 58 T27 14 T145 2
auto[0] auto[0] auto[1] auto[0] auto[0] 134148 1 T25 81 T33 10 T23 8
auto[0] auto[0] auto[1] auto[0] auto[1] 28732 1 T9 1 T26 1 T33 42
auto[0] auto[0] auto[1] auto[1] auto[0] 37530 1 T6 2 T22 1 T26 1
auto[0] auto[0] auto[1] auto[1] auto[1] 38139 1 T33 27 T28 357 T61 125
auto[0] auto[1] auto[0] auto[0] auto[0] 49513 1 T11 1 T8 1 T22 2
auto[0] auto[1] auto[0] auto[0] auto[1] 44283 1 T1 7 T28 462 T24 859
auto[0] auto[1] auto[0] auto[1] auto[0] 45899 1 T1 248 T9 2 T25 9
auto[0] auto[1] auto[0] auto[1] auto[1] 46455 1 T1 6 T8 2 T9 3
auto[0] auto[1] auto[1] auto[0] auto[0] 57855 1 T8 2 T9 5 T63 976
auto[0] auto[1] auto[1] auto[0] auto[1] 45234 1 T6 5 T10 1 T28 344
auto[0] auto[1] auto[1] auto[1] auto[0] 54297 1 T6 8 T9 2 T22 5
auto[0] auto[1] auto[1] auto[1] auto[1] 47265 1 T8 4 T9 6 T33 8
auto[1] auto[0] auto[0] auto[0] auto[0] 174211 1 T12 1 T5 42 T8 112
auto[1] auto[0] auto[0] auto[0] auto[1] 166028 1 T7 1 T8 1 T9 52
auto[1] auto[0] auto[0] auto[1] auto[0] 154988 1 T8 49 T22 72 T141 31
auto[1] auto[0] auto[0] auto[1] auto[1] 165214 1 T6 301 T8 60 T9 66
auto[1] auto[0] auto[1] auto[0] auto[0] 1708905 1 T5 242 T11 1 T8 25
auto[1] auto[0] auto[1] auto[0] auto[1] 156080 1 T11 2 T8 68 T9 106
auto[1] auto[0] auto[1] auto[1] auto[0] 146182 1 T6 103 T7 2 T8 34
auto[1] auto[0] auto[1] auto[1] auto[1] 174586 1 T1 8 T5 7 T8 18
auto[1] auto[1] auto[0] auto[0] auto[0] 547706 1 T1 83 T11 1 T8 39
auto[1] auto[1] auto[0] auto[0] auto[1] 442619 1 T1 1 T8 57 T22 81
auto[1] auto[1] auto[0] auto[1] auto[0] 489670 1 T1 15 T8 63 T9 44
auto[1] auto[1] auto[0] auto[1] auto[1] 488498 1 T1 697 T7 1 T8 42
auto[1] auto[1] auto[1] auto[0] auto[0] 595699 1 T6 283 T7 1 T11 1
auto[1] auto[1] auto[1] auto[0] auto[1] 473391 1 T4 26 T6 175 T8 39
auto[1] auto[1] auto[1] auto[1] auto[0] 503715 1 T1 48 T5 7 T6 379
auto[1] auto[1] auto[1] auto[1] auto[1] 481520 1 T5 94 T8 101 T9 42


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 200765 1 T12 1 T5 42 T8 112
auto[0] auto[0] auto[0] auto[0] auto[1] 206116 1 T7 2 T8 1 T9 52
auto[0] auto[0] auto[0] auto[1] auto[0] 193722 1 T8 49 T22 72 T141 31
auto[0] auto[0] auto[0] auto[1] auto[1] 195782 1 T6 301 T8 60 T9 66
auto[0] auto[0] auto[1] auto[0] auto[0] 1842006 1 T5 242 T11 1 T8 25
auto[0] auto[0] auto[1] auto[0] auto[1] 183216 1 T11 2 T8 68 T9 107
auto[0] auto[0] auto[1] auto[1] auto[0] 182821 1 T6 105 T7 2 T8 34
auto[0] auto[0] auto[1] auto[1] auto[1] 211608 1 T1 8 T5 7 T8 18
auto[0] auto[1] auto[0] auto[0] auto[0] 596829 1 T1 83 T11 2 T8 40
auto[0] auto[1] auto[0] auto[0] auto[1] 486640 1 T1 8 T8 57 T22 81
auto[0] auto[1] auto[0] auto[1] auto[0] 534067 1 T1 169 T8 63 T9 46
auto[0] auto[1] auto[0] auto[1] auto[1] 534374 1 T1 703 T7 1 T8 44
auto[0] auto[1] auto[1] auto[0] auto[0] 653304 1 T6 283 T7 1 T11 1
auto[0] auto[1] auto[1] auto[0] auto[1] 518440 1 T4 26 T6 180 T8 39
auto[0] auto[1] auto[1] auto[1] auto[0] 557312 1 T1 48 T5 7 T6 387
auto[0] auto[1] auto[1] auto[1] auto[1] 528220 1 T5 94 T8 105 T9 48
auto[1] auto[0] auto[0] auto[0] auto[0] 1062 1 T28 8 T88 34 T90 3
auto[1] auto[0] auto[0] auto[0] auto[1] 1487 1 T28 36 T73 74 T130 9
auto[1] auto[0] auto[0] auto[1] auto[0] 1330 1 T24 2 T73 1 T151 21
auto[1] auto[0] auto[0] auto[1] auto[1] 1549 1 T151 7 T91 26 T152 25
auto[1] auto[0] auto[1] auto[0] auto[0] 1047 1 T28 232 T57 502 T91 69
auto[1] auto[0] auto[1] auto[0] auto[1] 1596 1 T28 176 T24 5 T29 1
auto[1] auto[0] auto[1] auto[1] auto[0] 891 1 T57 7 T73 6 T88 1
auto[1] auto[0] auto[1] auto[1] auto[1] 1117 1 T28 4 T153 34 T73 39
auto[1] auto[1] auto[0] auto[0] auto[0] 390 1 T73 6 T130 5 T151 2
auto[1] auto[1] auto[0] auto[0] auto[1] 262 1 T28 1 T24 13 T91 100
auto[1] auto[1] auto[0] auto[1] auto[0] 1502 1 T1 94 T28 6 T153 22
auto[1] auto[1] auto[0] auto[1] auto[1] 579 1 T28 492 T91 6 T154 15
auto[1] auto[1] auto[1] auto[0] auto[0] 250 1 T57 25 T88 13 T155 18
auto[1] auto[1] auto[1] auto[0] auto[1] 185 1 T156 65 T157 1 T18 14
auto[1] auto[1] auto[1] auto[1] auto[0] 700 1 T158 33 T73 20 T130 86
auto[1] auto[1] auto[1] auto[1] auto[1] 565 1 T158 2 T91 23 T154 8


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 174211 1 T12 1 T5 42 T8 112
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 166028 1 T7 1 T8 1 T9 52
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 154988 1 T8 49 T22 72 T141 31
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 165214 1 T6 301 T8 60 T9 66
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1708905 1 T5 242 T11 1 T8 25
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 156080 1 T11 2 T8 68 T9 106
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 146182 1 T6 103 T7 2 T8 34
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 174586 1 T1 8 T5 7 T8 18
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 547706 1 T1 83 T11 1 T8 39
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 442619 1 T1 1 T8 57 T22 81
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 489670 1 T1 15 T8 63 T9 44
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 488498 1 T1 697 T7 1 T8 42
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 595699 1 T6 283 T7 1 T11 1
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 473391 1 T4 26 T6 175 T8 39
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 503715 1 T1 48 T5 7 T6 379
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 481520 1 T5 94 T8 101 T9 42
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3491 1 T9 6 T141 2 T121 8
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3461 1 T22 1 T23 22 T28 3
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3783 1 T23 12 T121 9 T24 6
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3378 1 T25 11 T27 12 T145 2
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 39263 1 T25 1 T33 6 T23 7
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3236 1 T9 1 T33 30 T23 8
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3036 1 T6 1 T24 8 T27 14
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3702 1 T33 21 T61 52 T55 70
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 7415 1 T8 1 T22 1 T144 7
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6539 1 T1 1 T24 35 T13 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6463 1 T1 2 T9 1 T25 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 7403 1 T8 1 T9 1 T22 3
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 9856 1 T8 1 T9 2 T63 205
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6920 1 T6 2 T28 11 T27 5
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7826 1 T6 7 T22 3 T144 4
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 7203 1 T8 4 T9 4 T33 4
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2962 1 T141 2 T28 1 T121 3
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2924 1 T23 8 T28 3 T146 1
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3053 1 T23 4 T121 4 T24 6
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2910 1 T25 12 T27 2 T159 3
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 26251 1 T25 3 T33 3 T23 1
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2646 1 T33 10 T23 1 T24 6
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2617 1 T6 1 T22 1 T24 41
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3073 1 T33 4 T61 39 T55 14
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6232 1 T22 1 T144 5 T28 47
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5640 1 T1 1 T28 6 T24 33
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5669 1 T1 1 T9 1 T25 2
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 6276 1 T1 3 T8 1 T9 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 8313 1 T8 1 T9 1 T63 183
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 6249 1 T6 2 T28 39 T27 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6969 1 T9 1 T22 1 T144 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 6216 1 T9 1 T33 3 T23 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2223 1 T141 2 T28 1 T121 2
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2168 1 T28 15 T40 2 T14 2
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2488 1 T24 4 T40 18 T14 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2113 1 T25 8 T159 1 T15 2
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 19266 1 T25 4 T33 1 T40 36
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2025 1 T33 2 T24 6 T147 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2166 1 T24 42 T40 23 T14 14
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2320 1 T33 2 T61 27 T55 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5452 1 T11 1 T144 5 T28 43
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4979 1 T1 2 T28 2 T24 30
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4805 1 T1 1 T28 2 T40 10
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5627 1 T1 1 T55 1 T147 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 7486 1 T63 199 T28 2 T58 110
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5736 1 T6 1 T28 16 T40 49
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5979 1 T6 1 T9 1 T22 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 5352 1 T9 1 T33 1 T23 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2246 1 T141 4 T28 2 T61 24
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2368 1 T28 7 T40 4 T14 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2370 1 T24 4 T40 16 T14 2
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2223 1 T25 8 T160 4 T123 22
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 14110 1 T25 51 T40 27 T41 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2086 1 T24 9 T147 5 T40 11
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2340 1 T24 41 T40 17 T14 10
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2499 1 T28 2 T61 6 T147 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 5128 1 T144 8 T28 38 T59 3
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4728 1 T28 6 T24 34 T147 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4722 1 T26 1 T28 4 T55 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 5453 1 T25 12 T24 2 T122 33
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 7072 1 T9 1 T63 169 T28 2
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 5550 1 T28 41 T40 48 T122 50
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5829 1 T144 6 T14 2 T122 10
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5114 1 T147 2 T16 1 T40 10
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1476 1 T26 1 T141 3 T28 16
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1808 1 T28 15 T40 3 T14 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1825 1 T24 6 T40 14 T14 4
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1586 1 T25 7 T123 16 T57 2
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 10151 1 T25 1 T40 18 T14 12
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1477 1 T24 6 T147 2 T40 16
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1747 1 T24 42 T40 19 T14 11
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1825 1 T61 1 T14 23 T122 18
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4501 1 T144 6 T28 45 T40 16
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4064 1 T1 1 T24 35 T14 3
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3956 1 T1 2 T28 11 T40 4
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4683 1 T1 1 T24 5 T14 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 5920 1 T9 1 T63 125 T28 2
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4882 1 T28 11 T40 41 T122 52
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4856 1 T144 4 T14 1 T122 8
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4587 1 T40 8 T41 1 T149 4
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1167 1 T141 2 T28 3 T40 16
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1844 1 T26 1 T28 3 T40 5
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1534 1 T24 6 T40 7 T14 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1517 1 T25 7 T123 12 T57 2
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7460 1 T25 1 T40 15 T14 9
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1258 1 T24 6 T147 3 T40 8
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1701 1 T24 52 T40 12 T14 12
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1488 1 T147 1 T14 17 T122 11
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3725 1 T144 7 T28 21 T40 2
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3282 1 T1 2 T28 4 T24 24
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3354 1 T25 2 T28 19 T40 5
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3911 1 T1 1 T25 12 T24 4
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 4643 1 T63 65 T28 2 T58 2
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 4070 1 T28 42 T40 32 T122 39
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 4066 1 T144 1 T14 2 T122 6
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3641 1 T147 1 T40 10 T14 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 786 1 T141 1 T28 19 T40 8
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1319 1 T7 1 T28 15 T40 3
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1011 1 T24 6 T40 3 T122 7
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1010 1 T25 1 T160 1 T123 6
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4404 1 T25 2 T40 11 T14 5
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 794 1 T24 6 T40 7 T14 5
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1199 1 T24 51 T40 6 T14 5
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1168 1 T14 7 T122 4 T123 4
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2575 1 T144 2 T28 2 T40 4
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2322 1 T28 1 T24 7 T14 2
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2302 1 T1 1 T28 22 T40 1
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2492 1 T25 2 T24 4 T14 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 3084 1 T63 20 T28 2 T60 5
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2706 1 T28 11 T40 21 T122 19
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2679 1 T14 3 T122 3 T158 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2493 1 T147 1 T40 4 T149 1

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