Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18720456	1			T1	825		T12	474		T4	50
all_pins[1]	18720456	1			T1	825		T12	474		T4	50
all_pins[2]	18720456	1			T1	825		T12	474		T4	50

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47849277	1			T1	2034		T12	950		T4	114
values[0x1]	8312091	1			T1	441		T12	472		T4	36
transitions[0x0=>0x1]	8311951	1			T1	441		T12	472		T4	36
transitions[0x1=>0x0]	8311968	1			T1	441		T12	472		T4	36

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18700376	1			T1	819		T12	474		T4	50
all_pins[0]	values[0x1]	20080	1			T1	6		T5	1		T6	4
all_pins[0]	transitions[0x0=>0x1]	20015	1			T1	6		T5	1		T6	4
all_pins[0]	transitions[0x1=>0x0]	8291642	1			T1	434		T12	472		T4	36
all_pins[1]	values[0x0]	18720135	1			T1	824		T12	474		T4	50
all_pins[1]	values[0x1]	321	1			T1	1		T28	4		T16	1
all_pins[1]	transitions[0x0=>0x1]	288	1			T1	1		T28	4		T16	1
all_pins[1]	transitions[0x1=>0x0]	20047	1			T1	6		T5	1		T6	4
all_pins[2]	values[0x0]	10428766	1			T1	391		T12	2		T4	14
all_pins[2]	values[0x1]	8291690	1			T1	434		T12	472		T4	36
all_pins[2]	transitions[0x0=>0x1]	8291648	1			T1	434		T12	472		T4	36
all_pins[2]	transitions[0x1=>0x0]	279	1			T1	1		T28	4		T16	1