Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 786 1 T72 10 T73 10 T74 10
all_values[1] 786 1 T72 10 T73 10 T74 10
all_values[2] 786 1 T72 10 T73 10 T74 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1226 1 T72 15 T73 14 T74 11
auto[1] 1132 1 T72 15 T73 16 T74 19


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 847 1 T72 8 T73 18 T74 11
auto[1] 1511 1 T72 22 T73 12 T74 19


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1345 1 T72 12 T73 23 T74 17
auto[1] 1013 1 T72 18 T73 7 T74 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 166 1 T72 2 T73 2 T76 1
all_values[0] auto[0] auto[0] auto[1] 82 1 T72 1 T74 1 T76 3
all_values[0] auto[0] auto[1] auto[0] 139 1 T72 1 T73 6 T74 3
all_values[0] auto[0] auto[1] auto[1] 77 1 T72 1 T73 1 T74 2
all_values[0] auto[1] auto[0] auto[1] 141 1 T73 1 T76 4 T129 1
all_values[0] auto[1] auto[1] auto[1] 181 1 T72 5 T74 4 T76 8
all_values[1] auto[0] auto[0] auto[0] 116 1 T73 1 T74 4 T130 1
all_values[1] auto[0] auto[0] auto[1] 88 1 T72 1 T73 2 T74 1
all_values[1] auto[0] auto[1] auto[0] 122 1 T74 3 T76 3 T130 1
all_values[1] auto[0] auto[1] auto[1] 96 1 T72 1 T73 2 T76 2
all_values[1] auto[1] auto[0] auto[1] 202 1 T72 3 T73 3 T76 6
all_values[1] auto[1] auto[1] auto[1] 162 1 T72 5 T73 2 T74 2
all_values[2] auto[0] auto[0] auto[0] 160 1 T72 3 T73 5 T76 2
all_values[2] auto[0] auto[0] auto[1] 80 1 T74 1 T76 2 T131 3
all_values[2] auto[0] auto[1] auto[0] 144 1 T72 2 T73 4 T74 1
all_values[2] auto[0] auto[1] auto[1] 75 1 T74 1 T76 4 T130 1
all_values[2] auto[1] auto[0] auto[1] 191 1 T72 5 T74 4 T76 6
all_values[2] auto[1] auto[1] auto[1] 136 1 T73 1 T74 3 T76 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%