Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4175	1			T5	4		T7	1		T8	12
sha2_none	4028	1			T6	2		T7	3		T11	3
sha2_512	7615	1			T1	3		T6	2		T7	2
sha2_384	7159	1			T1	2		T5	2		T6	1
sha2_256	6189	1			T1	2		T4	1		T5	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18460

1

T1

2

T4

1

T5

4

auto[1]

11081

1

T1

6

T5

3

T6

3

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11034

1

T1

6

T5

2

T6

1

auto[1]

18507

1

T1

2

T4

1

T5

5

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15515

1

T1

7

T4

1

T5

3

disabled

14026

1

T1

1

T5

4

T6

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4656	1			T1	2		T5	2		T7	1
key_none	7668	1			T1	1		T4	1		T5	1
key_1024	4245	1			T5	1		T6	1		T7	1
key_512	3697	1			T1	1		T5	1		T7	2
key_384	3354	1			T1	1		T6	2		T8	6
key_256	2977	1			T1	3		T5	2		T7	1
key_128	2872	1			T6	1		T11	1		T8	8

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18671

1

T1

4

T5

4

T6

3

auto[1]

10870

1

T1

4

T4

1

T5

3

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29318

1

T1

8

T4

1

T5

7

disabled

223

1

T59

3

T61

1

T62

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1621

1

T1

1

T11

2

T8

3

enabled

auto[0]

auto[0]

auto[1]

1518

1

T1

1

T5

1

T8

3

enabled

auto[0]

auto[1]

auto[0]

1635

1

T1

2

T8

3

T9

1

enabled

auto[0]

auto[1]

auto[1]

1566

1

T1

2

T7

1

T8

1

enabled

auto[1]

auto[0]

auto[0]

4318

1

T6

1

T7

1

T11

1

enabled

auto[1]

auto[0]

auto[1]

1550

1

T4

1

T6

1

T8

2

enabled

auto[1]

auto[1]

auto[0]

1751

1

T1

1

T5

1

T6

1

enabled

auto[1]

auto[1]

auto[1]

1556

1

T5

1

T8

5

T9

3

disabled

auto[0]

auto[0]

auto[0]

1147

1

T5

1

T8

7

T9

4

disabled

auto[0]

auto[0]

auto[1]

1213

1

T7

2

T8

1

T9

2

disabled

auto[0]

auto[1]

auto[0]

1150

1

T8

5

T22

5

T141

2

disabled

auto[0]

auto[1]

auto[1]

1184

1

T6

1

T8

4

T9

5

disabled

auto[1]

auto[0]

auto[0]

5947

1

T5

2

T11

1

T8

2

disabled

auto[1]

auto[0]

auto[1]

1146

1

T11

2

T8

2

T9

7

disabled

auto[1]

auto[1]

auto[0]

1102

1

T6

1

T7

2

T8

3

disabled

auto[1]

auto[1]

auto[1]

1137

1

T1

1

T5

1

T8

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15425

1

T1

7

T4

1

T5

3

enabled

disabled

90

1

T59

2

T142

1

T143

3

disabled

disabled

133

1

T59

1

T61

1

T62

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13893

1

T1

1

T5

4

T6

2

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1206	1			T5	1		T8	1		T9	1
key_invalid	sha2_none	819	1			T7	1		T22	1		T25	2
key_invalid	sha2_512	903	1			T8	1		T22	2		T25	1
key_invalid	sha2_384	835	1			T1	1		T5	1		T8	2
key_invalid	sha2_256	789	1			T1	1		T22	4		T10	1
key_none	sha2_invalid	495	1			T22	2		T10	1		T141	1
key_none	sha2_none	519	1			T6	1		T11	1		T22	1
key_none	sha2_512	2560	1			T7	1		T11	1		T8	2
key_none	sha2_384	2505	1			T1	1		T5	1		T8	2
key_none	sha2_256	1549	1			T4	1		T9	1		T25	1
key_1024	sha2_invalid	462	1			T8	4		T9	1		T27	1
key_1024	sha2_none	556	1			T8	3		T9	2		T22	4
key_1024	sha2_512	1681	1			T6	1		T7	1		T8	1
key_1024	sha2_384	881	1			T8	2		T26	2		T141	1
key_512	sha2_invalid	529	1			T5	1		T7	1		T8	3
key_512	sha2_none	551	1			T7	1		T11	2		T8	2
key_512	sha2_512	567	1			T9	1		T22	2		T10	1
key_512	sha2_384	1166	1			T8	1		T22	1		T10	1
key_512	sha2_256	827	1			T1	1		T8	2		T9	1
key_384	sha2_invalid	495	1			T9	1		T25	1		T10	1
key_384	sha2_none	542	1			T6	1		T8	1		T22	1
key_384	sha2_512	626	1			T6	1		T9	3		T22	1
key_384	sha2_384	569	1			T8	2		T9	2		T22	3
key_384	sha2_256	1082	1			T8	3		T9	4		T25	1
key_256	sha2_invalid	455	1			T5	2		T8	2		T22	1
key_256	sha2_none	493	1			T7	1		T8	1		T22	2
key_256	sha2_512	652	1			T1	3		T8	1		T9	1
key_256	sha2_384	580	1			T8	4		T9	3		T22	1
key_256	sha2_256	756	1			T8	2		T33	1		T144	1
key_128	sha2_invalid	515	1			T8	2		T22	4		T25	1
key_128	sha2_none	538	1			T8	1		T9	3		T10	1
key_128	sha2_512	606	1			T8	2		T9	1		T22	1
key_128	sha2_384	612	1			T6	1		T11	1		T8	1
key_128	sha2_256	553	1			T8	1		T9	3		T22	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

622

1

T5

1

T11

1

T8

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1206	1			T5	1		T8	1		T9	1
key_invalid	sha2_none	819	1			T7	1		T22	1		T25	2
key_invalid	sha2_512	903	1			T8	1		T22	2		T25	1
key_invalid	sha2_384	835	1			T1	1		T5	1		T8	2
key_invalid	sha2_256	789	1			T1	1		T22	4		T10	1
key_none	sha2_invalid	495	1			T22	2		T10	1		T141	1
key_none	sha2_none	519	1			T6	1		T11	1		T22	1
key_none	sha2_512	2560	1			T7	1		T11	1		T8	2
key_none	sha2_384	2505	1			T1	1		T5	1		T8	2
key_none	sha2_256	1549	1			T4	1		T9	1		T25	1
key_1024	sha2_invalid	462	1			T8	4		T9	1		T27	1
key_1024	sha2_none	556	1			T8	3		T9	2		T22	4
key_1024	sha2_512	1681	1			T6	1		T7	1		T8	1
key_1024	sha2_384	881	1			T8	2		T26	2		T141	1
key_1024	sha2_256	622	1			T5	1		T11	1		T8	1
key_512	sha2_invalid	529	1			T5	1		T7	1		T8	3
key_512	sha2_none	551	1			T7	1		T11	2		T8	2
key_512	sha2_512	567	1			T9	1		T22	2		T10	1
key_512	sha2_384	1166	1			T8	1		T22	1		T10	1
key_512	sha2_256	827	1			T1	1		T8	2		T9	1
key_384	sha2_invalid	495	1			T9	1		T25	1		T10	1
key_384	sha2_none	542	1			T6	1		T8	1		T22	1
key_384	sha2_512	626	1			T6	1		T9	3		T22	1
key_384	sha2_384	569	1			T8	2		T9	2		T22	3
key_384	sha2_256	1082	1			T8	3		T9	4		T25	1
key_256	sha2_invalid	455	1			T5	2		T8	2		T22	1
key_256	sha2_none	493	1			T7	1		T8	1		T22	2
key_256	sha2_512	652	1			T1	3		T8	1		T9	1
key_256	sha2_384	580	1			T8	4		T9	3		T22	1
key_256	sha2_256	756	1			T8	2		T33	1		T144	1
key_128	sha2_invalid	515	1			T8	2		T22	4		T25	1
key_128	sha2_none	538	1			T8	1		T9	3		T10	1
key_128	sha2_512	606	1			T8	2		T9	1		T22	1
key_128	sha2_384	612	1			T6	1		T11	1		T8	1
key_128	sha2_256	553	1			T8	1		T9	3		T22	2