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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 657
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T103 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.756074783 Aug 27 02:16:44 PM UTC 24 Aug 27 02:17:01 PM UTC 24 1332403590 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2118584893 Aug 27 02:17:00 PM UTC 24 Aug 27 02:17:02 PM UTC 24 41212002 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3455985718 Aug 27 02:16:57 PM UTC 24 Aug 27 02:17:03 PM UTC 24 2315123505 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.1611771183 Aug 27 02:17:01 PM UTC 24 Aug 27 02:17:03 PM UTC 24 208763860 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.2879325312 Aug 27 02:16:58 PM UTC 24 Aug 27 02:17:04 PM UTC 24 186266059 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.4138138234 Aug 27 02:17:02 PM UTC 24 Aug 27 02:17:05 PM UTC 24 41979644 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1166933799 Aug 27 02:17:05 PM UTC 24 Aug 27 02:17:07 PM UTC 24 22196307 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.214307710 Aug 27 02:17:06 PM UTC 24 Aug 27 02:17:08 PM UTC 24 258745495 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2339118230 Aug 27 02:17:04 PM UTC 24 Aug 27 02:17:11 PM UTC 24 1430213736 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1579638131 Aug 27 02:17:08 PM UTC 24 Aug 27 02:17:11 PM UTC 24 74065469 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3330538701 Aug 27 02:17:13 PM UTC 24 Aug 27 02:17:15 PM UTC 24 48375443 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.743182376 Aug 27 02:17:05 PM UTC 24 Aug 27 02:17:15 PM UTC 24 2224915641 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3266430099 Aug 27 02:17:13 PM UTC 24 Aug 27 02:17:16 PM UTC 24 69603571 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2383460515 Aug 27 02:17:14 PM UTC 24 Aug 27 02:17:16 PM UTC 24 134618619 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.976533766 Aug 27 02:17:13 PM UTC 24 Aug 27 02:17:17 PM UTC 24 88941241 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1596473541 Aug 27 02:17:17 PM UTC 24 Aug 27 02:17:19 PM UTC 24 42198301 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.178207592 Aug 27 02:17:17 PM UTC 24 Aug 27 02:17:19 PM UTC 24 34582776 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.4092298434 Aug 27 02:17:18 PM UTC 24 Aug 27 02:17:20 PM UTC 24 27802860 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.1007071388 Aug 27 02:17:17 PM UTC 24 Aug 27 02:17:20 PM UTC 24 28180017 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.4042855701 Aug 27 02:17:17 PM UTC 24 Aug 27 02:17:21 PM UTC 24 101093025 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.215629903 Aug 27 02:17:20 PM UTC 24 Aug 27 02:17:22 PM UTC 24 24129411 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2711790994 Aug 27 02:17:20 PM UTC 24 Aug 27 02:17:22 PM UTC 24 64519712 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4053118068 Aug 27 02:17:22 PM UTC 24 Aug 27 02:17:25 PM UTC 24 22605743 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1673740811 Aug 27 02:17:21 PM UTC 24 Aug 27 02:17:26 PM UTC 24 611430026 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2366117998 Aug 27 02:17:14 PM UTC 24 Aug 27 02:17:26 PM UTC 24 1866869508 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1285143016 Aug 27 02:17:22 PM UTC 24 Aug 27 02:17:27 PM UTC 24 147346130 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.342955345 Aug 27 02:17:15 PM UTC 24 Aug 27 02:17:27 PM UTC 24 1773993305 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.2718463056 Aug 27 02:17:26 PM UTC 24 Aug 27 02:17:28 PM UTC 24 26260371 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.3169847430 Aug 27 02:17:26 PM UTC 24 Aug 27 02:17:29 PM UTC 24 84309491 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3797523743 Aug 27 02:17:21 PM UTC 24 Aug 27 02:17:29 PM UTC 24 517695723 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.207393137 Aug 27 02:17:27 PM UTC 24 Aug 27 02:17:29 PM UTC 24 49435796 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1311077005 Aug 27 02:17:25 PM UTC 24 Aug 27 02:17:30 PM UTC 24 172752360 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.698288978 Aug 27 02:17:23 PM UTC 24 Aug 27 02:17:30 PM UTC 24 1178515222 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.2780688791 Aug 27 02:17:31 PM UTC 24 Aug 27 02:17:33 PM UTC 24 24395769 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.999270064 Aug 27 02:17:31 PM UTC 24 Aug 27 02:17:33 PM UTC 24 59958260 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1882766559 Aug 27 02:17:30 PM UTC 24 Aug 27 02:17:35 PM UTC 24 595701045 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.116671357 Aug 27 02:17:31 PM UTC 24 Aug 27 02:17:36 PM UTC 24 133166856 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.1313395226 Aug 27 02:17:31 PM UTC 24 Aug 27 02:17:38 PM UTC 24 1038528637 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.308432777 Aug 27 02:17:34 PM UTC 24 Aug 27 02:17:39 PM UTC 24 285165725 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3455800690 Aug 27 02:17:34 PM UTC 24 Aug 27 02:17:40 PM UTC 24 269546495 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.3072361947 Aug 27 02:17:38 PM UTC 24 Aug 27 02:17:40 PM UTC 24 41507786 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.91504009 Aug 27 02:17:36 PM UTC 24 Aug 27 02:17:41 PM UTC 24 150487955 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.4139683067 Aug 27 02:17:39 PM UTC 24 Aug 27 02:17:41 PM UTC 24 17964992 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1967365557 Aug 27 02:17:29 PM UTC 24 Aug 27 02:17:42 PM UTC 24 1631163125 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1611864168 Aug 27 02:17:37 PM UTC 24 Aug 27 02:17:42 PM UTC 24 163108875 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1720039739 Aug 27 02:17:29 PM UTC 24 Aug 27 02:17:42 PM UTC 24 1492352663 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3403944692 Aug 27 02:17:40 PM UTC 24 Aug 27 02:17:44 PM UTC 24 178234388 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1727949848 Aug 27 02:17:42 PM UTC 24 Aug 27 02:17:44 PM UTC 24 12854096 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.654489011 Aug 27 02:17:40 PM UTC 24 Aug 27 02:17:44 PM UTC 24 74012734 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.333628647 Aug 27 02:17:44 PM UTC 24 Aug 27 02:17:46 PM UTC 24 53139295 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.3932493173 Aug 27 02:17:41 PM UTC 24 Aug 27 02:17:46 PM UTC 24 256831963 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1508120020 Aug 27 02:17:44 PM UTC 24 Aug 27 02:17:46 PM UTC 24 221728631 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2836273601 Aug 27 02:17:42 PM UTC 24 Aug 27 02:17:48 PM UTC 24 508018158 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.1840713759 Aug 27 02:17:45 PM UTC 24 Aug 27 02:17:48 PM UTC 24 142641614 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.151082242 Aug 27 02:17:47 PM UTC 24 Aug 27 02:17:49 PM UTC 24 37248465 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1247786653 Aug 27 02:17:47 PM UTC 24 Aug 27 02:17:49 PM UTC 24 45864067 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3932133229 Aug 27 02:17:47 PM UTC 24 Aug 27 02:17:50 PM UTC 24 25464739 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.981526760 Aug 27 02:17:46 PM UTC 24 Aug 27 02:17:50 PM UTC 24 126846913 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.3571882082 Aug 27 02:17:50 PM UTC 24 Aug 27 02:17:52 PM UTC 24 35007398 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.3093265393 Aug 27 02:17:50 PM UTC 24 Aug 27 02:17:53 PM UTC 24 53155544 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3830159445 Aug 27 02:17:48 PM UTC 24 Aug 27 02:17:54 PM UTC 24 181238852 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.41242676 Aug 27 02:17:51 PM UTC 24 Aug 27 02:17:54 PM UTC 24 61801656 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3767149841 Aug 27 02:17:51 PM UTC 24 Aug 27 02:17:55 PM UTC 24 71388911 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2318139303 Aug 27 02:17:50 PM UTC 24 Aug 27 02:17:56 PM UTC 24 587893576 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2961927155 Aug 27 02:17:53 PM UTC 24 Aug 27 02:17:56 PM UTC 24 72934858 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2418220883 Aug 27 02:17:50 PM UTC 24 Aug 27 02:17:56 PM UTC 24 635779032 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2550117095 Aug 27 02:17:55 PM UTC 24 Aug 27 02:17:57 PM UTC 24 14804908 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.2377224276 Aug 27 02:17:54 PM UTC 24 Aug 27 02:18:02 PM UTC 24 638774661 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1568694621 Aug 27 02:18:06 PM UTC 24 Aug 27 02:18:08 PM UTC 24 173423491 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2771783901 Aug 27 02:18:06 PM UTC 24 Aug 27 02:18:09 PM UTC 24 36100238 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3654033102 Aug 27 02:18:07 PM UTC 24 Aug 27 02:18:09 PM UTC 24 68524362 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.516399778 Aug 27 02:18:07 PM UTC 24 Aug 27 02:18:10 PM UTC 24 108219119 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2845295344 Aug 27 02:18:06 PM UTC 24 Aug 27 02:18:10 PM UTC 24 61843366 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2928639949 Aug 27 02:18:07 PM UTC 24 Aug 27 02:18:10 PM UTC 24 93972234 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.2908031989 Aug 27 02:18:11 PM UTC 24 Aug 27 02:18:13 PM UTC 24 80348541 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.2965774742 Aug 27 02:18:07 PM UTC 24 Aug 27 02:18:11 PM UTC 24 108136490 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1756551313 Aug 27 02:18:07 PM UTC 24 Aug 27 02:18:12 PM UTC 24 169299678 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1867428360 Aug 27 02:18:11 PM UTC 24 Aug 27 02:18:13 PM UTC 24 15755148 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2008812496 Aug 27 02:18:08 PM UTC 24 Aug 27 02:18:13 PM UTC 24 189914846 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.105492526 Aug 27 02:18:11 PM UTC 24 Aug 27 02:18:14 PM UTC 24 185597182 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.1192542184 Aug 27 02:18:09 PM UTC 24 Aug 27 02:18:15 PM UTC 24 227456404 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3720147783 Aug 27 02:18:12 PM UTC 24 Aug 27 02:18:15 PM UTC 24 60679985 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1345812920 Aug 27 02:18:14 PM UTC 24 Aug 27 02:18:16 PM UTC 24 32708750 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2586643439 Aug 27 02:18:14 PM UTC 24 Aug 27 02:18:17 PM UTC 24 119718953 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1899624175 Aug 27 02:18:13 PM UTC 24 Aug 27 02:18:17 PM UTC 24 350293096 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1951077536 Aug 27 02:18:11 PM UTC 24 Aug 27 02:18:18 PM UTC 24 893308102 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3754366889 Aug 27 02:18:15 PM UTC 24 Aug 27 02:18:18 PM UTC 24 36462255 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.547350503 Aug 27 02:18:17 PM UTC 24 Aug 27 02:18:19 PM UTC 24 20535560 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.3139339670 Aug 27 02:18:17 PM UTC 24 Aug 27 02:18:19 PM UTC 24 13428150 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1909643701 Aug 27 02:18:13 PM UTC 24 Aug 27 02:18:19 PM UTC 24 652665727 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.459347180 Aug 27 02:18:16 PM UTC 24 Aug 27 02:18:20 PM UTC 24 149933665 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2368592077 Aug 27 02:18:16 PM UTC 24 Aug 27 02:18:21 PM UTC 24 36702536 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2399741436 Aug 27 02:18:18 PM UTC 24 Aug 27 02:18:21 PM UTC 24 38475997 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.997167399 Aug 27 02:18:21 PM UTC 24 Aug 27 02:18:23 PM UTC 24 48983118 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1988064035 Aug 27 02:18:20 PM UTC 24 Aug 27 02:18:23 PM UTC 24 22672922 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.1790464944 Aug 27 02:18:21 PM UTC 24 Aug 27 02:18:23 PM UTC 24 19628472 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.973504137 Aug 27 02:18:17 PM UTC 24 Aug 27 02:18:24 PM UTC 24 124972433 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.610020602 Aug 27 02:18:21 PM UTC 24 Aug 27 02:18:25 PM UTC 24 52606097 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2352981681 Aug 27 02:18:20 PM UTC 24 Aug 27 02:18:26 PM UTC 24 715541826 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1601450659 Aug 27 02:18:22 PM UTC 24 Aug 27 02:18:26 PM UTC 24 113953604 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1995732435 Aug 27 02:18:22 PM UTC 24 Aug 27 02:18:26 PM UTC 24 254342235 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.128528257 Aug 27 02:18:25 PM UTC 24 Aug 27 02:18:27 PM UTC 24 52747051 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.22633951 Aug 27 02:18:25 PM UTC 24 Aug 27 02:18:27 PM UTC 24 120416642 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3149356574 Aug 27 02:18:27 PM UTC 24 Aug 27 02:18:29 PM UTC 24 27623861 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3985914783 Aug 27 02:18:27 PM UTC 24 Aug 27 02:18:29 PM UTC 24 30441516 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1762513031 Aug 27 02:18:25 PM UTC 24 Aug 27 02:18:29 PM UTC 24 130496667 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.881348904 Aug 27 02:18:24 PM UTC 24 Aug 27 02:18:30 PM UTC 24 94164367 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2408985332 Aug 27 02:18:26 PM UTC 24 Aug 27 02:18:31 PM UTC 24 176554839 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2219803008 Aug 27 02:18:29 PM UTC 24 Aug 27 02:18:32 PM UTC 24 41006447 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.4040501320 Aug 27 02:18:27 PM UTC 24 Aug 27 02:18:32 PM UTC 24 516035896 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.951119421 Aug 27 02:18:25 PM UTC 24 Aug 27 02:18:33 PM UTC 24 295215198 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1071806741 Aug 27 02:18:28 PM UTC 24 Aug 27 02:18:33 PM UTC 24 474414996 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3203965179 Aug 27 02:18:31 PM UTC 24 Aug 27 02:18:33 PM UTC 24 32785554 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.4195800298 Aug 27 02:18:31 PM UTC 24 Aug 27 02:18:34 PM UTC 24 39865797 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2404480355 Aug 27 02:18:30 PM UTC 24 Aug 27 02:18:34 PM UTC 24 227785909 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.3565810816 Aug 27 02:18:27 PM UTC 24 Aug 27 02:18:34 PM UTC 24 129634023 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3719231311 Aug 27 02:18:30 PM UTC 24 Aug 27 02:18:35 PM UTC 24 301292892 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.945559849 Aug 27 02:18:34 PM UTC 24 Aug 27 02:18:36 PM UTC 24 14252227 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.832360539 Aug 27 02:18:32 PM UTC 24 Aug 27 02:18:37 PM UTC 24 162807268 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1390366158 Aug 27 02:18:32 PM UTC 24 Aug 27 02:18:37 PM UTC 24 108243892 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3995407335 Aug 27 02:18:34 PM UTC 24 Aug 27 02:18:37 PM UTC 24 256158959 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2217104606 Aug 27 02:18:35 PM UTC 24 Aug 27 02:18:37 PM UTC 24 323197004 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3023788281 Aug 27 02:18:35 PM UTC 24 Aug 27 02:18:37 PM UTC 24 38075248 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.208944536 Aug 27 02:18:36 PM UTC 24 Aug 27 02:18:38 PM UTC 24 98456891 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2407473724 Aug 27 02:18:36 PM UTC 24 Aug 27 02:18:38 PM UTC 24 46500150 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3806455908 Aug 27 02:18:35 PM UTC 24 Aug 27 02:18:39 PM UTC 24 26618053 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2308764411 Aug 27 02:18:34 PM UTC 24 Aug 27 02:18:39 PM UTC 24 170648803 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.2655277748 Aug 27 02:18:37 PM UTC 24 Aug 27 02:18:39 PM UTC 24 24797721 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.3617897561 Aug 27 02:18:37 PM UTC 24 Aug 27 02:18:39 PM UTC 24 26297216 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.228626005 Aug 27 02:18:38 PM UTC 24 Aug 27 02:18:40 PM UTC 24 19808114 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3457865971 Aug 27 02:18:38 PM UTC 24 Aug 27 02:18:40 PM UTC 24 63474779 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1119021189 Aug 27 02:18:38 PM UTC 24 Aug 27 02:18:40 PM UTC 24 37323987 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3478853211 Aug 27 02:18:39 PM UTC 24 Aug 27 02:18:41 PM UTC 24 13664238 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2926879084 Aug 27 02:18:40 PM UTC 24 Aug 27 02:18:41 PM UTC 24 43907716 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.1253918956 Aug 27 02:18:39 PM UTC 24 Aug 27 02:18:41 PM UTC 24 25761438 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1820980790 Aug 27 02:18:40 PM UTC 24 Aug 27 02:18:41 PM UTC 24 119941554 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.801804879 Aug 27 02:18:40 PM UTC 24 Aug 27 02:18:42 PM UTC 24 15865379 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.4292496659 Aug 27 02:18:40 PM UTC 24 Aug 27 02:18:42 PM UTC 24 36894547 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2760760489 Aug 27 02:18:41 PM UTC 24 Aug 27 02:18:43 PM UTC 24 11506541 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2413178384 Aug 27 02:18:41 PM UTC 24 Aug 27 02:18:43 PM UTC 24 14877311 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.1578002170 Aug 27 02:18:41 PM UTC 24 Aug 27 02:18:43 PM UTC 24 58678314 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2317461131 Aug 27 02:18:41 PM UTC 24 Aug 27 02:18:43 PM UTC 24 13760870 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.566858759 Aug 27 02:18:43 PM UTC 24 Aug 27 02:18:44 PM UTC 24 11743261 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1668425586 Aug 27 02:18:43 PM UTC 24 Aug 27 02:18:44 PM UTC 24 12730929 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.277192111 Aug 27 02:18:43 PM UTC 24 Aug 27 02:18:44 PM UTC 24 12115821 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.1205296677 Aug 27 02:18:43 PM UTC 24 Aug 27 02:18:44 PM UTC 24 31287802 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2185283694 Aug 27 02:18:43 PM UTC 24 Aug 27 02:18:45 PM UTC 24 13777067 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1852928019 Aug 27 02:18:43 PM UTC 24 Aug 27 02:18:45 PM UTC 24 17782842 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2759443169 Aug 27 02:18:44 PM UTC 24 Aug 27 02:18:46 PM UTC 24 46553313 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.1236656290 Aug 27 02:18:44 PM UTC 24 Aug 27 02:18:46 PM UTC 24 53282235 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1822695199 Aug 27 02:18:44 PM UTC 24 Aug 27 02:18:46 PM UTC 24 34277654 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2680366723 Aug 27 02:18:44 PM UTC 24 Aug 27 02:18:46 PM UTC 24 65267665 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3868965788 Aug 27 02:18:45 PM UTC 24 Aug 27 02:18:47 PM UTC 24 92209947 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3164751366 Aug 27 02:18:45 PM UTC 24 Aug 27 02:18:47 PM UTC 24 14840181 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3336661644 Aug 27 02:18:45 PM UTC 24 Aug 27 02:18:47 PM UTC 24 14173283 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2299775370 Aug 27 02:17:45 PM UTC 24 Aug 27 02:20:01 PM UTC 24 19082605399 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3061656756 Aug 27 02:17:31 PM UTC 24 Aug 27 02:34:02 PM UTC 24 218066263147 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.2658552848
Short name T1
Test name
Test status
Simulation time 148089865 ps
CPU time 6.31 seconds
Started Aug 27 01:42:43 PM UTC 24
Finished Aug 27 01:42:52 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658552848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2658552848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_smoke.815575281
Short name T22
Test name
Test status
Simulation time 3282209980 ps
CPU time 16.98 seconds
Started Aug 27 01:42:59 PM UTC 24
Finished Aug 27 01:43:17 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815575281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.815575281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.3114842476
Short name T14
Test name
Test status
Simulation time 2385100522 ps
CPU time 136.74 seconds
Started Aug 27 01:43:22 PM UTC 24
Finished Aug 27 01:45:41 PM UTC 24
Peak memory 215888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31148424
76 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3114842476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.739257537
Short name T30
Test name
Test status
Simulation time 13164536188 ps
CPU time 526.8 seconds
Started Aug 27 01:44:27 PM UTC 24
Finished Aug 27 01:53:21 PM UTC 24
Peak memory 498164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73925753
7 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.739257537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.3581361243
Short name T28
Test name
Test status
Simulation time 3036530571 ps
CPU time 49.11 seconds
Started Aug 27 01:43:04 PM UTC 24
Finished Aug 27 01:43:54 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581361243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3581361243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.202472845
Short name T65
Test name
Test status
Simulation time 148933712 ps
CPU time 1.43 seconds
Started Aug 27 01:42:53 PM UTC 24
Finished Aug 27 01:43:02 PM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202472845 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.202472845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1611864168
Short name T136
Test name
Test status
Simulation time 163108875 ps
CPU time 4.09 seconds
Started Aug 27 02:17:37 PM UTC 24
Finished Aug 27 02:17:42 PM UTC 24
Peak memory 207920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611864168 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1611864168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_stress_all.3798248163
Short name T73
Test name
Test status
Simulation time 4336181053 ps
CPU time 264.26 seconds
Started Aug 27 01:44:54 PM UTC 24
Finished Aug 27 01:49:23 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798248163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3798248163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_error.666423867
Short name T61
Test name
Test status
Simulation time 1659997703 ps
CPU time 84.55 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:44:21 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666423867 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.666423867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.2812331774
Short name T16
Test name
Test status
Simulation time 764336911 ps
CPU time 41.18 seconds
Started Aug 27 01:44:17 PM UTC 24
Finished Aug 27 01:45:00 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812331774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2812331774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.215629903
Short name T106
Test name
Test status
Simulation time 24129411 ps
CPU time 0.98 seconds
Started Aug 27 02:17:20 PM UTC 24
Finished Aug 27 02:17:22 PM UTC 24
Peak memory 206708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215629903 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.215629903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_smoke.4001165673
Short name T8
Test name
Test status
Simulation time 4816144504 ps
CPU time 14.29 seconds
Started Aug 27 01:42:39 PM UTC 24
Finished Aug 27 01:43:05 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001165673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4001165673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.2269563672
Short name T123
Test name
Test status
Simulation time 1766231392 ps
CPU time 94.45 seconds
Started Aug 27 01:44:51 PM UTC 24
Finished Aug 27 01:46:28 PM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269563672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2269563672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.2369551922
Short name T32
Test name
Test status
Simulation time 1187144193 ps
CPU time 18.75 seconds
Started Aug 27 01:54:17 PM UTC 24
Finished Aug 27 01:54:37 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369551922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2369551922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1951077536
Short name T75
Test name
Test status
Simulation time 893308102 ps
CPU time 5.94 seconds
Started Aug 27 02:18:11 PM UTC 24
Finished Aug 27 02:18:18 PM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951077536 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1951077536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_stress_all.3607596157
Short name T82
Test name
Test status
Simulation time 138353122242 ps
CPU time 266.4 seconds
Started Aug 27 02:09:26 PM UTC 24
Finished Aug 27 02:13:57 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607596157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3607596157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_alert_test.2818454463
Short name T2
Test name
Test status
Simulation time 56267415 ps
CPU time 0.64 seconds
Started Aug 27 01:42:42 PM UTC 24
Finished Aug 27 01:42:54 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818454463 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2818454463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_stress_all.1057386528
Short name T156
Test name
Test status
Simulation time 12519641302 ps
CPU time 851.54 seconds
Started Aug 27 02:00:01 PM UTC 24
Finished Aug 27 02:14:26 PM UTC 24
Peak memory 708964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057386528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1057386528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_long_msg.55670616
Short name T55
Test name
Test status
Simulation time 91506941025 ps
CPU time 109.89 seconds
Started Aug 27 01:42:39 PM UTC 24
Finished Aug 27 01:44:42 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55670616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.55670616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_stress_all.2030398813
Short name T18
Test name
Test status
Simulation time 47710933431 ps
CPU time 2179.17 seconds
Started Aug 27 02:11:33 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 768432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030398813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2030398813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.3629004919
Short name T13
Test name
Test status
Simulation time 6483465358 ps
CPU time 69.92 seconds
Started Aug 27 01:42:57 PM UTC 24
Finished Aug 27 01:44:11 PM UTC 24
Peak memory 369004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36290049
19 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3629004919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.1334054059
Short name T69
Test name
Test status
Simulation time 49605898 ps
CPU time 2.65 seconds
Started Aug 27 02:16:35 PM UTC 24
Finished Aug 27 02:16:38 PM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334054059 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1334054059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.1876186290
Short name T102
Test name
Test status
Simulation time 1765060789 ps
CPU time 8.22 seconds
Started Aug 27 02:16:45 PM UTC 24
Finished Aug 27 02:16:54 PM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876186290 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1876186290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.756074783
Short name T103
Test name
Test status
Simulation time 1332403590 ps
CPU time 15.73 seconds
Started Aug 27 02:16:44 PM UTC 24
Finished Aug 27 02:17:01 PM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756074783 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.756074783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.2500468319
Short name T100
Test name
Test status
Simulation time 16865058 ps
CPU time 1.11 seconds
Started Aug 27 02:16:41 PM UTC 24
Finished Aug 27 02:16:43 PM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500468319 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2500468319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3281467828
Short name T529
Test name
Test status
Simulation time 71360275 ps
CPU time 3.36 seconds
Started Aug 27 02:16:55 PM UTC 24
Finished Aug 27 02:16:59 PM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3281467828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.3281467828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.1352467597
Short name T101
Test name
Test status
Simulation time 144129450 ps
CPU time 1.1 seconds
Started Aug 27 02:16:42 PM UTC 24
Finished Aug 27 02:16:44 PM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352467597 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1352467597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.1167427098
Short name T528
Test name
Test status
Simulation time 14960442 ps
CPU time 0.79 seconds
Started Aug 27 02:16:40 PM UTC 24
Finished Aug 27 02:16:41 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167427098 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1167427098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1973360306
Short name T115
Test name
Test status
Simulation time 46781457 ps
CPU time 2.7 seconds
Started Aug 27 02:16:54 PM UTC 24
Finished Aug 27 02:16:58 PM UTC 24
Peak memory 207912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973360306 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.1973360306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.783617637
Short name T87
Test name
Test status
Simulation time 344148350 ps
CPU time 5.51 seconds
Started Aug 27 02:16:33 PM UTC 24
Finished Aug 27 02:16:40 PM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783617637 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.783617637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.743182376
Short name T104
Test name
Test status
Simulation time 2224915641 ps
CPU time 9.7 seconds
Started Aug 27 02:17:05 PM UTC 24
Finished Aug 27 02:17:15 PM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743182376 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.743182376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2339118230
Short name T535
Test name
Test status
Simulation time 1430213736 ps
CPU time 6.19 seconds
Started Aug 27 02:17:04 PM UTC 24
Finished Aug 27 02:17:11 PM UTC 24
Peak memory 207604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339118230 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2339118230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.1611771183
Short name T532
Test name
Test status
Simulation time 208763860 ps
CPU time 1.12 seconds
Started Aug 27 02:17:01 PM UTC 24
Finished Aug 27 02:17:03 PM UTC 24
Peak memory 206836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611771183 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1611771183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.214307710
Short name T534
Test name
Test status
Simulation time 258745495 ps
CPU time 1.73 seconds
Started Aug 27 02:17:06 PM UTC 24
Finished Aug 27 02:17:08 PM UTC 24
Peak memory 206664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=214307710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_re
set.214307710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.4138138234
Short name T533
Test name
Test status
Simulation time 41979644 ps
CPU time 1.22 seconds
Started Aug 27 02:17:02 PM UTC 24
Finished Aug 27 02:17:05 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138138234 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4138138234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2118584893
Short name T530
Test name
Test status
Simulation time 41212002 ps
CPU time 0.78 seconds
Started Aug 27 02:17:00 PM UTC 24
Finished Aug 27 02:17:02 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118584893 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2118584893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1166933799
Short name T116
Test name
Test status
Simulation time 22196307 ps
CPU time 1.3 seconds
Started Aug 27 02:17:05 PM UTC 24
Finished Aug 27 02:17:07 PM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166933799 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.1166933799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3455985718
Short name T531
Test name
Test status
Simulation time 2315123505 ps
CPU time 4.73 seconds
Started Aug 27 02:16:57 PM UTC 24
Finished Aug 27 02:17:03 PM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455985718 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3455985718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.2879325312
Short name T70
Test name
Test status
Simulation time 186266059 ps
CPU time 4.67 seconds
Started Aug 27 02:16:58 PM UTC 24
Finished Aug 27 02:17:04 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879325312 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2879325312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2845295344
Short name T576
Test name
Test status
Simulation time 61843366 ps
CPU time 2.69 seconds
Started Aug 27 02:18:06 PM UTC 24
Finished Aug 27 02:18:10 PM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2845295344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.2845295344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1568694621
Short name T572
Test name
Test status
Simulation time 173423491 ps
CPU time 1.07 seconds
Started Aug 27 02:18:06 PM UTC 24
Finished Aug 27 02:18:08 PM UTC 24
Peak memory 206336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568694621 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1568694621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2550117095
Short name T571
Test name
Test status
Simulation time 14804908 ps
CPU time 0.95 seconds
Started Aug 27 02:17:55 PM UTC 24
Finished Aug 27 02:17:57 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550117095 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2550117095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2771783901
Short name T573
Test name
Test status
Simulation time 36100238 ps
CPU time 1.85 seconds
Started Aug 27 02:18:06 PM UTC 24
Finished Aug 27 02:18:09 PM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771783901 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.2771783901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2961927155
Short name T569
Test name
Test status
Simulation time 72934858 ps
CPU time 2.01 seconds
Started Aug 27 02:17:53 PM UTC 24
Finished Aug 27 02:17:56 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961927155 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2961927155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.2377224276
Short name T137
Test name
Test status
Simulation time 638774661 ps
CPU time 6.72 seconds
Started Aug 27 02:17:54 PM UTC 24
Finished Aug 27 02:18:02 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377224276 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2377224276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2008812496
Short name T582
Test name
Test status
Simulation time 189914846 ps
CPU time 3.31 seconds
Started Aug 27 02:18:08 PM UTC 24
Finished Aug 27 02:18:13 PM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2008812496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.2008812496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.516399778
Short name T575
Test name
Test status
Simulation time 108219119 ps
CPU time 1.16 seconds
Started Aug 27 02:18:07 PM UTC 24
Finished Aug 27 02:18:10 PM UTC 24
Peak memory 206448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516399778 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.516399778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3654033102
Short name T574
Test name
Test status
Simulation time 68524362 ps
CPU time 0.88 seconds
Started Aug 27 02:18:07 PM UTC 24
Finished Aug 27 02:18:09 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654033102 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3654033102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2928639949
Short name T577
Test name
Test status
Simulation time 93972234 ps
CPU time 1.67 seconds
Started Aug 27 02:18:07 PM UTC 24
Finished Aug 27 02:18:10 PM UTC 24
Peak memory 206672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928639949 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.2928639949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1756551313
Short name T580
Test name
Test status
Simulation time 169299678 ps
CPU time 3.54 seconds
Started Aug 27 02:18:07 PM UTC 24
Finished Aug 27 02:18:12 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756551313 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1756551313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.2965774742
Short name T579
Test name
Test status
Simulation time 108136490 ps
CPU time 2.92 seconds
Started Aug 27 02:18:07 PM UTC 24
Finished Aug 27 02:18:11 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965774742 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2965774742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3720147783
Short name T585
Test name
Test status
Simulation time 60679985 ps
CPU time 2.41 seconds
Started Aug 27 02:18:12 PM UTC 24
Finished Aug 27 02:18:15 PM UTC 24
Peak memory 207860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3720147783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.3720147783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.2908031989
Short name T578
Test name
Test status
Simulation time 80348541 ps
CPU time 1.2 seconds
Started Aug 27 02:18:11 PM UTC 24
Finished Aug 27 02:18:13 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908031989 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2908031989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1867428360
Short name T581
Test name
Test status
Simulation time 15755148 ps
CPU time 0.93 seconds
Started Aug 27 02:18:11 PM UTC 24
Finished Aug 27 02:18:13 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867428360 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1867428360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.105492526
Short name T583
Test name
Test status
Simulation time 185597182 ps
CPU time 2.56 seconds
Started Aug 27 02:18:11 PM UTC 24
Finished Aug 27 02:18:14 PM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105492526 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.105492526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.1192542184
Short name T584
Test name
Test status
Simulation time 227456404 ps
CPU time 4.01 seconds
Started Aug 27 02:18:09 PM UTC 24
Finished Aug 27 02:18:15 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192542184 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1192542184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2368592077
Short name T593
Test name
Test status
Simulation time 36702536 ps
CPU time 3.31 seconds
Started Aug 27 02:18:16 PM UTC 24
Finished Aug 27 02:18:21 PM UTC 24
Peak memory 207864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2368592077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.2368592077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2586643439
Short name T587
Test name
Test status
Simulation time 119718953 ps
CPU time 0.98 seconds
Started Aug 27 02:18:14 PM UTC 24
Finished Aug 27 02:18:17 PM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586643439 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2586643439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1345812920
Short name T586
Test name
Test status
Simulation time 32708750 ps
CPU time 0.89 seconds
Started Aug 27 02:18:14 PM UTC 24
Finished Aug 27 02:18:16 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345812920 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1345812920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3754366889
Short name T589
Test name
Test status
Simulation time 36462255 ps
CPU time 2.46 seconds
Started Aug 27 02:18:15 PM UTC 24
Finished Aug 27 02:18:18 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754366889 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.3754366889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1899624175
Short name T588
Test name
Test status
Simulation time 350293096 ps
CPU time 2.82 seconds
Started Aug 27 02:18:13 PM UTC 24
Finished Aug 27 02:18:17 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899624175 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1899624175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1909643701
Short name T139
Test name
Test status
Simulation time 652665727 ps
CPU time 5.45 seconds
Started Aug 27 02:18:13 PM UTC 24
Finished Aug 27 02:18:19 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909643701 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1909643701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1988064035
Short name T596
Test name
Test status
Simulation time 22672922 ps
CPU time 2.35 seconds
Started Aug 27 02:18:20 PM UTC 24
Finished Aug 27 02:18:23 PM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1988064035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.1988064035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.3139339670
Short name T591
Test name
Test status
Simulation time 13428150 ps
CPU time 0.98 seconds
Started Aug 27 02:18:17 PM UTC 24
Finished Aug 27 02:18:19 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139339670 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3139339670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.547350503
Short name T590
Test name
Test status
Simulation time 20535560 ps
CPU time 0.75 seconds
Started Aug 27 02:18:17 PM UTC 24
Finished Aug 27 02:18:19 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547350503 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.547350503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2399741436
Short name T594
Test name
Test status
Simulation time 38475997 ps
CPU time 1.68 seconds
Started Aug 27 02:18:18 PM UTC 24
Finished Aug 27 02:18:21 PM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399741436 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.2399741436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.459347180
Short name T592
Test name
Test status
Simulation time 149933665 ps
CPU time 2.69 seconds
Started Aug 27 02:18:16 PM UTC 24
Finished Aug 27 02:18:20 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459347180 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.459347180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.973504137
Short name T598
Test name
Test status
Simulation time 124972433 ps
CPU time 5.68 seconds
Started Aug 27 02:18:17 PM UTC 24
Finished Aug 27 02:18:24 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973504137 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.973504137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1995732435
Short name T602
Test name
Test status
Simulation time 254342235 ps
CPU time 3.09 seconds
Started Aug 27 02:18:22 PM UTC 24
Finished Aug 27 02:18:26 PM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1995732435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.1995732435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.1790464944
Short name T597
Test name
Test status
Simulation time 19628472 ps
CPU time 1.39 seconds
Started Aug 27 02:18:21 PM UTC 24
Finished Aug 27 02:18:23 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790464944 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1790464944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.997167399
Short name T595
Test name
Test status
Simulation time 48983118 ps
CPU time 0.84 seconds
Started Aug 27 02:18:21 PM UTC 24
Finished Aug 27 02:18:23 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997167399 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.997167399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1601450659
Short name T601
Test name
Test status
Simulation time 113953604 ps
CPU time 2.9 seconds
Started Aug 27 02:18:22 PM UTC 24
Finished Aug 27 02:18:26 PM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601450659 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.1601450659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2352981681
Short name T600
Test name
Test status
Simulation time 715541826 ps
CPU time 4.92 seconds
Started Aug 27 02:18:20 PM UTC 24
Finished Aug 27 02:18:26 PM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352981681 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2352981681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.610020602
Short name T599
Test name
Test status
Simulation time 52606097 ps
CPU time 2.72 seconds
Started Aug 27 02:18:21 PM UTC 24
Finished Aug 27 02:18:25 PM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610020602 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.610020602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2408985332
Short name T609
Test name
Test status
Simulation time 176554839 ps
CPU time 4.1 seconds
Started Aug 27 02:18:26 PM UTC 24
Finished Aug 27 02:18:31 PM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2408985332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.2408985332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.22633951
Short name T604
Test name
Test status
Simulation time 120416642 ps
CPU time 1.29 seconds
Started Aug 27 02:18:25 PM UTC 24
Finished Aug 27 02:18:27 PM UTC 24
Peak memory 206532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22633951 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.22633951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.128528257
Short name T603
Test name
Test status
Simulation time 52747051 ps
CPU time 0.85 seconds
Started Aug 27 02:18:25 PM UTC 24
Finished Aug 27 02:18:27 PM UTC 24
Peak memory 203560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128528257 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.128528257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1762513031
Short name T607
Test name
Test status
Simulation time 130496667 ps
CPU time 3.15 seconds
Started Aug 27 02:18:25 PM UTC 24
Finished Aug 27 02:18:29 PM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762513031 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1762513031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.881348904
Short name T608
Test name
Test status
Simulation time 94164367 ps
CPU time 4.19 seconds
Started Aug 27 02:18:24 PM UTC 24
Finished Aug 27 02:18:30 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881348904 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.881348904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.951119421
Short name T140
Test name
Test status
Simulation time 295215198 ps
CPU time 6.84 seconds
Started Aug 27 02:18:25 PM UTC 24
Finished Aug 27 02:18:33 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951119421 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.951119421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2219803008
Short name T610
Test name
Test status
Simulation time 41006447 ps
CPU time 1.56 seconds
Started Aug 27 02:18:29 PM UTC 24
Finished Aug 27 02:18:32 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2219803008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2219803008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3985914783
Short name T606
Test name
Test status
Simulation time 30441516 ps
CPU time 1.01 seconds
Started Aug 27 02:18:27 PM UTC 24
Finished Aug 27 02:18:29 PM UTC 24
Peak memory 206096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985914783 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3985914783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3149356574
Short name T605
Test name
Test status
Simulation time 27623861 ps
CPU time 0.84 seconds
Started Aug 27 02:18:27 PM UTC 24
Finished Aug 27 02:18:29 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149356574 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3149356574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1071806741
Short name T612
Test name
Test status
Simulation time 474414996 ps
CPU time 3.88 seconds
Started Aug 27 02:18:28 PM UTC 24
Finished Aug 27 02:18:33 PM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071806741 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.1071806741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.4040501320
Short name T611
Test name
Test status
Simulation time 516035896 ps
CPU time 4.03 seconds
Started Aug 27 02:18:27 PM UTC 24
Finished Aug 27 02:18:32 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040501320 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4040501320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.3565810816
Short name T616
Test name
Test status
Simulation time 129634023 ps
CPU time 6.12 seconds
Started Aug 27 02:18:27 PM UTC 24
Finished Aug 27 02:18:34 PM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565810816 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3565810816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1390366158
Short name T620
Test name
Test status
Simulation time 108243892 ps
CPU time 2.95 seconds
Started Aug 27 02:18:32 PM UTC 24
Finished Aug 27 02:18:37 PM UTC 24
Peak memory 218364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1390366158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.1390366158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.4195800298
Short name T614
Test name
Test status
Simulation time 39865797 ps
CPU time 1.11 seconds
Started Aug 27 02:18:31 PM UTC 24
Finished Aug 27 02:18:34 PM UTC 24
Peak memory 206444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195800298 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4195800298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3203965179
Short name T613
Test name
Test status
Simulation time 32785554 ps
CPU time 0.8 seconds
Started Aug 27 02:18:31 PM UTC 24
Finished Aug 27 02:18:33 PM UTC 24
Peak memory 203564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203965179 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3203965179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.832360539
Short name T619
Test name
Test status
Simulation time 162807268 ps
CPU time 2.94 seconds
Started Aug 27 02:18:32 PM UTC 24
Finished Aug 27 02:18:37 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832360539 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.832360539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2404480355
Short name T615
Test name
Test status
Simulation time 227785909 ps
CPU time 2.47 seconds
Started Aug 27 02:18:30 PM UTC 24
Finished Aug 27 02:18:34 PM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404480355 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2404480355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3719231311
Short name T617
Test name
Test status
Simulation time 301292892 ps
CPU time 4.09 seconds
Started Aug 27 02:18:30 PM UTC 24
Finished Aug 27 02:18:35 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719231311 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3719231311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3806455908
Short name T626
Test name
Test status
Simulation time 26618053 ps
CPU time 2.56 seconds
Started Aug 27 02:18:35 PM UTC 24
Finished Aug 27 02:18:39 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3806455908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.3806455908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2217104606
Short name T622
Test name
Test status
Simulation time 323197004 ps
CPU time 1.15 seconds
Started Aug 27 02:18:35 PM UTC 24
Finished Aug 27 02:18:37 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217104606 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2217104606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.945559849
Short name T618
Test name
Test status
Simulation time 14252227 ps
CPU time 0.85 seconds
Started Aug 27 02:18:34 PM UTC 24
Finished Aug 27 02:18:36 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945559849 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.945559849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3023788281
Short name T623
Test name
Test status
Simulation time 38075248 ps
CPU time 1.53 seconds
Started Aug 27 02:18:35 PM UTC 24
Finished Aug 27 02:18:37 PM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023788281 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.3023788281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3995407335
Short name T621
Test name
Test status
Simulation time 256158959 ps
CPU time 2.26 seconds
Started Aug 27 02:18:34 PM UTC 24
Finished Aug 27 02:18:37 PM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995407335 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3995407335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2308764411
Short name T627
Test name
Test status
Simulation time 170648803 ps
CPU time 3.93 seconds
Started Aug 27 02:18:34 PM UTC 24
Finished Aug 27 02:18:39 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308764411 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2308764411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.342955345
Short name T110
Test name
Test status
Simulation time 1773993305 ps
CPU time 10.94 seconds
Started Aug 27 02:17:15 PM UTC 24
Finished Aug 27 02:17:27 PM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342955345 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.342955345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2366117998
Short name T109
Test name
Test status
Simulation time 1866869508 ps
CPU time 11.21 seconds
Started Aug 27 02:17:14 PM UTC 24
Finished Aug 27 02:17:26 PM UTC 24
Peak memory 207604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366117998 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2366117998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3266430099
Short name T538
Test name
Test status
Simulation time 69603571 ps
CPU time 1.1 seconds
Started Aug 27 02:17:13 PM UTC 24
Finished Aug 27 02:17:16 PM UTC 24
Peak memory 205924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266430099 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3266430099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.178207592
Short name T539
Test name
Test status
Simulation time 34582776 ps
CPU time 1.66 seconds
Started Aug 27 02:17:17 PM UTC 24
Finished Aug 27 02:17:19 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=178207592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_re
set.178207592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2383460515
Short name T105
Test name
Test status
Simulation time 134618619 ps
CPU time 1.27 seconds
Started Aug 27 02:17:14 PM UTC 24
Finished Aug 27 02:17:16 PM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383460515 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2383460515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3330538701
Short name T537
Test name
Test status
Simulation time 48375443 ps
CPU time 0.87 seconds
Started Aug 27 02:17:13 PM UTC 24
Finished Aug 27 02:17:15 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330538701 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3330538701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1596473541
Short name T117
Test name
Test status
Simulation time 42198301 ps
CPU time 1.6 seconds
Started Aug 27 02:17:17 PM UTC 24
Finished Aug 27 02:17:19 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596473541 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.1596473541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1579638131
Short name T536
Test name
Test status
Simulation time 74065469 ps
CPU time 2.36 seconds
Started Aug 27 02:17:08 PM UTC 24
Finished Aug 27 02:17:11 PM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579638131 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1579638131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.976533766
Short name T71
Test name
Test status
Simulation time 88941241 ps
CPU time 2.94 seconds
Started Aug 27 02:17:13 PM UTC 24
Finished Aug 27 02:17:17 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976533766 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.976533766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2407473724
Short name T625
Test name
Test status
Simulation time 46500150 ps
CPU time 0.96 seconds
Started Aug 27 02:18:36 PM UTC 24
Finished Aug 27 02:18:38 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407473724 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2407473724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.208944536
Short name T624
Test name
Test status
Simulation time 98456891 ps
CPU time 0.86 seconds
Started Aug 27 02:18:36 PM UTC 24
Finished Aug 27 02:18:38 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208944536 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.208944536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.2655277748
Short name T628
Test name
Test status
Simulation time 24797721 ps
CPU time 0.84 seconds
Started Aug 27 02:18:37 PM UTC 24
Finished Aug 27 02:18:39 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655277748 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2655277748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.3617897561
Short name T629
Test name
Test status
Simulation time 26297216 ps
CPU time 0.9 seconds
Started Aug 27 02:18:37 PM UTC 24
Finished Aug 27 02:18:39 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617897561 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3617897561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3457865971
Short name T631
Test name
Test status
Simulation time 63474779 ps
CPU time 0.89 seconds
Started Aug 27 02:18:38 PM UTC 24
Finished Aug 27 02:18:40 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457865971 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3457865971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.228626005
Short name T630
Test name
Test status
Simulation time 19808114 ps
CPU time 0.81 seconds
Started Aug 27 02:18:38 PM UTC 24
Finished Aug 27 02:18:40 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228626005 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.228626005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1119021189
Short name T632
Test name
Test status
Simulation time 37323987 ps
CPU time 0.85 seconds
Started Aug 27 02:18:38 PM UTC 24
Finished Aug 27 02:18:40 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119021189 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1119021189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.1253918956
Short name T635
Test name
Test status
Simulation time 25761438 ps
CPU time 0.88 seconds
Started Aug 27 02:18:39 PM UTC 24
Finished Aug 27 02:18:41 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253918956 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1253918956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3478853211
Short name T633
Test name
Test status
Simulation time 13664238 ps
CPU time 0.92 seconds
Started Aug 27 02:18:39 PM UTC 24
Finished Aug 27 02:18:41 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478853211 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3478853211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1820980790
Short name T636
Test name
Test status
Simulation time 119941554 ps
CPU time 0.89 seconds
Started Aug 27 02:18:40 PM UTC 24
Finished Aug 27 02:18:41 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820980790 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1820980790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1673740811
Short name T108
Test name
Test status
Simulation time 611430026 ps
CPU time 3.67 seconds
Started Aug 27 02:17:21 PM UTC 24
Finished Aug 27 02:17:26 PM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673740811 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1673740811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3797523743
Short name T111
Test name
Test status
Simulation time 517695723 ps
CPU time 6.89 seconds
Started Aug 27 02:17:21 PM UTC 24
Finished Aug 27 02:17:29 PM UTC 24
Peak memory 207592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797523743 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3797523743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2711790994
Short name T107
Test name
Test status
Simulation time 64519712 ps
CPU time 1.27 seconds
Started Aug 27 02:17:20 PM UTC 24
Finished Aug 27 02:17:22 PM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711790994 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2711790994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1285143016
Short name T542
Test name
Test status
Simulation time 147346130 ps
CPU time 3.44 seconds
Started Aug 27 02:17:22 PM UTC 24
Finished Aug 27 02:17:27 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1285143016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.1285143016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.4092298434
Short name T540
Test name
Test status
Simulation time 27802860 ps
CPU time 0.84 seconds
Started Aug 27 02:17:18 PM UTC 24
Finished Aug 27 02:17:20 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092298434 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4092298434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4053118068
Short name T118
Test name
Test status
Simulation time 22605743 ps
CPU time 1.62 seconds
Started Aug 27 02:17:22 PM UTC 24
Finished Aug 27 02:17:25 PM UTC 24
Peak memory 206784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053118068 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.4053118068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.1007071388
Short name T541
Test name
Test status
Simulation time 28180017 ps
CPU time 1.95 seconds
Started Aug 27 02:17:17 PM UTC 24
Finished Aug 27 02:17:20 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007071388 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1007071388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.4042855701
Short name T135
Test name
Test status
Simulation time 101093025 ps
CPU time 3.03 seconds
Started Aug 27 02:17:17 PM UTC 24
Finished Aug 27 02:17:21 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042855701 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4042855701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2926879084
Short name T634
Test name
Test status
Simulation time 43907716 ps
CPU time 0.76 seconds
Started Aug 27 02:18:40 PM UTC 24
Finished Aug 27 02:18:41 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926879084 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2926879084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.801804879
Short name T637
Test name
Test status
Simulation time 15865379 ps
CPU time 0.86 seconds
Started Aug 27 02:18:40 PM UTC 24
Finished Aug 27 02:18:42 PM UTC 24
Peak memory 203204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801804879 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.801804879
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.4292496659
Short name T638
Test name
Test status
Simulation time 36894547 ps
CPU time 0.83 seconds
Started Aug 27 02:18:40 PM UTC 24
Finished Aug 27 02:18:42 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292496659 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4292496659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2760760489
Short name T639
Test name
Test status
Simulation time 11506541 ps
CPU time 0.8 seconds
Started Aug 27 02:18:41 PM UTC 24
Finished Aug 27 02:18:43 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760760489 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2760760489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2413178384
Short name T640
Test name
Test status
Simulation time 14877311 ps
CPU time 0.88 seconds
Started Aug 27 02:18:41 PM UTC 24
Finished Aug 27 02:18:43 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413178384 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2413178384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.1578002170
Short name T641
Test name
Test status
Simulation time 58678314 ps
CPU time 0.87 seconds
Started Aug 27 02:18:41 PM UTC 24
Finished Aug 27 02:18:43 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578002170 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1578002170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2317461131
Short name T642
Test name
Test status
Simulation time 13760870 ps
CPU time 0.97 seconds
Started Aug 27 02:18:41 PM UTC 24
Finished Aug 27 02:18:43 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317461131 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2317461131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.566858759
Short name T643
Test name
Test status
Simulation time 11743261 ps
CPU time 0.77 seconds
Started Aug 27 02:18:43 PM UTC 24
Finished Aug 27 02:18:44 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566858759 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.566858759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1668425586
Short name T644
Test name
Test status
Simulation time 12730929 ps
CPU time 0.84 seconds
Started Aug 27 02:18:43 PM UTC 24
Finished Aug 27 02:18:44 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668425586 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1668425586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.277192111
Short name T645
Test name
Test status
Simulation time 12115821 ps
CPU time 0.86 seconds
Started Aug 27 02:18:43 PM UTC 24
Finished Aug 27 02:18:44 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277192111 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.277192111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1967365557
Short name T114
Test name
Test status
Simulation time 1631163125 ps
CPU time 12.24 seconds
Started Aug 27 02:17:29 PM UTC 24
Finished Aug 27 02:17:42 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967365557 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1967365557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.1720039739
Short name T552
Test name
Test status
Simulation time 1492352663 ps
CPU time 12.72 seconds
Started Aug 27 02:17:29 PM UTC 24
Finished Aug 27 02:17:42 PM UTC 24
Peak memory 207884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720039739 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1720039739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.3169847430
Short name T544
Test name
Test status
Simulation time 84309491 ps
CPU time 1.41 seconds
Started Aug 27 02:17:26 PM UTC 24
Finished Aug 27 02:17:29 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169847430 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3169847430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3061656756
Short name T657
Test name
Test status
Simulation time 218066263147 ps
CPU time 980.86 seconds
Started Aug 27 02:17:31 PM UTC 24
Finished Aug 27 02:34:02 PM UTC 24
Peak memory 222896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3061656756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.3061656756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.207393137
Short name T112
Test name
Test status
Simulation time 49435796 ps
CPU time 0.95 seconds
Started Aug 27 02:17:27 PM UTC 24
Finished Aug 27 02:17:29 PM UTC 24
Peak memory 205712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207393137 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.207393137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.2718463056
Short name T543
Test name
Test status
Simulation time 26260371 ps
CPU time 0.78 seconds
Started Aug 27 02:17:26 PM UTC 24
Finished Aug 27 02:17:28 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718463056 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2718463056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1882766559
Short name T119
Test name
Test status
Simulation time 595701045 ps
CPU time 3.26 seconds
Started Aug 27 02:17:30 PM UTC 24
Finished Aug 27 02:17:35 PM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882766559 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.1882766559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.698288978
Short name T545
Test name
Test status
Simulation time 1178515222 ps
CPU time 5.86 seconds
Started Aug 27 02:17:23 PM UTC 24
Finished Aug 27 02:17:30 PM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698288978 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.698288978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1311077005
Short name T134
Test name
Test status
Simulation time 172752360 ps
CPU time 3.29 seconds
Started Aug 27 02:17:25 PM UTC 24
Finished Aug 27 02:17:30 PM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311077005 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1311077005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.1205296677
Short name T646
Test name
Test status
Simulation time 31287802 ps
CPU time 0.75 seconds
Started Aug 27 02:18:43 PM UTC 24
Finished Aug 27 02:18:44 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205296677 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1205296677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2185283694
Short name T647
Test name
Test status
Simulation time 13777067 ps
CPU time 0.82 seconds
Started Aug 27 02:18:43 PM UTC 24
Finished Aug 27 02:18:45 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185283694 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2185283694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1852928019
Short name T648
Test name
Test status
Simulation time 17782842 ps
CPU time 1.03 seconds
Started Aug 27 02:18:43 PM UTC 24
Finished Aug 27 02:18:45 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852928019 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1852928019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2759443169
Short name T649
Test name
Test status
Simulation time 46553313 ps
CPU time 0.85 seconds
Started Aug 27 02:18:44 PM UTC 24
Finished Aug 27 02:18:46 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759443169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2759443169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.1236656290
Short name T650
Test name
Test status
Simulation time 53282235 ps
CPU time 0.83 seconds
Started Aug 27 02:18:44 PM UTC 24
Finished Aug 27 02:18:46 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236656290 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1236656290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1822695199
Short name T651
Test name
Test status
Simulation time 34277654 ps
CPU time 0.78 seconds
Started Aug 27 02:18:44 PM UTC 24
Finished Aug 27 02:18:46 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822695199 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1822695199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2680366723
Short name T652
Test name
Test status
Simulation time 65267665 ps
CPU time 0.79 seconds
Started Aug 27 02:18:44 PM UTC 24
Finished Aug 27 02:18:46 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680366723 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2680366723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3164751366
Short name T654
Test name
Test status
Simulation time 14840181 ps
CPU time 0.95 seconds
Started Aug 27 02:18:45 PM UTC 24
Finished Aug 27 02:18:47 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164751366 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3164751366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3868965788
Short name T653
Test name
Test status
Simulation time 92209947 ps
CPU time 0.9 seconds
Started Aug 27 02:18:45 PM UTC 24
Finished Aug 27 02:18:47 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868965788 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3868965788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3336661644
Short name T655
Test name
Test status
Simulation time 14173283 ps
CPU time 0.94 seconds
Started Aug 27 02:18:45 PM UTC 24
Finished Aug 27 02:18:47 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336661644 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3336661644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3455800690
Short name T548
Test name
Test status
Simulation time 269546495 ps
CPU time 4.62 seconds
Started Aug 27 02:17:34 PM UTC 24
Finished Aug 27 02:17:40 PM UTC 24
Peak memory 218040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3455800690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.3455800690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.999270064
Short name T113
Test name
Test status
Simulation time 59958260 ps
CPU time 1.37 seconds
Started Aug 27 02:17:31 PM UTC 24
Finished Aug 27 02:17:33 PM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999270064 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.999270064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.2780688791
Short name T546
Test name
Test status
Simulation time 24395769 ps
CPU time 0.86 seconds
Started Aug 27 02:17:31 PM UTC 24
Finished Aug 27 02:17:33 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780688791 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2780688791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.308432777
Short name T120
Test name
Test status
Simulation time 285165725 ps
CPU time 3.79 seconds
Started Aug 27 02:17:34 PM UTC 24
Finished Aug 27 02:17:39 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308432777 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.308432777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.1313395226
Short name T547
Test name
Test status
Simulation time 1038528637 ps
CPU time 5.92 seconds
Started Aug 27 02:17:31 PM UTC 24
Finished Aug 27 02:17:38 PM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313395226 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1313395226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.116671357
Short name T132
Test name
Test status
Simulation time 133166856 ps
CPU time 4.36 seconds
Started Aug 27 02:17:31 PM UTC 24
Finished Aug 27 02:17:36 PM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116671357 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.116671357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.654489011
Short name T555
Test name
Test status
Simulation time 74012734 ps
CPU time 3.09 seconds
Started Aug 27 02:17:40 PM UTC 24
Finished Aug 27 02:17:44 PM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=654489011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_re
set.654489011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.4139683067
Short name T551
Test name
Test status
Simulation time 17964992 ps
CPU time 1.04 seconds
Started Aug 27 02:17:39 PM UTC 24
Finished Aug 27 02:17:41 PM UTC 24
Peak memory 206892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139683067 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4139683067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.3072361947
Short name T549
Test name
Test status
Simulation time 41507786 ps
CPU time 0.83 seconds
Started Aug 27 02:17:38 PM UTC 24
Finished Aug 27 02:17:40 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072361947 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3072361947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3403944692
Short name T553
Test name
Test status
Simulation time 178234388 ps
CPU time 2.68 seconds
Started Aug 27 02:17:40 PM UTC 24
Finished Aug 27 02:17:44 PM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403944692 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.3403944692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.91504009
Short name T550
Test name
Test status
Simulation time 150487955 ps
CPU time 3.8 seconds
Started Aug 27 02:17:36 PM UTC 24
Finished Aug 27 02:17:41 PM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91504009 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.91504009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2299775370
Short name T656
Test name
Test status
Simulation time 19082605399 ps
CPU time 133.69 seconds
Started Aug 27 02:17:45 PM UTC 24
Finished Aug 27 02:20:01 PM UTC 24
Peak memory 218092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2299775370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.2299775370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.333628647
Short name T556
Test name
Test status
Simulation time 53139295 ps
CPU time 1.19 seconds
Started Aug 27 02:17:44 PM UTC 24
Finished Aug 27 02:17:46 PM UTC 24
Peak memory 206656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333628647 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.333628647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1727949848
Short name T554
Test name
Test status
Simulation time 12854096 ps
CPU time 0.83 seconds
Started Aug 27 02:17:42 PM UTC 24
Finished Aug 27 02:17:44 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727949848 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1727949848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1508120020
Short name T558
Test name
Test status
Simulation time 221728631 ps
CPU time 1.81 seconds
Started Aug 27 02:17:44 PM UTC 24
Finished Aug 27 02:17:46 PM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508120020 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.1508120020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.3932493173
Short name T557
Test name
Test status
Simulation time 256831963 ps
CPU time 3.28 seconds
Started Aug 27 02:17:41 PM UTC 24
Finished Aug 27 02:17:46 PM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932493173 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3932493173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2836273601
Short name T133
Test name
Test status
Simulation time 508018158 ps
CPU time 4.16 seconds
Started Aug 27 02:17:42 PM UTC 24
Finished Aug 27 02:17:48 PM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836273601 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2836273601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3830159445
Short name T565
Test name
Test status
Simulation time 181238852 ps
CPU time 4.7 seconds
Started Aug 27 02:17:48 PM UTC 24
Finished Aug 27 02:17:54 PM UTC 24
Peak memory 218032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3830159445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.3830159445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1247786653
Short name T561
Test name
Test status
Simulation time 45864067 ps
CPU time 1.36 seconds
Started Aug 27 02:17:47 PM UTC 24
Finished Aug 27 02:17:49 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247786653 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1247786653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.151082242
Short name T560
Test name
Test status
Simulation time 37248465 ps
CPU time 0.87 seconds
Started Aug 27 02:17:47 PM UTC 24
Finished Aug 27 02:17:49 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151082242 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.151082242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3932133229
Short name T562
Test name
Test status
Simulation time 25464739 ps
CPU time 1.69 seconds
Started Aug 27 02:17:47 PM UTC 24
Finished Aug 27 02:17:50 PM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932133229 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.3932133229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.1840713759
Short name T559
Test name
Test status
Simulation time 142641614 ps
CPU time 2.27 seconds
Started Aug 27 02:17:45 PM UTC 24
Finished Aug 27 02:17:48 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840713759 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1840713759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.981526760
Short name T138
Test name
Test status
Simulation time 126846913 ps
CPU time 2.89 seconds
Started Aug 27 02:17:46 PM UTC 24
Finished Aug 27 02:17:50 PM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981526760 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.981526760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3767149841
Short name T567
Test name
Test status
Simulation time 71388911 ps
CPU time 3.48 seconds
Started Aug 27 02:17:51 PM UTC 24
Finished Aug 27 02:17:55 PM UTC 24
Peak memory 223988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3767149841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3767149841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.3093265393
Short name T564
Test name
Test status
Simulation time 53155544 ps
CPU time 1.1 seconds
Started Aug 27 02:17:50 PM UTC 24
Finished Aug 27 02:17:53 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093265393 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3093265393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.3571882082
Short name T563
Test name
Test status
Simulation time 35007398 ps
CPU time 0.9 seconds
Started Aug 27 02:17:50 PM UTC 24
Finished Aug 27 02:17:52 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571882082 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3571882082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.41242676
Short name T566
Test name
Test status
Simulation time 61801656 ps
CPU time 2.69 seconds
Started Aug 27 02:17:51 PM UTC 24
Finished Aug 27 02:17:54 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41242676 -assert nopostproc +UVM_
TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.41242676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2418220883
Short name T570
Test name
Test status
Simulation time 635779032 ps
CPU time 4.57 seconds
Started Aug 27 02:17:50 PM UTC 24
Finished Aug 27 02:17:56 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418220883 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2418220883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2318139303
Short name T568
Test name
Test status
Simulation time 587893576 ps
CPU time 4.22 seconds
Started Aug 27 02:17:50 PM UTC 24
Finished Aug 27 02:17:56 PM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318139303 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2318139303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.3148646178
Short name T7
Test name
Test status
Simulation time 420098485 ps
CPU time 10.09 seconds
Started Aug 27 01:42:39 PM UTC 24
Finished Aug 27 01:43:01 PM UTC 24
Peak memory 207068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148646178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3148646178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.3821304898
Short name T5
Test name
Test status
Simulation time 1005482803 ps
CPU time 6.41 seconds
Started Aug 27 01:42:40 PM UTC 24
Finished Aug 27 01:42:57 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821304898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3821304898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.1909395223
Short name T318
Test name
Test status
Simulation time 5364169329 ps
CPU time 1029.97 seconds
Started Aug 27 01:42:39 PM UTC 24
Finished Aug 27 02:00:11 PM UTC 24
Peak memory 770160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909395223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1909395223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_error.3880367067
Short name T12
Test name
Test status
Simulation time 52116184 ps
CPU time 4 seconds
Started Aug 27 01:42:40 PM UTC 24
Finished Aug 27 01:42:55 PM UTC 24
Peak memory 207036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880367067 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3880367067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.3602605882
Short name T3
Test name
Test status
Simulation time 62342828 ps
CPU time 0.93 seconds
Started Aug 27 01:42:42 PM UTC 24
Finished Aug 27 01:42:54 PM UTC 24
Peak memory 235228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602605882 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3602605882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_stress_all.3350392634
Short name T80
Test name
Test status
Simulation time 288405303969 ps
CPU time 992.09 seconds
Started Aug 27 01:42:41 PM UTC 24
Finished Aug 27 01:59:27 PM UTC 24
Peak memory 688676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350392634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3350392634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.1597535479
Short name T29
Test name
Test status
Simulation time 7329385621 ps
CPU time 344.95 seconds
Started Aug 27 01:42:42 PM UTC 24
Finished Aug 27 01:48:45 PM UTC 24
Peak memory 653348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15975354
79 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1597535479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.1382913140
Short name T58
Test name
Test status
Simulation time 1633354817 ps
CPU time 73.68 seconds
Started Aug 27 01:42:41 PM UTC 24
Finished Aug 27 01:43:59 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382913140 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1382913140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2402927511
Short name T60
Test name
Test status
Simulation time 15014964480 ps
CPU time 89.75 seconds
Started Aug 27 01:42:41 PM UTC 24
Finished Aug 27 01:44:16 PM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402927511 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2402927511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1146598497
Short name T163
Test name
Test status
Simulation time 3123954892 ps
CPU time 119.13 seconds
Started Aug 27 01:42:41 PM UTC 24
Finished Aug 27 01:44:45 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146598497 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1146598497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.1221274827
Short name T261
Test name
Test status
Simulation time 70072496303 ps
CPU time 681.26 seconds
Started Aug 27 01:42:40 PM UTC 24
Finished Aug 27 01:54:20 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221274827 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1221274827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.2212929974
Short name T499
Test name
Test status
Simulation time 824281795977 ps
CPU time 2672.49 seconds
Started Aug 27 01:42:40 PM UTC 24
Finished Aug 27 02:27:51 PM UTC 24
Peak memory 227452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212929974 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2212929974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.1634501233
Short name T483
Test name
Test status
Simulation time 39949295182 ps
CPU time 2082.61 seconds
Started Aug 27 01:42:40 PM UTC 24
Finished Aug 27 02:17:55 PM UTC 24
Peak memory 227320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634501233 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1634501233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.531232441
Short name T23
Test name
Test status
Simulation time 8806864182 ps
CPU time 60.93 seconds
Started Aug 27 01:42:40 PM UTC 24
Finished Aug 27 01:43:52 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531232441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.531232441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_alert_test.2878883602
Short name T20
Test name
Test status
Simulation time 38236766 ps
CPU time 0.7 seconds
Started Aug 27 01:42:53 PM UTC 24
Finished Aug 27 01:42:55 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878883602 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2878883602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.3761183651
Short name T26
Test name
Test status
Simulation time 817391901 ps
CPU time 42.64 seconds
Started Aug 27 01:42:42 PM UTC 24
Finished Aug 27 01:43:33 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761183651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3761183651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.1889166517
Short name T356
Test name
Test status
Simulation time 26935454365 ps
CPU time 1212.35 seconds
Started Aug 27 01:42:43 PM UTC 24
Finished Aug 27 02:03:09 PM UTC 24
Peak memory 762144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889166517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1889166517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_error.1194615705
Short name T59
Test name
Test status
Simulation time 2403208641 ps
CPU time 86.19 seconds
Started Aug 27 01:42:43 PM UTC 24
Finished Aug 27 01:44:12 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194615705 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1194615705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2267973555
Short name T37
Test name
Test status
Simulation time 11408894228 ps
CPU time 132.68 seconds
Started Aug 27 01:42:42 PM UTC 24
Finished Aug 27 01:45:10 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267973555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2267973555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_smoke.4046438504
Short name T9
Test name
Test status
Simulation time 833466363 ps
CPU time 16.23 seconds
Started Aug 27 01:42:42 PM UTC 24
Finished Aug 27 01:43:12 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046438504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4046438504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_stress_all.4209249983
Short name T72
Test name
Test status
Simulation time 20339585319 ps
CPU time 334.39 seconds
Started Aug 27 01:42:53 PM UTC 24
Finished Aug 27 01:48:33 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209249983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4209249983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_stress_all_with_rand_reset.984333594
Short name T15
Test name
Test status
Simulation time 8076877666 ps
CPU time 191.51 seconds
Started Aug 27 01:42:53 PM UTC 24
Finished Aug 27 01:46:08 PM UTC 24
Peak memory 633068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98433359
4 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.984333594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.120320070
Short name T63
Test name
Test status
Simulation time 1207143871 ps
CPU time 39.28 seconds
Started Aug 27 01:42:45 PM UTC 24
Finished Aug 27 01:43:33 PM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120320070 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.120320070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2602223682
Short name T78
Test name
Test status
Simulation time 2975130104 ps
CPU time 85.99 seconds
Started Aug 27 01:42:48 PM UTC 24
Finished Aug 27 01:44:17 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602223682 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2602223682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.2965934666
Short name T165
Test name
Test status
Simulation time 14578623506 ps
CPU time 116.42 seconds
Started Aug 27 01:42:51 PM UTC 24
Finished Aug 27 01:44:49 PM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965934666 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2965934666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.3929962943
Short name T260
Test name
Test status
Simulation time 41235902008 ps
CPU time 680.15 seconds
Started Aug 27 01:42:43 PM UTC 24
Finished Aug 27 01:54:13 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929962943 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3929962943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.258118307
Short name T485
Test name
Test status
Simulation time 167402645985 ps
CPU time 2150.44 seconds
Started Aug 27 01:42:43 PM UTC 24
Finished Aug 27 02:18:57 PM UTC 24
Peak memory 223492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258118307 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.258118307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.776456462
Short name T503
Test name
Test status
Simulation time 1018725757509 ps
CPU time 2760.69 seconds
Started Aug 27 01:42:44 PM UTC 24
Finished Aug 27 02:29:16 PM UTC 24
Peak memory 227532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776456462 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.776456462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.3463105761
Short name T6
Test name
Test status
Simulation time 1422335340 ps
CPU time 12.96 seconds
Started Aug 27 01:42:43 PM UTC 24
Finished Aug 27 01:42:58 PM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463105761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3463105761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_alert_test.809435026
Short name T183
Test name
Test status
Simulation time 12476901 ps
CPU time 0.84 seconds
Started Aug 27 01:47:07 PM UTC 24
Finished Aug 27 01:47:09 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809435026 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.809435026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.974195012
Short name T185
Test name
Test status
Simulation time 3126899522 ps
CPU time 49.03 seconds
Started Aug 27 01:46:45 PM UTC 24
Finished Aug 27 01:47:35 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974195012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.974195012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.1487311640
Short name T181
Test name
Test status
Simulation time 2917055693 ps
CPU time 8.43 seconds
Started Aug 27 01:46:54 PM UTC 24
Finished Aug 27 01:47:03 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487311640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1487311640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.4175655914
Short name T209
Test name
Test status
Simulation time 3411272880 ps
CPU time 217.06 seconds
Started Aug 27 01:46:49 PM UTC 24
Finished Aug 27 01:50:29 PM UTC 24
Peak memory 463096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175655914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4175655914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_error.4074473723
Short name T192
Test name
Test status
Simulation time 4009745945 ps
CPU time 79.24 seconds
Started Aug 27 01:46:57 PM UTC 24
Finished Aug 27 01:48:19 PM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074473723 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4074473723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_long_msg.252977952
Short name T200
Test name
Test status
Simulation time 30109000746 ps
CPU time 161.72 seconds
Started Aug 27 01:46:41 PM UTC 24
Finished Aug 27 01:49:25 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252977952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.252977952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_smoke.333109423
Short name T178
Test name
Test status
Simulation time 66054991 ps
CPU time 3.73 seconds
Started Aug 27 01:46:39 PM UTC 24
Finished Aug 27 01:46:44 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333109423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.333109423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_stress_all.1434414933
Short name T131
Test name
Test status
Simulation time 124207829415 ps
CPU time 589.78 seconds
Started Aug 27 01:47:05 PM UTC 24
Finished Aug 27 01:57:02 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434414933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1434414933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.663120242
Short name T125
Test name
Test status
Simulation time 1059380672 ps
CPU time 62.21 seconds
Started Aug 27 01:47:02 PM UTC 24
Finished Aug 27 01:48:06 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663120242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.663120242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_alert_test.3160097200
Short name T189
Test name
Test status
Simulation time 26437962 ps
CPU time 0.91 seconds
Started Aug 27 01:48:01 PM UTC 24
Finished Aug 27 01:48:03 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160097200 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3160097200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.2789543544
Short name T190
Test name
Test status
Simulation time 1326093117 ps
CPU time 49.02 seconds
Started Aug 27 01:47:18 PM UTC 24
Finished Aug 27 01:48:09 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789543544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2789543544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.283339068
Short name T153
Test name
Test status
Simulation time 1519969331 ps
CPU time 22.32 seconds
Started Aug 27 01:47:37 PM UTC 24
Finished Aug 27 01:48:00 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283339068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.283339068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.2365505334
Short name T464
Test name
Test status
Simulation time 32117328669 ps
CPU time 1672.83 seconds
Started Aug 27 01:47:24 PM UTC 24
Finished Aug 27 02:15:34 PM UTC 24
Peak memory 784748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365505334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2365505334
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_error.1839695463
Short name T204
Test name
Test status
Simulation time 8934968986 ps
CPU time 129.69 seconds
Started Aug 27 01:47:41 PM UTC 24
Finished Aug 27 01:49:53 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839695463 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1839695463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_long_msg.1060337126
Short name T195
Test name
Test status
Simulation time 2652361367 ps
CPU time 93.4 seconds
Started Aug 27 01:47:10 PM UTC 24
Finished Aug 27 01:48:46 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060337126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1060337126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_smoke.878333656
Short name T148
Test name
Test status
Simulation time 1455160899 ps
CPU time 11.98 seconds
Started Aug 27 01:47:10 PM UTC 24
Finished Aug 27 01:47:24 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878333656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.878333656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_stress_all.320448281
Short name T130
Test name
Test status
Simulation time 16911722743 ps
CPU time 202.81 seconds
Started Aug 27 01:47:49 PM UTC 24
Finished Aug 27 01:51:15 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320448281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.320448281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.2093514077
Short name T128
Test name
Test status
Simulation time 2311213065 ps
CPU time 113.09 seconds
Started Aug 27 01:47:43 PM UTC 24
Finished Aug 27 01:49:39 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093514077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2093514077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_alert_test.3196195294
Short name T194
Test name
Test status
Simulation time 24779958 ps
CPU time 0.87 seconds
Started Aug 27 01:48:42 PM UTC 24
Finished Aug 27 01:48:44 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196195294 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3196195294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.922898553
Short name T196
Test name
Test status
Simulation time 518526769 ps
CPU time 38.03 seconds
Started Aug 27 01:48:10 PM UTC 24
Finished Aug 27 01:48:50 PM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922898553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.922898553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.1762308411
Short name T158
Test name
Test status
Simulation time 389200874 ps
CPU time 23.57 seconds
Started Aug 27 01:48:20 PM UTC 24
Finished Aug 27 01:48:44 PM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762308411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1762308411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.3755602957
Short name T229
Test name
Test status
Simulation time 2829010149 ps
CPU time 220.76 seconds
Started Aug 27 01:48:15 PM UTC 24
Finished Aug 27 01:51:59 PM UTC 24
Peak memory 465240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755602957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3755602957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_error.1637134299
Short name T219
Test name
Test status
Simulation time 42431988672 ps
CPU time 169.74 seconds
Started Aug 27 01:48:20 PM UTC 24
Finished Aug 27 01:51:12 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637134299 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1637134299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2383068019
Short name T215
Test name
Test status
Simulation time 9434794455 ps
CPU time 168.62 seconds
Started Aug 27 01:48:07 PM UTC 24
Finished Aug 27 01:50:58 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383068019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2383068019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_smoke.4090146020
Short name T193
Test name
Test status
Simulation time 705896787 ps
CPU time 13.91 seconds
Started Aug 27 01:48:04 PM UTC 24
Finished Aug 27 01:48:19 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090146020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4090146020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_stress_all.3667616312
Short name T494
Test name
Test status
Simulation time 41212135624 ps
CPU time 2074.78 seconds
Started Aug 27 01:48:36 PM UTC 24
Finished Aug 27 02:23:31 PM UTC 24
Peak memory 825640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667616312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3667616312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.4179733205
Short name T210
Test name
Test status
Simulation time 26808244504 ps
CPU time 124.91 seconds
Started Aug 27 01:48:23 PM UTC 24
Finished Aug 27 01:50:31 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179733205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.4179733205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_alert_test.58175263
Short name T199
Test name
Test status
Simulation time 17304085 ps
CPU time 0.74 seconds
Started Aug 27 01:49:21 PM UTC 24
Finished Aug 27 01:49:23 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58175263 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.58175263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.2766366895
Short name T198
Test name
Test status
Simulation time 455686419 ps
CPU time 31.92 seconds
Started Aug 27 01:48:46 PM UTC 24
Finished Aug 27 01:49:20 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766366895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2766366895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.3363635141
Short name T284
Test name
Test status
Simulation time 10698318559 ps
CPU time 471.89 seconds
Started Aug 27 01:48:48 PM UTC 24
Finished Aug 27 01:56:46 PM UTC 24
Peak memory 454880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363635141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3363635141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_error.306770573
Short name T234
Test name
Test status
Simulation time 94139754716 ps
CPU time 199.01 seconds
Started Aug 27 01:48:51 PM UTC 24
Finished Aug 27 01:52:13 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306770573 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.306770573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_long_msg.1012605255
Short name T214
Test name
Test status
Simulation time 35071028837 ps
CPU time 128.6 seconds
Started Aug 27 01:48:46 PM UTC 24
Finished Aug 27 01:50:57 PM UTC 24
Peak memory 207584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012605255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1012605255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_smoke.2554398653
Short name T197
Test name
Test status
Simulation time 408026325 ps
CPU time 7.01 seconds
Started Aug 27 01:48:46 PM UTC 24
Finished Aug 27 01:48:55 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554398653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2554398653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_stress_all.3665755876
Short name T221
Test name
Test status
Simulation time 6755757600 ps
CPU time 138.08 seconds
Started Aug 27 01:48:56 PM UTC 24
Finished Aug 27 01:51:16 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665755876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3665755876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2486558787
Short name T201
Test name
Test status
Simulation time 2654965424 ps
CPU time 30.36 seconds
Started Aug 27 01:48:53 PM UTC 24
Finished Aug 27 01:49:25 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486558787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2486558787
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_alert_test.1114516209
Short name T205
Test name
Test status
Simulation time 33485582 ps
CPU time 0.84 seconds
Started Aug 27 01:49:52 PM UTC 24
Finished Aug 27 01:49:53 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114516209 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1114516209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.982856513
Short name T31
Test name
Test status
Simulation time 982181330 ps
CPU time 49.09 seconds
Started Aug 27 01:49:28 PM UTC 24
Finished Aug 27 01:50:18 PM UTC 24
Peak memory 206564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982856513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.982856513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.2093357178
Short name T208
Test name
Test status
Simulation time 2641311958 ps
CPU time 36.41 seconds
Started Aug 27 01:49:28 PM UTC 24
Finished Aug 27 01:50:06 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093357178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2093357178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.4234577837
Short name T311
Test name
Test status
Simulation time 2884422539 ps
CPU time 614.53 seconds
Started Aug 27 01:49:28 PM UTC 24
Finished Aug 27 01:59:50 PM UTC 24
Peak memory 695948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234577837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4234577837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_error.479622767
Short name T223
Test name
Test status
Simulation time 10151765170 ps
CPU time 106.82 seconds
Started Aug 27 01:49:32 PM UTC 24
Finished Aug 27 01:51:21 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479622767 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.479622767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_long_msg.750279054
Short name T235
Test name
Test status
Simulation time 10232580706 ps
CPU time 166.38 seconds
Started Aug 27 01:49:24 PM UTC 24
Finished Aug 27 01:52:14 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750279054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.750279054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_smoke.4038005754
Short name T202
Test name
Test status
Simulation time 64021995 ps
CPU time 4.75 seconds
Started Aug 27 01:49:24 PM UTC 24
Finished Aug 27 01:49:31 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038005754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4038005754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_stress_all.3808588680
Short name T372
Test name
Test status
Simulation time 377601699601 ps
CPU time 881.38 seconds
Started Aug 27 01:49:48 PM UTC 24
Finished Aug 27 02:04:41 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808588680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3808588680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.2508525017
Short name T222
Test name
Test status
Simulation time 5910325694 ps
CPU time 95.76 seconds
Started Aug 27 01:49:41 PM UTC 24
Finished Aug 27 01:51:18 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508525017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2508525017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_alert_test.3142075337
Short name T211
Test name
Test status
Simulation time 78496986 ps
CPU time 0.83 seconds
Started Aug 27 01:50:31 PM UTC 24
Finished Aug 27 01:50:32 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142075337 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3142075337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.3918291056
Short name T212
Test name
Test status
Simulation time 985092486 ps
CPU time 35.23 seconds
Started Aug 27 01:50:00 PM UTC 24
Finished Aug 27 01:50:37 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918291056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3918291056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.3599045639
Short name T227
Test name
Test status
Simulation time 6339574050 ps
CPU time 85.15 seconds
Started Aug 27 01:50:06 PM UTC 24
Finished Aug 27 01:51:33 PM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599045639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3599045639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2362769481
Short name T384
Test name
Test status
Simulation time 10176603249 ps
CPU time 929.09 seconds
Started Aug 27 01:50:00 PM UTC 24
Finished Aug 27 02:05:40 PM UTC 24
Peak memory 756016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362769481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2362769481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_error.3485307436
Short name T238
Test name
Test status
Simulation time 33766288558 ps
CPU time 129.83 seconds
Started Aug 27 01:50:07 PM UTC 24
Finished Aug 27 01:52:20 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485307436 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3485307436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_long_msg.3250179823
Short name T217
Test name
Test status
Simulation time 4854849204 ps
CPU time 63.73 seconds
Started Aug 27 01:49:54 PM UTC 24
Finished Aug 27 01:51:00 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250179823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3250179823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_smoke.1401853614
Short name T207
Test name
Test status
Simulation time 116619421 ps
CPU time 3.7 seconds
Started Aug 27 01:49:54 PM UTC 24
Finished Aug 27 01:49:59 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401853614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1401853614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_stress_all.1866077650
Short name T515
Test name
Test status
Simulation time 256678833532 ps
CPU time 3024.54 seconds
Started Aug 27 01:50:22 PM UTC 24
Finished Aug 27 02:41:16 PM UTC 24
Peak memory 835772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866077650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1866077650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.189645904
Short name T239
Test name
Test status
Simulation time 22099294629 ps
CPU time 118.76 seconds
Started Aug 27 01:50:20 PM UTC 24
Finished Aug 27 01:52:22 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189645904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.189645904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_alert_test.2665394548
Short name T218
Test name
Test status
Simulation time 28572974 ps
CPU time 0.86 seconds
Started Aug 27 01:51:01 PM UTC 24
Finished Aug 27 01:51:03 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665394548 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2665394548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.3518918366
Short name T224
Test name
Test status
Simulation time 1455550415 ps
CPU time 43.45 seconds
Started Aug 27 01:50:38 PM UTC 24
Finished Aug 27 01:51:23 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518918366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3518918366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.851561865
Short name T225
Test name
Test status
Simulation time 1920274077 ps
CPU time 34.44 seconds
Started Aug 27 01:50:52 PM UTC 24
Finished Aug 27 01:51:28 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851561865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.851561865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.4089910916
Short name T387
Test name
Test status
Simulation time 4998068519 ps
CPU time 899.42 seconds
Started Aug 27 01:50:47 PM UTC 24
Finished Aug 27 02:05:55 PM UTC 24
Peak memory 762136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089910916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4089910916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_error.2892375609
Short name T230
Test name
Test status
Simulation time 5938356917 ps
CPU time 58.31 seconds
Started Aug 27 01:51:01 PM UTC 24
Finished Aug 27 01:52:01 PM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892375609 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2892375609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_long_msg.4124295542
Short name T231
Test name
Test status
Simulation time 27470300018 ps
CPU time 89.37 seconds
Started Aug 27 01:50:33 PM UTC 24
Finished Aug 27 01:52:05 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124295542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4124295542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_smoke.3423998183
Short name T213
Test name
Test status
Simulation time 1938719102 ps
CPU time 12 seconds
Started Aug 27 01:50:32 PM UTC 24
Finished Aug 27 01:50:46 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423998183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3423998183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2809775762
Short name T86
Test name
Test status
Simulation time 574864211369 ps
CPU time 3712.03 seconds
Started Aug 27 01:51:01 PM UTC 24
Finished Aug 27 02:53:28 PM UTC 24
Peak memory 839924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809775762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2809775762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2694022087
Short name T232
Test name
Test status
Simulation time 1256706088 ps
CPU time 62.87 seconds
Started Aug 27 01:51:01 PM UTC 24
Finished Aug 27 01:52:06 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694022087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2694022087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_alert_test.1984246911
Short name T226
Test name
Test status
Simulation time 15398122 ps
CPU time 0.86 seconds
Started Aug 27 01:51:29 PM UTC 24
Finished Aug 27 01:51:31 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984246911 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1984246911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.3290533257
Short name T237
Test name
Test status
Simulation time 891213278 ps
CPU time 59.54 seconds
Started Aug 27 01:51:17 PM UTC 24
Finished Aug 27 01:52:18 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290533257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3290533257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.3403833831
Short name T233
Test name
Test status
Simulation time 2823892404 ps
CPU time 53.26 seconds
Started Aug 27 01:51:17 PM UTC 24
Finished Aug 27 01:52:12 PM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403833831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3403833831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.719900092
Short name T342
Test name
Test status
Simulation time 4896542645 ps
CPU time 630.96 seconds
Started Aug 27 01:51:17 PM UTC 24
Finished Aug 27 02:01:54 PM UTC 24
Peak memory 749988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719900092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.719900092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_error.350218451
Short name T267
Test name
Test status
Simulation time 26798368444 ps
CPU time 260.26 seconds
Started Aug 27 01:51:20 PM UTC 24
Finished Aug 27 01:55:44 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350218451 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.350218451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_long_msg.3118533408
Short name T240
Test name
Test status
Simulation time 6534285333 ps
CPU time 65.95 seconds
Started Aug 27 01:51:14 PM UTC 24
Finished Aug 27 01:52:22 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118533408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3118533408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_smoke.3990193581
Short name T220
Test name
Test status
Simulation time 543153285 ps
CPU time 8.82 seconds
Started Aug 27 01:51:04 PM UTC 24
Finished Aug 27 01:51:14 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990193581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3990193581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_stress_all.331886593
Short name T129
Test name
Test status
Simulation time 4562971458 ps
CPU time 37.31 seconds
Started Aug 27 01:51:24 PM UTC 24
Finished Aug 27 01:52:02 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331886593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.331886593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.1963288269
Short name T252
Test name
Test status
Simulation time 6346893832 ps
CPU time 128.04 seconds
Started Aug 27 01:51:22 PM UTC 24
Finished Aug 27 01:53:33 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963288269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1963288269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_alert_test.2185943739
Short name T236
Test name
Test status
Simulation time 12464710 ps
CPU time 0.91 seconds
Started Aug 27 01:52:13 PM UTC 24
Finished Aug 27 01:52:15 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185943739 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2185943739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.878798812
Short name T249
Test name
Test status
Simulation time 1342832506 ps
CPU time 92.33 seconds
Started Aug 27 01:51:43 PM UTC 24
Finished Aug 27 01:53:18 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878798812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.878798812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.1536443138
Short name T245
Test name
Test status
Simulation time 16345363590 ps
CPU time 40.5 seconds
Started Aug 27 01:52:02 PM UTC 24
Finished Aug 27 01:52:45 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536443138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1536443138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.3213522010
Short name T292
Test name
Test status
Simulation time 27508193641 ps
CPU time 343.03 seconds
Started Aug 27 01:52:00 PM UTC 24
Finished Aug 27 01:57:48 PM UTC 24
Peak memory 676136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213522010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3213522010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_error.3846957660
Short name T253
Test name
Test status
Simulation time 1389914914 ps
CPU time 87.46 seconds
Started Aug 27 01:52:03 PM UTC 24
Finished Aug 27 01:53:33 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846957660 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3846957660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_long_msg.3740648643
Short name T46
Test name
Test status
Simulation time 46934596873 ps
CPU time 181.2 seconds
Started Aug 27 01:51:34 PM UTC 24
Finished Aug 27 01:54:38 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740648643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3740648643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_smoke.1242660372
Short name T228
Test name
Test status
Simulation time 299384574 ps
CPU time 9.45 seconds
Started Aug 27 01:51:32 PM UTC 24
Finished Aug 27 01:51:43 PM UTC 24
Peak memory 207424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242660372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1242660372
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_stress_all.1434409745
Short name T91
Test name
Test status
Simulation time 16679509332 ps
CPU time 187.39 seconds
Started Aug 27 01:52:07 PM UTC 24
Finished Aug 27 01:55:17 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434409745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1434409745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.3446820808
Short name T258
Test name
Test status
Simulation time 14277974800 ps
CPU time 116.02 seconds
Started Aug 27 01:52:07 PM UTC 24
Finished Aug 27 01:54:05 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446820808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3446820808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_alert_test.3572567540
Short name T243
Test name
Test status
Simulation time 18541114 ps
CPU time 0.85 seconds
Started Aug 27 01:52:39 PM UTC 24
Finished Aug 27 01:52:41 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572567540 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3572567540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.4171677801
Short name T247
Test name
Test status
Simulation time 712338446 ps
CPU time 38.93 seconds
Started Aug 27 01:52:16 PM UTC 24
Finished Aug 27 01:52:56 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171677801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4171677801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.679010155
Short name T242
Test name
Test status
Simulation time 770990058 ps
CPU time 16.34 seconds
Started Aug 27 01:52:21 PM UTC 24
Finished Aug 27 01:52:38 PM UTC 24
Peak memory 207372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679010155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.679010155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3591870739
Short name T306
Test name
Test status
Simulation time 15758445308 ps
CPU time 367.79 seconds
Started Aug 27 01:52:19 PM UTC 24
Finished Aug 27 01:58:32 PM UTC 24
Peak memory 653660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591870739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3591870739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_error.2556427120
Short name T254
Test name
Test status
Simulation time 4842101758 ps
CPU time 72.48 seconds
Started Aug 27 01:52:23 PM UTC 24
Finished Aug 27 01:53:37 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556427120 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2556427120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_long_msg.2701626284
Short name T263
Test name
Test status
Simulation time 8997980907 ps
CPU time 127.86 seconds
Started Aug 27 01:52:16 PM UTC 24
Finished Aug 27 01:54:26 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701626284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2701626284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_smoke.2726684790
Short name T241
Test name
Test status
Simulation time 2022732780 ps
CPU time 11.02 seconds
Started Aug 27 01:52:16 PM UTC 24
Finished Aug 27 01:52:28 PM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726684790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2726684790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_stress_all.921075027
Short name T81
Test name
Test status
Simulation time 34131944808 ps
CPU time 440.59 seconds
Started Aug 27 01:52:29 PM UTC 24
Finished Aug 27 01:59:55 PM UTC 24
Peak memory 680160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921075027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.921075027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.2006256780
Short name T51
Test name
Test status
Simulation time 9890461333 ps
CPU time 143.83 seconds
Started Aug 27 01:52:23 PM UTC 24
Finished Aug 27 01:54:49 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006256780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2006256780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2556793567
Short name T21
Test name
Test status
Simulation time 29944632 ps
CPU time 0.87 seconds
Started Aug 27 01:42:59 PM UTC 24
Finished Aug 27 01:43:01 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556793567 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2556793567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.3737781280
Short name T11
Test name
Test status
Simulation time 760709721 ps
CPU time 8.94 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:43:05 PM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737781280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3737781280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.974382424
Short name T25
Test name
Test status
Simulation time 3746829511 ps
CPU time 24.96 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:43:21 PM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974382424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.974382424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.2025138769
Short name T359
Test name
Test status
Simulation time 6424854406 ps
CPU time 1214.8 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 02:03:22 PM UTC 24
Peak memory 755556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025138769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2025138769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_long_msg.1880373589
Short name T121
Test name
Test status
Simulation time 15490038602 ps
CPU time 59.2 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:43:56 PM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880373589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1880373589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.3039791179
Short name T66
Test name
Test status
Simulation time 168552608 ps
CPU time 1.51 seconds
Started Aug 27 01:42:57 PM UTC 24
Finished Aug 27 01:43:02 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039791179 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3039791179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_smoke.81285443
Short name T4
Test name
Test status
Simulation time 27805390 ps
CPU time 1.04 seconds
Started Aug 27 01:42:54 PM UTC 24
Finished Aug 27 01:42:56 PM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81285443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.hmac_smoke.81285443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_stress_all.2936598021
Short name T127
Test name
Test status
Simulation time 140185753265 ps
CPU time 346.99 seconds
Started Aug 27 01:42:57 PM UTC 24
Finished Aug 27 01:48:51 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936598021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2936598021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.4001781417
Short name T79
Test name
Test status
Simulation time 6250859416 ps
CPU time 85.99 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:44:26 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001781417 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.4001781417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.1590059904
Short name T64
Test name
Test status
Simulation time 5316331797 ps
CPU time 82.67 seconds
Started Aug 27 01:42:56 PM UTC 24
Finished Aug 27 01:44:24 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590059904 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1590059904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.651989955
Short name T39
Test name
Test status
Simulation time 8864826860 ps
CPU time 141.23 seconds
Started Aug 27 01:42:57 PM UTC 24
Finished Aug 27 01:45:23 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651989955 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.651989955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.1497442358
Short name T47
Test name
Test status
Simulation time 197812711877 ps
CPU time 694.6 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:54:38 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497442358 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1497442358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1734553406
Short name T493
Test name
Test status
Simulation time 593269286945 ps
CPU time 2399.95 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 02:23:21 PM UTC 24
Peak memory 227232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734553406 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1734553406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.271168682
Short name T504
Test name
Test status
Simulation time 402665483888 ps
CPU time 2778.41 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 02:29:45 PM UTC 24
Peak memory 227384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271168682 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.271168682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.2698128187
Short name T33
Test name
Test status
Simulation time 4701371104 ps
CPU time 45.42 seconds
Started Aug 27 01:42:55 PM UTC 24
Finished Aug 27 01:43:42 PM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698128187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2698128187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_alert_test.1336955836
Short name T250
Test name
Test status
Simulation time 20574081 ps
CPU time 0.81 seconds
Started Aug 27 01:53:24 PM UTC 24
Finished Aug 27 01:53:26 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336955836 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1336955836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.965117803
Short name T251
Test name
Test status
Simulation time 7297416059 ps
CPU time 43.51 seconds
Started Aug 27 01:52:48 PM UTC 24
Finished Aug 27 01:53:33 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965117803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.965117803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.1089554738
Short name T151
Test name
Test status
Simulation time 919914374 ps
CPU time 47.23 seconds
Started Aug 27 01:52:51 PM UTC 24
Finished Aug 27 01:53:40 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089554738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1089554738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2258089380
Short name T352
Test name
Test status
Simulation time 3444434143 ps
CPU time 583.69 seconds
Started Aug 27 01:52:51 PM UTC 24
Finished Aug 27 02:02:40 PM UTC 24
Peak memory 764188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258089380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2258089380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_error.4067063184
Short name T52
Test name
Test status
Simulation time 29328255379 ps
CPU time 111.66 seconds
Started Aug 27 01:52:58 PM UTC 24
Finished Aug 27 01:54:51 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067063184 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4067063184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_long_msg.4051821215
Short name T279
Test name
Test status
Simulation time 64750251473 ps
CPU time 219.67 seconds
Started Aug 27 01:52:47 PM UTC 24
Finished Aug 27 01:56:30 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051821215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4051821215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_smoke.1161162932
Short name T248
Test name
Test status
Simulation time 1070571756 ps
CPU time 13.55 seconds
Started Aug 27 01:52:42 PM UTC 24
Finished Aug 27 01:52:57 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161162932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1161162932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_stress_all.362289825
Short name T415
Test name
Test status
Simulation time 83571257072 ps
CPU time 968.69 seconds
Started Aug 27 01:53:19 PM UTC 24
Finished Aug 27 02:09:40 PM UTC 24
Peak memory 215756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362289825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.362289825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3584572956
Short name T50
Test name
Test status
Simulation time 1978414624 ps
CPU time 108.34 seconds
Started Aug 27 01:52:58 PM UTC 24
Finished Aug 27 01:54:48 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584572956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3584572956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2094153628
Short name T259
Test name
Test status
Simulation time 28371554 ps
CPU time 0.88 seconds
Started Aug 27 01:54:07 PM UTC 24
Finished Aug 27 01:54:08 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094153628 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2094153628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.1181192355
Short name T48
Test name
Test status
Simulation time 2977463384 ps
CPU time 66.22 seconds
Started Aug 27 01:53:36 PM UTC 24
Finished Aug 27 01:54:43 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181192355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1181192355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.1505032516
Short name T264
Test name
Test status
Simulation time 4701028698 ps
CPU time 55.48 seconds
Started Aug 27 01:53:38 PM UTC 24
Finished Aug 27 01:54:35 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505032516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1505032516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.4033629375
Short name T371
Test name
Test status
Simulation time 4086395466 ps
CPU time 650.17 seconds
Started Aug 27 01:53:36 PM UTC 24
Finished Aug 27 02:04:33 PM UTC 24
Peak memory 692504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033629375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4033629375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_error.3177030170
Short name T257
Test name
Test status
Simulation time 3667455467 ps
CPU time 23.22 seconds
Started Aug 27 01:53:40 PM UTC 24
Finished Aug 27 01:54:05 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177030170 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3177030170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_long_msg.1259055549
Short name T276
Test name
Test status
Simulation time 163954841781 ps
CPU time 163.2 seconds
Started Aug 27 01:53:35 PM UTC 24
Finished Aug 27 01:56:21 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259055549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1259055549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_smoke.3968651870
Short name T255
Test name
Test status
Simulation time 252397291 ps
CPU time 14.43 seconds
Started Aug 27 01:53:27 PM UTC 24
Finished Aug 27 01:53:42 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968651870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3968651870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_stress_all.3183906889
Short name T511
Test name
Test status
Simulation time 18220039245 ps
CPU time 2421.74 seconds
Started Aug 27 01:54:06 PM UTC 24
Finished Aug 27 02:34:52 PM UTC 24
Peak memory 833776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183906889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3183906889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.2372599094
Short name T265
Test name
Test status
Simulation time 13750659813 ps
CPU time 104.82 seconds
Started Aug 27 01:53:43 PM UTC 24
Finished Aug 27 01:55:30 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372599094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2372599094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_alert_test.775762229
Short name T49
Test name
Test status
Simulation time 15156853 ps
CPU time 0.88 seconds
Started Aug 27 01:54:43 PM UTC 24
Finished Aug 27 01:54:45 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775762229 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.775762229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.1086062621
Short name T88
Test name
Test status
Simulation time 2150779467 ps
CPU time 36.51 seconds
Started Aug 27 01:54:25 PM UTC 24
Finished Aug 27 01:55:03 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086062621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1086062621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.102817149
Short name T268
Test name
Test status
Simulation time 814723029 ps
CPU time 89.03 seconds
Started Aug 27 01:54:23 PM UTC 24
Finished Aug 27 01:55:54 PM UTC 24
Peak memory 430304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102817149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.102817149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_error.3117053547
Short name T53
Test name
Test status
Simulation time 11466100820 ps
CPU time 23.38 seconds
Started Aug 27 01:54:27 PM UTC 24
Finished Aug 27 01:54:52 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117053547 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3117053547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_long_msg.3957633999
Short name T288
Test name
Test status
Simulation time 2599465037 ps
CPU time 167.85 seconds
Started Aug 27 01:54:09 PM UTC 24
Finished Aug 27 01:56:59 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957633999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3957633999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_smoke.1875389829
Short name T262
Test name
Test status
Simulation time 4448394304 ps
CPU time 16.11 seconds
Started Aug 27 01:54:07 PM UTC 24
Finished Aug 27 01:54:24 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875389829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1875389829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_stress_all.4154783386
Short name T516
Test name
Test status
Simulation time 86302003862 ps
CPU time 2941.82 seconds
Started Aug 27 01:54:37 PM UTC 24
Finished Aug 27 02:44:08 PM UTC 24
Peak memory 794916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154783386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4154783386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.428603259
Short name T93
Test name
Test status
Simulation time 4885017298 ps
CPU time 59.63 seconds
Started Aug 27 01:54:36 PM UTC 24
Finished Aug 27 01:55:38 PM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428603259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.428603259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_alert_test.259012904
Short name T89
Test name
Test status
Simulation time 40247494 ps
CPU time 0.87 seconds
Started Aug 27 01:55:04 PM UTC 24
Finished Aug 27 01:55:06 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259012904 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.259012904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.3376951577
Short name T269
Test name
Test status
Simulation time 6083568845 ps
CPU time 67.68 seconds
Started Aug 27 01:54:45 PM UTC 24
Finished Aug 27 01:55:55 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376951577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3376951577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.1599966242
Short name T90
Test name
Test status
Simulation time 1001304496 ps
CPU time 15.35 seconds
Started Aug 27 01:54:51 PM UTC 24
Finished Aug 27 01:55:07 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599966242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1599966242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.1411195611
Short name T439
Test name
Test status
Simulation time 5889953114 ps
CPU time 1037.26 seconds
Started Aug 27 01:54:49 PM UTC 24
Finished Aug 27 02:12:17 PM UTC 24
Peak memory 721252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411195611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1411195611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_error.1883504312
Short name T308
Test name
Test status
Simulation time 59727032526 ps
CPU time 252.28 seconds
Started Aug 27 01:54:53 PM UTC 24
Finished Aug 27 01:59:09 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883504312 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1883504312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_long_msg.4052858547
Short name T283
Test name
Test status
Simulation time 32936970067 ps
CPU time 115.59 seconds
Started Aug 27 01:54:44 PM UTC 24
Finished Aug 27 01:56:42 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052858547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4052858547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_smoke.1141160799
Short name T54
Test name
Test status
Simulation time 797033733 ps
CPU time 13.97 seconds
Started Aug 27 01:54:43 PM UTC 24
Finished Aug 27 01:54:58 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141160799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1141160799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_stress_all.32170831
Short name T519
Test name
Test status
Simulation time 49203405629 ps
CPU time 3056.18 seconds
Started Aug 27 01:54:59 PM UTC 24
Finished Aug 27 02:46:25 PM UTC 24
Peak memory 821492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32170831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.32170831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3018210069
Short name T275
Test name
Test status
Simulation time 6891863207 ps
CPU time 79.76 seconds
Started Aug 27 01:54:53 PM UTC 24
Finished Aug 27 01:56:14 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018210069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3018210069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_alert_test.3234519470
Short name T271
Test name
Test status
Simulation time 13672952 ps
CPU time 0.84 seconds
Started Aug 27 01:55:55 PM UTC 24
Finished Aug 27 01:55:57 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234519470 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3234519470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.1962098858
Short name T274
Test name
Test status
Simulation time 708431534 ps
CPU time 53.2 seconds
Started Aug 27 01:55:19 PM UTC 24
Finished Aug 27 01:56:13 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962098858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1962098858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.3061820456
Short name T155
Test name
Test status
Simulation time 780342832 ps
CPU time 26.97 seconds
Started Aug 27 01:55:32 PM UTC 24
Finished Aug 27 01:56:00 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061820456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3061820456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.28852855
Short name T428
Test name
Test status
Simulation time 5461044328 ps
CPU time 923.24 seconds
Started Aug 27 01:55:20 PM UTC 24
Finished Aug 27 02:10:52 PM UTC 24
Peak memory 778516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28852855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.28852855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_error.800772743
Short name T270
Test name
Test status
Simulation time 230261296 ps
CPU time 16.12 seconds
Started Aug 27 01:55:39 PM UTC 24
Finished Aug 27 01:55:56 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800772743 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.800772743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_long_msg.922637972
Short name T277
Test name
Test status
Simulation time 9156770289 ps
CPU time 73.31 seconds
Started Aug 27 01:55:08 PM UTC 24
Finished Aug 27 01:56:23 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922637972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.922637972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_smoke.4122238780
Short name T92
Test name
Test status
Simulation time 530409863 ps
CPU time 10.56 seconds
Started Aug 27 01:55:07 PM UTC 24
Finished Aug 27 01:55:19 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122238780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.4122238780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_stress_all.4196649945
Short name T495
Test name
Test status
Simulation time 16187428932 ps
CPU time 1699.69 seconds
Started Aug 27 01:55:47 PM UTC 24
Finished Aug 27 02:24:25 PM UTC 24
Peak memory 753896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196649945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4196649945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.3156131513
Short name T298
Test name
Test status
Simulation time 68610510925 ps
CPU time 136.36 seconds
Started Aug 27 01:55:47 PM UTC 24
Finished Aug 27 01:58:06 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156131513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3156131513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_alert_test.1698500414
Short name T278
Test name
Test status
Simulation time 11867110 ps
CPU time 0.89 seconds
Started Aug 27 01:56:23 PM UTC 24
Finished Aug 27 01:56:25 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698500414 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1698500414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.271072645
Short name T282
Test name
Test status
Simulation time 666539578 ps
CPU time 40.48 seconds
Started Aug 27 01:55:58 PM UTC 24
Finished Aug 27 01:56:40 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271072645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.271072645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.3975133691
Short name T285
Test name
Test status
Simulation time 17676984829 ps
CPU time 40.2 seconds
Started Aug 27 01:56:06 PM UTC 24
Finished Aug 27 01:56:48 PM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975133691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3975133691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.3803259111
Short name T286
Test name
Test status
Simulation time 959994630 ps
CPU time 47.18 seconds
Started Aug 27 01:56:01 PM UTC 24
Finished Aug 27 01:56:50 PM UTC 24
Peak memory 252192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803259111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3803259111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_error.1880060588
Short name T304
Test name
Test status
Simulation time 13197244460 ps
CPU time 131.77 seconds
Started Aug 27 01:56:10 PM UTC 24
Finished Aug 27 01:58:25 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880060588 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1880060588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_long_msg.2441523656
Short name T272
Test name
Test status
Simulation time 1665382151 ps
CPU time 6.42 seconds
Started Aug 27 01:55:57 PM UTC 24
Finished Aug 27 01:56:05 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441523656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2441523656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_smoke.137070204
Short name T273
Test name
Test status
Simulation time 1731256802 ps
CPU time 11.37 seconds
Started Aug 27 01:55:57 PM UTC 24
Finished Aug 27 01:56:10 PM UTC 24
Peak memory 207204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137070204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.137070204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_stress_all.3055878641
Short name T522
Test name
Test status
Simulation time 47037635628 ps
CPU time 3264.39 seconds
Started Aug 27 01:56:16 PM UTC 24
Finished Aug 27 02:51:13 PM UTC 24
Peak memory 852236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055878641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3055878641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.3636685080
Short name T300
Test name
Test status
Simulation time 26254117949 ps
CPU time 113.84 seconds
Started Aug 27 01:56:15 PM UTC 24
Finished Aug 27 01:58:11 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636685080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3636685080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_alert_test.4266214002
Short name T287
Test name
Test status
Simulation time 128639182 ps
CPU time 0.87 seconds
Started Aug 27 01:56:49 PM UTC 24
Finished Aug 27 01:56:51 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266214002 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4266214002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.294485281
Short name T291
Test name
Test status
Simulation time 4918697218 ps
CPU time 68.64 seconds
Started Aug 27 01:56:31 PM UTC 24
Finished Aug 27 01:57:42 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294485281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.294485281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.405466069
Short name T289
Test name
Test status
Simulation time 965991048 ps
CPU time 18.83 seconds
Started Aug 27 01:56:42 PM UTC 24
Finished Aug 27 01:57:02 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405466069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.405466069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.630051078
Short name T420
Test name
Test status
Simulation time 15934683073 ps
CPU time 812.74 seconds
Started Aug 27 01:56:34 PM UTC 24
Finished Aug 27 02:10:15 PM UTC 24
Peak memory 741808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630051078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.630051078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_error.1964859550
Short name T321
Test name
Test status
Simulation time 60090434403 ps
CPU time 226.07 seconds
Started Aug 27 01:56:42 PM UTC 24
Finished Aug 27 02:00:32 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964859550 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1964859550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_long_msg.3491502911
Short name T302
Test name
Test status
Simulation time 4042555284 ps
CPU time 104.97 seconds
Started Aug 27 01:56:26 PM UTC 24
Finished Aug 27 01:58:13 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491502911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3491502911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_smoke.3009479649
Short name T280
Test name
Test status
Simulation time 5842685864 ps
CPU time 7.65 seconds
Started Aug 27 01:56:25 PM UTC 24
Finished Aug 27 01:56:34 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009479649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3009479649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_stress_all.2202522450
Short name T509
Test name
Test status
Simulation time 214331889246 ps
CPU time 2104.91 seconds
Started Aug 27 01:56:48 PM UTC 24
Finished Aug 27 02:32:14 PM UTC 24
Peak memory 796956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202522450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2202522450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.3883160601
Short name T301
Test name
Test status
Simulation time 9642684228 ps
CPU time 86.44 seconds
Started Aug 27 01:56:44 PM UTC 24
Finished Aug 27 01:58:12 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883160601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3883160601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_alert_test.1579077726
Short name T294
Test name
Test status
Simulation time 28260305 ps
CPU time 0.92 seconds
Started Aug 27 01:57:54 PM UTC 24
Finished Aug 27 01:57:56 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579077726 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1579077726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.2144519950
Short name T44
Test name
Test status
Simulation time 1585766774 ps
CPU time 88.68 seconds
Started Aug 27 01:57:02 PM UTC 24
Finished Aug 27 01:58:32 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144519950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2144519950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.748059732
Short name T293
Test name
Test status
Simulation time 17987982494 ps
CPU time 46.74 seconds
Started Aug 27 01:57:06 PM UTC 24
Finished Aug 27 01:57:54 PM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748059732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.748059732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.736405995
Short name T368
Test name
Test status
Simulation time 27866961958 ps
CPU time 416.53 seconds
Started Aug 27 01:57:06 PM UTC 24
Finished Aug 27 02:04:07 PM UTC 24
Peak memory 663832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736405995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.736405995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_error.4193391254
Short name T322
Test name
Test status
Simulation time 34340990398 ps
CPU time 195.74 seconds
Started Aug 27 01:57:15 PM UTC 24
Finished Aug 27 02:00:34 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193391254 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4193391254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_long_msg.1596238487
Short name T295
Test name
Test status
Simulation time 3393666651 ps
CPU time 64.79 seconds
Started Aug 27 01:56:51 PM UTC 24
Finished Aug 27 01:57:58 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596238487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1596238487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_smoke.4152786763
Short name T290
Test name
Test status
Simulation time 1075288248 ps
CPU time 21.51 seconds
Started Aug 27 01:56:51 PM UTC 24
Finished Aug 27 01:57:14 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152786763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4152786763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_stress_all.1653049129
Short name T152
Test name
Test status
Simulation time 8426876816 ps
CPU time 488.05 seconds
Started Aug 27 01:57:49 PM UTC 24
Finished Aug 27 02:06:03 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653049129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1653049129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.3936534414
Short name T94
Test name
Test status
Simulation time 35818498673 ps
CPU time 116.96 seconds
Started Aug 27 01:57:44 PM UTC 24
Finished Aug 27 01:59:43 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936534414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3936534414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_alert_test.3536932063
Short name T303
Test name
Test status
Simulation time 13875873 ps
CPU time 0.83 seconds
Started Aug 27 01:58:15 PM UTC 24
Finished Aug 27 01:58:17 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536932063 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3536932063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.3968177023
Short name T299
Test name
Test status
Simulation time 32404875 ps
CPU time 2.49 seconds
Started Aug 27 01:58:04 PM UTC 24
Finished Aug 27 01:58:08 PM UTC 24
Peak memory 207112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968177023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3968177023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.1507177415
Short name T307
Test name
Test status
Simulation time 5869953275 ps
CPU time 31.18 seconds
Started Aug 27 01:58:07 PM UTC 24
Finished Aug 27 01:58:40 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507177415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1507177415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.2409137001
Short name T498
Test name
Test status
Simulation time 8191221452 ps
CPU time 1746.66 seconds
Started Aug 27 01:58:04 PM UTC 24
Finished Aug 27 02:27:28 PM UTC 24
Peak memory 786728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409137001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2409137001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_error.4033492020
Short name T338
Test name
Test status
Simulation time 11114662977 ps
CPU time 212.94 seconds
Started Aug 27 01:58:08 PM UTC 24
Finished Aug 27 02:01:45 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033492020 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4033492020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_long_msg.2666029658
Short name T329
Test name
Test status
Simulation time 20369600387 ps
CPU time 178.25 seconds
Started Aug 27 01:57:59 PM UTC 24
Finished Aug 27 02:01:00 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666029658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2666029658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_smoke.857955232
Short name T297
Test name
Test status
Simulation time 1536712732 ps
CPU time 5.02 seconds
Started Aug 27 01:57:57 PM UTC 24
Finished Aug 27 01:58:04 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857955232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.857955232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_stress_all.3801690653
Short name T478
Test name
Test status
Simulation time 79086869629 ps
CPU time 1121.57 seconds
Started Aug 27 01:58:13 PM UTC 24
Finished Aug 27 02:17:08 PM UTC 24
Peak memory 712932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801690653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3801690653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.201521034
Short name T319
Test name
Test status
Simulation time 8280756504 ps
CPU time 116.38 seconds
Started Aug 27 01:58:13 PM UTC 24
Finished Aug 27 02:00:12 PM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201521034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.201521034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_alert_test.1264619287
Short name T310
Test name
Test status
Simulation time 23466906 ps
CPU time 0.82 seconds
Started Aug 27 01:59:43 PM UTC 24
Finished Aug 27 01:59:45 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264619287 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1264619287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.466508565
Short name T313
Test name
Test status
Simulation time 6734525567 ps
CPU time 86.63 seconds
Started Aug 27 01:58:29 PM UTC 24
Finished Aug 27 01:59:57 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466508565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.466508565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.1757262832
Short name T315
Test name
Test status
Simulation time 13981419242 ps
CPU time 82.59 seconds
Started Aug 27 01:58:34 PM UTC 24
Finished Aug 27 01:59:59 PM UTC 24
Peak memory 215476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757262832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1757262832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.4183089384
Short name T396
Test name
Test status
Simulation time 9870739239 ps
CPU time 506.82 seconds
Started Aug 27 01:58:34 PM UTC 24
Finished Aug 27 02:07:07 PM UTC 24
Peak memory 469292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183089384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4183089384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_error.1168644645
Short name T312
Test name
Test status
Simulation time 13018647697 ps
CPU time 68.44 seconds
Started Aug 27 01:58:40 PM UTC 24
Finished Aug 27 01:59:51 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168644645 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1168644645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_long_msg.2313085209
Short name T314
Test name
Test status
Simulation time 7874427705 ps
CPU time 90.33 seconds
Started Aug 27 01:58:26 PM UTC 24
Finished Aug 27 01:59:58 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313085209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2313085209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_smoke.2278379393
Short name T305
Test name
Test status
Simulation time 2017463433 ps
CPU time 8.57 seconds
Started Aug 27 01:58:18 PM UTC 24
Finished Aug 27 01:58:28 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278379393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2278379393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_stress_all.253059093
Short name T500
Test name
Test status
Simulation time 118887078312 ps
CPU time 1686.6 seconds
Started Aug 27 01:59:31 PM UTC 24
Finished Aug 27 02:27:56 PM UTC 24
Peak memory 741804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253059093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.253059093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.682410929
Short name T309
Test name
Test status
Simulation time 900585802 ps
CPU time 30.33 seconds
Started Aug 27 01:59:11 PM UTC 24
Finished Aug 27 01:59:42 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682410929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.682410929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_alert_test.314944874
Short name T161
Test name
Test status
Simulation time 14231935 ps
CPU time 0.88 seconds
Started Aug 27 01:43:33 PM UTC 24
Finished Aug 27 01:43:35 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314944874 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.314944874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3535172043
Short name T10
Test name
Test status
Simulation time 1966484119 ps
CPU time 27.97 seconds
Started Aug 27 01:43:03 PM UTC 24
Finished Aug 27 01:43:32 PM UTC 24
Peak memory 223840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535172043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3535172043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.2381972276
Short name T332
Test name
Test status
Simulation time 19505905151 ps
CPU time 1073.69 seconds
Started Aug 27 01:43:03 PM UTC 24
Finished Aug 27 02:01:09 PM UTC 24
Peak memory 745888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381972276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2381972276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_error.4007217292
Short name T142
Test name
Test status
Simulation time 36527381748 ps
CPU time 200.8 seconds
Started Aug 27 01:43:04 PM UTC 24
Finished Aug 27 01:46:28 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007217292 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.4007217292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_long_msg.1499780470
Short name T144
Test name
Test status
Simulation time 942245155 ps
CPU time 49.17 seconds
Started Aug 27 01:43:00 PM UTC 24
Finished Aug 27 01:43:51 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499780470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1499780470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2881458070
Short name T67
Test name
Test status
Simulation time 511095264 ps
CPU time 1.73 seconds
Started Aug 27 01:43:29 PM UTC 24
Finished Aug 27 01:43:32 PM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881458070 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2881458070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_stress_all.1419670321
Short name T324
Test name
Test status
Simulation time 56046941769 ps
CPU time 1026.3 seconds
Started Aug 27 01:43:22 PM UTC 24
Finished Aug 27 02:00:39 PM UTC 24
Peak memory 698656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419670321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1419670321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3446617213
Short name T164
Test name
Test status
Simulation time 22502657148 ps
CPU time 96.17 seconds
Started Aug 27 01:43:08 PM UTC 24
Finished Aug 27 01:44:46 PM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446617213 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3446617213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.4113913661
Short name T35
Test name
Test status
Simulation time 6759345498 ps
CPU time 108.33 seconds
Started Aug 27 01:43:13 PM UTC 24
Finished Aug 27 01:45:04 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113913661 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4113913661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.2653199908
Short name T38
Test name
Test status
Simulation time 15278271571 ps
CPU time 117.79 seconds
Started Aug 27 01:43:18 PM UTC 24
Finished Aug 27 01:45:18 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653199908 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2653199908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.2737989293
Short name T244
Test name
Test status
Simulation time 71966762845 ps
CPU time 569.84 seconds
Started Aug 27 01:43:06 PM UTC 24
Finished Aug 27 01:52:43 PM UTC 24
Peak memory 206876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737989293 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2737989293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.3689727114
Short name T502
Test name
Test status
Simulation time 833437880844 ps
CPU time 2684.88 seconds
Started Aug 27 01:43:06 PM UTC 24
Finished Aug 27 02:28:21 PM UTC 24
Peak memory 227648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689727114 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3689727114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.2628290951
Short name T492
Test name
Test status
Simulation time 158444698934 ps
CPU time 2384.25 seconds
Started Aug 27 01:43:07 PM UTC 24
Finished Aug 27 02:23:17 PM UTC 24
Peak memory 227156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628290951 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2628290951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.3116838322
Short name T27
Test name
Test status
Simulation time 5655263688 ps
CPU time 73.52 seconds
Started Aug 27 01:43:05 PM UTC 24
Finished Aug 27 01:44:20 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116838322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3116838322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_alert_test.3375354092
Short name T317
Test name
Test status
Simulation time 14473975 ps
CPU time 0.78 seconds
Started Aug 27 02:00:07 PM UTC 24
Finished Aug 27 02:00:09 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375354092 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3375354092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.2749134999
Short name T327
Test name
Test status
Simulation time 3526453409 ps
CPU time 58.94 seconds
Started Aug 27 01:59:53 PM UTC 24
Finished Aug 27 02:00:53 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749134999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2749134999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.4032707775
Short name T154
Test name
Test status
Simulation time 896530252 ps
CPU time 63.99 seconds
Started Aug 27 01:59:57 PM UTC 24
Finished Aug 27 02:01:03 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032707775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4032707775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.2298246281
Short name T347
Test name
Test status
Simulation time 1036154561 ps
CPU time 150.83 seconds
Started Aug 27 01:59:53 PM UTC 24
Finished Aug 27 02:02:26 PM UTC 24
Peak memory 420196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298246281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2298246281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_error.4205296492
Short name T323
Test name
Test status
Simulation time 2443733324 ps
CPU time 35.77 seconds
Started Aug 27 01:59:59 PM UTC 24
Finished Aug 27 02:00:36 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205296492 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4205296492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_long_msg.1001298827
Short name T349
Test name
Test status
Simulation time 3367540089 ps
CPU time 165.37 seconds
Started Aug 27 01:59:46 PM UTC 24
Finished Aug 27 02:02:34 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001298827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1001298827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_smoke.3227958845
Short name T316
Test name
Test status
Simulation time 1045895110 ps
CPU time 16.46 seconds
Started Aug 27 01:59:45 PM UTC 24
Finished Aug 27 02:00:03 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227958845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3227958845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.3624570814
Short name T95
Test name
Test status
Simulation time 3754447191 ps
CPU time 48.49 seconds
Started Aug 27 01:59:59 PM UTC 24
Finished Aug 27 02:00:49 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624570814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3624570814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_alert_test.4116111187
Short name T326
Test name
Test status
Simulation time 50666574 ps
CPU time 0.88 seconds
Started Aug 27 02:00:51 PM UTC 24
Finished Aug 27 02:00:53 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116111187 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4116111187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.2205119111
Short name T325
Test name
Test status
Simulation time 1042697932 ps
CPU time 33.05 seconds
Started Aug 27 02:00:15 PM UTC 24
Finished Aug 27 02:00:49 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205119111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2205119111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.2768375706
Short name T331
Test name
Test status
Simulation time 4110296240 ps
CPU time 28.37 seconds
Started Aug 27 02:00:33 PM UTC 24
Finished Aug 27 02:01:03 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768375706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2768375706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.2172978346
Short name T497
Test name
Test status
Simulation time 7864612038 ps
CPU time 1602.54 seconds
Started Aug 27 02:00:17 PM UTC 24
Finished Aug 27 02:27:15 PM UTC 24
Peak memory 794984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172978346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2172978346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_error.2727404524
Short name T360
Test name
Test status
Simulation time 25237809310 ps
CPU time 168.64 seconds
Started Aug 27 02:00:35 PM UTC 24
Finished Aug 27 02:03:27 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727404524 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2727404524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_long_msg.3175822319
Short name T328
Test name
Test status
Simulation time 11194558524 ps
CPU time 38.72 seconds
Started Aug 27 02:00:13 PM UTC 24
Finished Aug 27 02:00:53 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175822319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3175822319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_smoke.303740685
Short name T320
Test name
Test status
Simulation time 242149451 ps
CPU time 4.39 seconds
Started Aug 27 02:00:10 PM UTC 24
Finished Aug 27 02:00:16 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303740685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.303740685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_stress_all.1819847093
Short name T461
Test name
Test status
Simulation time 68144193332 ps
CPU time 864.72 seconds
Started Aug 27 02:00:42 PM UTC 24
Finished Aug 27 02:15:16 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819847093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1819847093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.479125227
Short name T345
Test name
Test status
Simulation time 1281493150 ps
CPU time 97.58 seconds
Started Aug 27 02:00:37 PM UTC 24
Finished Aug 27 02:02:17 PM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479125227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.479125227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_alert_test.3344908781
Short name T333
Test name
Test status
Simulation time 19320815 ps
CPU time 0.9 seconds
Started Aug 27 02:01:11 PM UTC 24
Finished Aug 27 02:01:13 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344908781 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3344908781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.1083640454
Short name T337
Test name
Test status
Simulation time 621181199 ps
CPU time 40.07 seconds
Started Aug 27 02:00:55 PM UTC 24
Finished Aug 27 02:01:37 PM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083640454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1083640454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.1396797210
Short name T353
Test name
Test status
Simulation time 15763612916 ps
CPU time 102.72 seconds
Started Aug 27 02:01:02 PM UTC 24
Finished Aug 27 02:02:47 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396797210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1396797210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.1579308780
Short name T462
Test name
Test status
Simulation time 7548214606 ps
CPU time 851.75 seconds
Started Aug 27 02:00:55 PM UTC 24
Finished Aug 27 02:15:16 PM UTC 24
Peak memory 739756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579308780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1579308780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_error.2692004066
Short name T363
Test name
Test status
Simulation time 2191659002 ps
CPU time 164.62 seconds
Started Aug 27 02:01:02 PM UTC 24
Finished Aug 27 02:03:49 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692004066 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2692004066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_long_msg.3931892326
Short name T373
Test name
Test status
Simulation time 57943734667 ps
CPU time 226.33 seconds
Started Aug 27 02:00:55 PM UTC 24
Finished Aug 27 02:04:45 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931892326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3931892326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_smoke.3742304060
Short name T330
Test name
Test status
Simulation time 367971179 ps
CPU time 8.12 seconds
Started Aug 27 02:00:51 PM UTC 24
Finished Aug 27 02:01:00 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742304060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3742304060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_stress_all.4270967596
Short name T429
Test name
Test status
Simulation time 56791336162 ps
CPU time 602.46 seconds
Started Aug 27 02:01:04 PM UTC 24
Finished Aug 27 02:11:14 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270967596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4270967596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.2523247162
Short name T334
Test name
Test status
Simulation time 134090535 ps
CPU time 9.15 seconds
Started Aug 27 02:01:04 PM UTC 24
Finished Aug 27 02:01:14 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523247162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2523247162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_alert_test.3230442850
Short name T341
Test name
Test status
Simulation time 30132690 ps
CPU time 0.87 seconds
Started Aug 27 02:01:48 PM UTC 24
Finished Aug 27 02:01:50 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230442850 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3230442850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.2696096686
Short name T336
Test name
Test status
Simulation time 175422440 ps
CPU time 4.57 seconds
Started Aug 27 02:01:24 PM UTC 24
Finished Aug 27 02:01:29 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696096686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2696096686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.3577495903
Short name T339
Test name
Test status
Simulation time 3265338133 ps
CPU time 15.03 seconds
Started Aug 27 02:01:30 PM UTC 24
Finished Aug 27 02:01:46 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577495903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3577495903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.674511006
Short name T434
Test name
Test status
Simulation time 13269686242 ps
CPU time 622.28 seconds
Started Aug 27 02:01:26 PM UTC 24
Finished Aug 27 02:11:55 PM UTC 24
Peak memory 737492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674511006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.674511006
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_error.3881953693
Short name T340
Test name
Test status
Simulation time 332552671 ps
CPU time 8.06 seconds
Started Aug 27 02:01:38 PM UTC 24
Finished Aug 27 02:01:47 PM UTC 24
Peak memory 207088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881953693 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3881953693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_long_msg.4087640115
Short name T361
Test name
Test status
Simulation time 2068049445 ps
CPU time 129.25 seconds
Started Aug 27 02:01:15 PM UTC 24
Finished Aug 27 02:03:27 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087640115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4087640115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_smoke.4061880684
Short name T335
Test name
Test status
Simulation time 577467159 ps
CPU time 9.79 seconds
Started Aug 27 02:01:14 PM UTC 24
Finished Aug 27 02:01:25 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061880684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4061880684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_stress_all.2827284671
Short name T157
Test name
Test status
Simulation time 39275794723 ps
CPU time 1740 seconds
Started Aug 27 02:01:47 PM UTC 24
Finished Aug 27 02:31:05 PM UTC 24
Peak memory 762216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827284671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2827284671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.4003840133
Short name T96
Test name
Test status
Simulation time 1445884364 ps
CPU time 83.9 seconds
Started Aug 27 02:01:46 PM UTC 24
Finished Aug 27 02:03:12 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003840133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4003840133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_alert_test.1808634790
Short name T350
Test name
Test status
Simulation time 13503578 ps
CPU time 0.83 seconds
Started Aug 27 02:02:36 PM UTC 24
Finished Aug 27 02:02:38 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808634790 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1808634790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.2083363610
Short name T346
Test name
Test status
Simulation time 479310395 ps
CPU time 10.34 seconds
Started Aug 27 02:02:10 PM UTC 24
Finished Aug 27 02:02:22 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083363610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2083363610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.3972093813
Short name T351
Test name
Test status
Simulation time 3361482668 ps
CPU time 20.43 seconds
Started Aug 27 02:02:19 PM UTC 24
Finished Aug 27 02:02:40 PM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972093813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3972093813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.4008405950
Short name T348
Test name
Test status
Simulation time 845607439 ps
CPU time 20.85 seconds
Started Aug 27 02:02:11 PM UTC 24
Finished Aug 27 02:02:33 PM UTC 24
Peak memory 239912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008405950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4008405950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_error.3781442885
Short name T354
Test name
Test status
Simulation time 3483520806 ps
CPU time 25.18 seconds
Started Aug 27 02:02:23 PM UTC 24
Finished Aug 27 02:02:50 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781442885 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3781442885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_long_msg.1433456676
Short name T344
Test name
Test status
Simulation time 530526849 ps
CPU time 12.62 seconds
Started Aug 27 02:01:57 PM UTC 24
Finished Aug 27 02:02:11 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433456676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1433456676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_smoke.3986469939
Short name T343
Test name
Test status
Simulation time 1561219121 ps
CPU time 17.07 seconds
Started Aug 27 02:01:51 PM UTC 24
Finished Aug 27 02:02:10 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986469939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3986469939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_stress_all.673957668
Short name T517
Test name
Test status
Simulation time 19984659749 ps
CPU time 2542.02 seconds
Started Aug 27 02:02:34 PM UTC 24
Finished Aug 27 02:45:23 PM UTC 24
Peak memory 801200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673957668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.673957668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.143267848
Short name T97
Test name
Test status
Simulation time 19596462728 ps
CPU time 77.37 seconds
Started Aug 27 02:02:27 PM UTC 24
Finished Aug 27 02:03:47 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143267848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.143267848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_alert_test.3747979375
Short name T358
Test name
Test status
Simulation time 14593487 ps
CPU time 0.88 seconds
Started Aug 27 02:03:18 PM UTC 24
Finished Aug 27 02:03:20 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747979375 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3747979375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.3974764675
Short name T376
Test name
Test status
Simulation time 11992272152 ps
CPU time 132.6 seconds
Started Aug 27 02:02:43 PM UTC 24
Finished Aug 27 02:04:58 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974764675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3974764675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.26231712
Short name T365
Test name
Test status
Simulation time 2132555282 ps
CPU time 66.76 seconds
Started Aug 27 02:02:51 PM UTC 24
Finished Aug 27 02:03:59 PM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26231712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.26231712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1424073523
Short name T366
Test name
Test status
Simulation time 2740270552 ps
CPU time 72.01 seconds
Started Aug 27 02:02:48 PM UTC 24
Finished Aug 27 02:04:02 PM UTC 24
Peak memory 332064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424073523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1424073523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_error.3276906453
Short name T390
Test name
Test status
Simulation time 8887277809 ps
CPU time 190.78 seconds
Started Aug 27 02:02:57 PM UTC 24
Finished Aug 27 02:06:11 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276906453 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3276906453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_long_msg.3603877545
Short name T357
Test name
Test status
Simulation time 1861426989 ps
CPU time 32.65 seconds
Started Aug 27 02:02:43 PM UTC 24
Finished Aug 27 02:03:17 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603877545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3603877545
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_smoke.2905035033
Short name T355
Test name
Test status
Simulation time 670304654 ps
CPU time 15.51 seconds
Started Aug 27 02:02:39 PM UTC 24
Finished Aug 27 02:02:56 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905035033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2905035033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_stress_all.3085510533
Short name T520
Test name
Test status
Simulation time 69050703816 ps
CPU time 2771.98 seconds
Started Aug 27 02:03:14 PM UTC 24
Finished Aug 27 02:49:51 PM UTC 24
Peak memory 770332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085510533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3085510533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.409206239
Short name T98
Test name
Test status
Simulation time 9721342368 ps
CPU time 62.07 seconds
Started Aug 27 02:03:12 PM UTC 24
Finished Aug 27 02:04:16 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409206239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.409206239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_alert_test.3928146224
Short name T367
Test name
Test status
Simulation time 14537338 ps
CPU time 0.84 seconds
Started Aug 27 02:04:00 PM UTC 24
Finished Aug 27 02:04:02 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928146224 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3928146224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.2313952174
Short name T369
Test name
Test status
Simulation time 888515913 ps
CPU time 50.63 seconds
Started Aug 27 02:03:29 PM UTC 24
Finished Aug 27 02:04:22 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313952174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2313952174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3280055651
Short name T364
Test name
Test status
Simulation time 4819750685 ps
CPU time 21.12 seconds
Started Aug 27 02:03:34 PM UTC 24
Finished Aug 27 02:03:57 PM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280055651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3280055651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.118764741
Short name T510
Test name
Test status
Simulation time 35876167801 ps
CPU time 1826.25 seconds
Started Aug 27 02:03:29 PM UTC 24
Finished Aug 27 02:34:14 PM UTC 24
Peak memory 801128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118764741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.118764741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_error.2400129735
Short name T393
Test name
Test status
Simulation time 2329862456 ps
CPU time 148.45 seconds
Started Aug 27 02:03:48 PM UTC 24
Finished Aug 27 02:06:19 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400129735 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2400129735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_long_msg.1235277416
Short name T398
Test name
Test status
Simulation time 23050595807 ps
CPU time 243.27 seconds
Started Aug 27 02:03:25 PM UTC 24
Finished Aug 27 02:07:32 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235277416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1235277416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_smoke.1592199989
Short name T362
Test name
Test status
Simulation time 586443195 ps
CPU time 11.17 seconds
Started Aug 27 02:03:21 PM UTC 24
Finished Aug 27 02:03:33 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592199989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1592199989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.5342916
Short name T381
Test name
Test status
Simulation time 3831055858 ps
CPU time 88.55 seconds
Started Aug 27 02:03:51 PM UTC 24
Finished Aug 27 02:05:21 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5342916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.5342916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_alert_test.435912537
Short name T375
Test name
Test status
Simulation time 23609735 ps
CPU time 0.81 seconds
Started Aug 27 02:04:47 PM UTC 24
Finished Aug 27 02:04:49 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435912537 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.435912537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.2642711600
Short name T382
Test name
Test status
Simulation time 5606923572 ps
CPU time 78.78 seconds
Started Aug 27 02:04:09 PM UTC 24
Finished Aug 27 02:05:31 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642711600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2642711600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2023519928
Short name T378
Test name
Test status
Simulation time 1944918490 ps
CPU time 38.89 seconds
Started Aug 27 02:04:22 PM UTC 24
Finished Aug 27 02:05:03 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023519928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2023519928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.546298511
Short name T490
Test name
Test status
Simulation time 5322744012 ps
CPU time 1017.71 seconds
Started Aug 27 02:04:17 PM UTC 24
Finished Aug 27 02:21:25 PM UTC 24
Peak memory 741596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546298511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.546298511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_error.4020449332
Short name T397
Test name
Test status
Simulation time 2663261981 ps
CPU time 173.61 seconds
Started Aug 27 02:04:26 PM UTC 24
Finished Aug 27 02:07:22 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020449332 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4020449332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_long_msg.2065683404
Short name T385
Test name
Test status
Simulation time 2990210899 ps
CPU time 99.8 seconds
Started Aug 27 02:04:02 PM UTC 24
Finished Aug 27 02:05:44 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065683404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2065683404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_smoke.1651491729
Short name T370
Test name
Test status
Simulation time 4567815566 ps
CPU time 21.1 seconds
Started Aug 27 02:04:02 PM UTC 24
Finished Aug 27 02:04:25 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651491729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1651491729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_stress_all.3926320290
Short name T514
Test name
Test status
Simulation time 207296056474 ps
CPU time 2021.32 seconds
Started Aug 27 02:04:45 PM UTC 24
Finished Aug 27 02:38:48 PM UTC 24
Peak memory 792860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926320290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3926320290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2656478734
Short name T374
Test name
Test status
Simulation time 358247391 ps
CPU time 11.89 seconds
Started Aug 27 02:04:35 PM UTC 24
Finished Aug 27 02:04:48 PM UTC 24
Peak memory 207124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656478734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2656478734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_alert_test.742148778
Short name T383
Test name
Test status
Simulation time 13794987 ps
CPU time 0.85 seconds
Started Aug 27 02:05:33 PM UTC 24
Finished Aug 27 02:05:35 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742148778 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.742148778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.348704430
Short name T379
Test name
Test status
Simulation time 62726479 ps
CPU time 2.36 seconds
Started Aug 27 02:05:00 PM UTC 24
Finished Aug 27 02:05:03 PM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348704430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.348704430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.2768174835
Short name T380
Test name
Test status
Simulation time 841905356 ps
CPU time 15.45 seconds
Started Aug 27 02:05:04 PM UTC 24
Finished Aug 27 02:05:21 PM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768174835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2768174835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.3949849697
Short name T488
Test name
Test status
Simulation time 4115854276 ps
CPU time 880.37 seconds
Started Aug 27 02:05:00 PM UTC 24
Finished Aug 27 02:19:50 PM UTC 24
Peak memory 752156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949849697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3949849697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_error.721133192
Short name T405
Test name
Test status
Simulation time 14010782657 ps
CPU time 178.05 seconds
Started Aug 27 02:05:04 PM UTC 24
Finished Aug 27 02:08:05 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721133192 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.721133192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_long_msg.2973177762
Short name T407
Test name
Test status
Simulation time 15540809069 ps
CPU time 200.31 seconds
Started Aug 27 02:04:50 PM UTC 24
Finished Aug 27 02:08:13 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973177762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2973177762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_smoke.1012283366
Short name T377
Test name
Test status
Simulation time 122856645 ps
CPU time 7.08 seconds
Started Aug 27 02:04:50 PM UTC 24
Finished Aug 27 02:04:58 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012283366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1012283366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_stress_all.3616765003
Short name T518
Test name
Test status
Simulation time 24852975186 ps
CPU time 2402.33 seconds
Started Aug 27 02:05:23 PM UTC 24
Finished Aug 27 02:45:49 PM UTC 24
Peak memory 813484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616765003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3616765003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.985447352
Short name T388
Test name
Test status
Simulation time 2616799047 ps
CPU time 37.84 seconds
Started Aug 27 02:05:21 PM UTC 24
Finished Aug 27 02:06:01 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985447352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.985447352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_alert_test.3319064950
Short name T391
Test name
Test status
Simulation time 12825126 ps
CPU time 0.81 seconds
Started Aug 27 02:06:13 PM UTC 24
Finished Aug 27 02:06:15 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319064950 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3319064950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.80211287
Short name T406
Test name
Test status
Simulation time 10189739388 ps
CPU time 137.95 seconds
Started Aug 27 02:05:46 PM UTC 24
Finished Aug 27 02:08:07 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80211287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.80211287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.1283829781
Short name T389
Test name
Test status
Simulation time 7032521152 ps
CPU time 9.79 seconds
Started Aug 27 02:05:58 PM UTC 24
Finished Aug 27 02:06:09 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283829781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1283829781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.518641131
Short name T491
Test name
Test status
Simulation time 40703195123 ps
CPU time 998.78 seconds
Started Aug 27 02:05:49 PM UTC 24
Finished Aug 27 02:22:38 PM UTC 24
Peak memory 725192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518641131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.518641131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_error.1212953423
Short name T411
Test name
Test status
Simulation time 5725847082 ps
CPU time 167.47 seconds
Started Aug 27 02:06:02 PM UTC 24
Finished Aug 27 02:08:52 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212953423 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1212953423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_long_msg.1148748393
Short name T403
Test name
Test status
Simulation time 38624858005 ps
CPU time 129.89 seconds
Started Aug 27 02:05:43 PM UTC 24
Finished Aug 27 02:07:56 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148748393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1148748393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_smoke.4141392174
Short name T386
Test name
Test status
Simulation time 10001479048 ps
CPU time 11.13 seconds
Started Aug 27 02:05:36 PM UTC 24
Finished Aug 27 02:05:48 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141392174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4141392174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_stress_all.2685168304
Short name T525
Test name
Test status
Simulation time 130775678387 ps
CPU time 3160.43 seconds
Started Aug 27 02:06:10 PM UTC 24
Finished Aug 27 02:59:21 PM UTC 24
Peak memory 842168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685168304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2685168304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.472709392
Short name T399
Test name
Test status
Simulation time 7594467274 ps
CPU time 84.93 seconds
Started Aug 27 02:06:08 PM UTC 24
Finished Aug 27 02:07:35 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472709392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.472709392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_alert_test.79784965
Short name T77
Test name
Test status
Simulation time 14760616 ps
CPU time 0.9 seconds
Started Aug 27 01:44:14 PM UTC 24
Finished Aug 27 01:44:15 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79784965 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.79784965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.3291434656
Short name T56
Test name
Test status
Simulation time 3326020111 ps
CPU time 135.8 seconds
Started Aug 27 01:43:35 PM UTC 24
Finished Aug 27 01:45:53 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291434656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3291434656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.297113061
Short name T24
Test name
Test status
Simulation time 590106128 ps
CPU time 30.07 seconds
Started Aug 27 01:43:37 PM UTC 24
Finished Aug 27 01:44:09 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297113061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.297113061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.2102692642
Short name T424
Test name
Test status
Simulation time 7196079706 ps
CPU time 1596.67 seconds
Started Aug 27 01:43:36 PM UTC 24
Finished Aug 27 02:10:29 PM UTC 24
Peak memory 803120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102692642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2102692642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_error.91773690
Short name T143
Test name
Test status
Simulation time 2717251195 ps
CPU time 169.78 seconds
Started Aug 27 01:43:40 PM UTC 24
Finished Aug 27 01:46:33 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91773690 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.91773690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_long_msg.1326980863
Short name T159
Test name
Test status
Simulation time 92603369238 ps
CPU time 140.29 seconds
Started Aug 27 01:43:35 PM UTC 24
Finished Aug 27 01:45:57 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326980863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1326980863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.2513211928
Short name T68
Test name
Test status
Simulation time 300197213 ps
CPU time 1.47 seconds
Started Aug 27 01:44:12 PM UTC 24
Finished Aug 27 01:44:14 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513211928 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2513211928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_smoke.2468846033
Short name T141
Test name
Test status
Simulation time 141870244 ps
CPU time 3.63 seconds
Started Aug 27 01:43:35 PM UTC 24
Finished Aug 27 01:43:39 PM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468846033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2468846033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_stress_all.1787178130
Short name T85
Test name
Test status
Simulation time 484676781789 ps
CPU time 3432.36 seconds
Started Aug 27 01:44:05 PM UTC 24
Finished Aug 27 02:41:52 PM UTC 24
Peak memory 815224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787178130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1787178130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.1951009615
Short name T76
Test name
Test status
Simulation time 83614298681 ps
CPU time 394.58 seconds
Started Aug 27 01:44:10 PM UTC 24
Finished Aug 27 01:50:50 PM UTC 24
Peak memory 645208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19510096
15 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1951009615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.2932111275
Short name T167
Test name
Test status
Simulation time 21740376122 ps
CPU time 105.13 seconds
Started Aug 27 01:43:57 PM UTC 24
Finished Aug 27 01:45:44 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932111275 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2932111275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.1290454487
Short name T169
Test name
Test status
Simulation time 18681591931 ps
CPU time 118.18 seconds
Started Aug 27 01:44:00 PM UTC 24
Finished Aug 27 01:46:01 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290454487 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1290454487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.3327729014
Short name T175
Test name
Test status
Simulation time 83687996786 ps
CPU time 148.78 seconds
Started Aug 27 01:44:04 PM UTC 24
Finished Aug 27 01:46:36 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327729014 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3327729014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.4258851443
Short name T266
Test name
Test status
Simulation time 219775290274 ps
CPU time 701.31 seconds
Started Aug 27 01:43:52 PM UTC 24
Finished Aug 27 01:55:42 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258851443 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.4258851443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.2488252990
Short name T506
Test name
Test status
Simulation time 2828442721375 ps
CPU time 2791.37 seconds
Started Aug 27 01:43:54 PM UTC 24
Finished Aug 27 02:30:58 PM UTC 24
Peak memory 221376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488252990 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2488252990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1456825722
Short name T496
Test name
Test status
Simulation time 224697586483 ps
CPU time 2461.22 seconds
Started Aug 27 01:43:56 PM UTC 24
Finished Aug 27 02:25:24 PM UTC 24
Peak memory 227400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456825722 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1456825722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.3030750486
Short name T40
Test name
Test status
Simulation time 8657671770 ps
CPU time 100.26 seconds
Started Aug 27 01:43:43 PM UTC 24
Finished Aug 27 01:45:25 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030750486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3030750486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_alert_test.574703765
Short name T400
Test name
Test status
Simulation time 23207500 ps
CPU time 0.85 seconds
Started Aug 27 02:07:36 PM UTC 24
Finished Aug 27 02:07:38 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574703765 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.574703765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.4180775802
Short name T395
Test name
Test status
Simulation time 166894086 ps
CPU time 11.38 seconds
Started Aug 27 02:06:21 PM UTC 24
Finished Aug 27 02:06:33 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180775802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4180775802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.607333702
Short name T404
Test name
Test status
Simulation time 1245397949 ps
CPU time 85.31 seconds
Started Aug 27 02:06:34 PM UTC 24
Finished Aug 27 02:08:01 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607333702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.607333702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.2704171133
Short name T501
Test name
Test status
Simulation time 23623848344 ps
CPU time 1294.65 seconds
Started Aug 27 02:06:32 PM UTC 24
Finished Aug 27 02:28:19 PM UTC 24
Peak memory 782620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704171133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2704171133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_error.4225747580
Short name T416
Test name
Test status
Simulation time 21133052701 ps
CPU time 154.12 seconds
Started Aug 27 02:07:09 PM UTC 24
Finished Aug 27 02:09:46 PM UTC 24
Peak memory 207424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225747580 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4225747580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1783963110
Short name T394
Test name
Test status
Simulation time 625546573 ps
CPU time 11.37 seconds
Started Aug 27 02:06:19 PM UTC 24
Finished Aug 27 02:06:32 PM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783963110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1783963110
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_smoke.2341759466
Short name T392
Test name
Test status
Simulation time 74289512 ps
CPU time 2.38 seconds
Started Aug 27 02:06:15 PM UTC 24
Finished Aug 27 02:06:18 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341759466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2341759466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_stress_all.1656586602
Short name T455
Test name
Test status
Simulation time 5263588141 ps
CPU time 400.29 seconds
Started Aug 27 02:07:34 PM UTC 24
Finished Aug 27 02:14:21 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656586602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1656586602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.352980001
Short name T401
Test name
Test status
Simulation time 2710889634 ps
CPU time 19.38 seconds
Started Aug 27 02:07:24 PM UTC 24
Finished Aug 27 02:07:45 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352980001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.352980001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_alert_test.643485322
Short name T409
Test name
Test status
Simulation time 30385196 ps
CPU time 0.85 seconds
Started Aug 27 02:08:23 PM UTC 24
Finished Aug 27 02:08:25 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643485322 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.643485322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.2444032922
Short name T45
Test name
Test status
Simulation time 713703756 ps
CPU time 39.43 seconds
Started Aug 27 02:07:47 PM UTC 24
Finished Aug 27 02:08:28 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444032922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2444032922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.3311036661
Short name T408
Test name
Test status
Simulation time 3001642855 ps
CPU time 18.66 seconds
Started Aug 27 02:08:02 PM UTC 24
Finished Aug 27 02:08:22 PM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311036661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3311036661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.3272527736
Short name T489
Test name
Test status
Simulation time 47016321870 ps
CPU time 746.65 seconds
Started Aug 27 02:07:57 PM UTC 24
Finished Aug 27 02:20:33 PM UTC 24
Peak memory 747804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272527736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3272527736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_error.3454432082
Short name T422
Test name
Test status
Simulation time 31465773560 ps
CPU time 136.44 seconds
Started Aug 27 02:08:06 PM UTC 24
Finished Aug 27 02:10:25 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454432082 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3454432082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_long_msg.3960267802
Short name T413
Test name
Test status
Simulation time 1416016641 ps
CPU time 86.97 seconds
Started Aug 27 02:07:46 PM UTC 24
Finished Aug 27 02:09:15 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960267802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3960267802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_smoke.2246814857
Short name T402
Test name
Test status
Simulation time 3384226692 ps
CPU time 6.03 seconds
Started Aug 27 02:07:39 PM UTC 24
Finished Aug 27 02:07:46 PM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246814857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2246814857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_stress_all.446211798
Short name T84
Test name
Test status
Simulation time 94258831727 ps
CPU time 1118.95 seconds
Started Aug 27 02:08:15 PM UTC 24
Finished Aug 27 02:27:06 PM UTC 24
Peak memory 217992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446211798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.446211798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.3876665156
Short name T418
Test name
Test status
Simulation time 3978944007 ps
CPU time 108.45 seconds
Started Aug 27 02:08:08 PM UTC 24
Finished Aug 27 02:09:59 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876665156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3876665156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_alert_test.2884235996
Short name T417
Test name
Test status
Simulation time 25200740 ps
CPU time 0.85 seconds
Started Aug 27 02:09:45 PM UTC 24
Finished Aug 27 02:09:47 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884235996 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2884235996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.3498434606
Short name T414
Test name
Test status
Simulation time 1103140988 ps
CPU time 44.79 seconds
Started Aug 27 02:08:38 PM UTC 24
Finished Aug 27 02:09:25 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498434606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3498434606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.1035848593
Short name T412
Test name
Test status
Simulation time 21470744 ps
CPU time 1.5 seconds
Started Aug 27 02:09:04 PM UTC 24
Finished Aug 27 02:09:07 PM UTC 24
Peak memory 206228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035848593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1035848593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.1442607202
Short name T482
Test name
Test status
Simulation time 11706457223 ps
CPU time 529.29 seconds
Started Aug 27 02:08:53 PM UTC 24
Finished Aug 27 02:17:48 PM UTC 24
Peak memory 762152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442607202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1442607202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_error.639873962
Short name T445
Test name
Test status
Simulation time 39759014779 ps
CPU time 233.53 seconds
Started Aug 27 02:09:07 PM UTC 24
Finished Aug 27 02:13:04 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639873962 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.639873962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2786947645
Short name T425
Test name
Test status
Simulation time 10376111641 ps
CPU time 118.67 seconds
Started Aug 27 02:08:29 PM UTC 24
Finished Aug 27 02:10:30 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786947645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2786947645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_smoke.2128874384
Short name T410
Test name
Test status
Simulation time 7913248278 ps
CPU time 10.1 seconds
Started Aug 27 02:08:26 PM UTC 24
Finished Aug 27 02:08:37 PM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128874384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2128874384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.1869004966
Short name T437
Test name
Test status
Simulation time 13411895964 ps
CPU time 169.5 seconds
Started Aug 27 02:09:17 PM UTC 24
Finished Aug 27 02:12:09 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869004966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1869004966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_alert_test.947924599
Short name T426
Test name
Test status
Simulation time 11605384 ps
CPU time 0.82 seconds
Started Aug 27 02:10:32 PM UTC 24
Finished Aug 27 02:10:34 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947924599 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.947924599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.1106179566
Short name T421
Test name
Test status
Simulation time 1135227173 ps
CPU time 17.9 seconds
Started Aug 27 02:10:01 PM UTC 24
Finished Aug 27 02:10:20 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106179566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1106179566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.2067394069
Short name T423
Test name
Test status
Simulation time 872985672 ps
CPU time 7.56 seconds
Started Aug 27 02:10:18 PM UTC 24
Finished Aug 27 02:10:27 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067394069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2067394069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.1147409883
Short name T468
Test name
Test status
Simulation time 1893461440 ps
CPU time 337.14 seconds
Started Aug 27 02:10:05 PM UTC 24
Finished Aug 27 02:15:47 PM UTC 24
Peak memory 465080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147409883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1147409883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_error.910888706
Short name T436
Test name
Test status
Simulation time 20413933202 ps
CPU time 104.3 seconds
Started Aug 27 02:10:21 PM UTC 24
Finished Aug 27 02:12:08 PM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910888706 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.910888706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1882100815
Short name T453
Test name
Test status
Simulation time 16351778308 ps
CPU time 258.84 seconds
Started Aug 27 02:09:48 PM UTC 24
Finished Aug 27 02:14:11 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882100815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1882100815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_smoke.883326215
Short name T419
Test name
Test status
Simulation time 1527812090 ps
CPU time 14.6 seconds
Started Aug 27 02:09:48 PM UTC 24
Finished Aug 27 02:10:04 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883326215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.883326215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_stress_all.3611859356
Short name T527
Test name
Test status
Simulation time 39925125630 ps
CPU time 5252.77 seconds
Started Aug 27 02:10:28 PM UTC 24
Finished Aug 27 03:38:52 PM UTC 24
Peak memory 893120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611859356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3611859356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2070722499
Short name T99
Test name
Test status
Simulation time 13473490930 ps
CPU time 71.84 seconds
Started Aug 27 02:10:27 PM UTC 24
Finished Aug 27 02:11:41 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070722499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2070722499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2196828416
Short name T432
Test name
Test status
Simulation time 31407015 ps
CPU time 0.81 seconds
Started Aug 27 02:11:42 PM UTC 24
Finished Aug 27 02:11:44 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196828416 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2196828416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.657930687
Short name T438
Test name
Test status
Simulation time 5769594065 ps
CPU time 87.36 seconds
Started Aug 27 02:10:41 PM UTC 24
Finished Aug 27 02:12:10 PM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657930687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.657930687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.1616103765
Short name T430
Test name
Test status
Simulation time 2597889020 ps
CPU time 23 seconds
Started Aug 27 02:10:54 PM UTC 24
Finished Aug 27 02:11:19 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616103765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1616103765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.122988060
Short name T480
Test name
Test status
Simulation time 6751045071 ps
CPU time 379.86 seconds
Started Aug 27 02:10:49 PM UTC 24
Finished Aug 27 02:17:14 PM UTC 24
Peak memory 506188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122988060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.122988060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_error.1865120583
Short name T456
Test name
Test status
Simulation time 13597179780 ps
CPU time 202.35 seconds
Started Aug 27 02:11:19 PM UTC 24
Finished Aug 27 02:14:44 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865120583 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1865120583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_long_msg.3147348746
Short name T431
Test name
Test status
Simulation time 766149236 ps
CPU time 55.23 seconds
Started Aug 27 02:10:35 PM UTC 24
Finished Aug 27 02:11:32 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147348746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3147348746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_smoke.2231512375
Short name T427
Test name
Test status
Simulation time 85460683 ps
CPU time 5.01 seconds
Started Aug 27 02:10:34 PM UTC 24
Finished Aug 27 02:10:40 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231512375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2231512375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.1282766509
Short name T435
Test name
Test status
Simulation time 2520104365 ps
CPU time 41.31 seconds
Started Aug 27 02:11:20 PM UTC 24
Finished Aug 27 02:12:03 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282766509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1282766509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_alert_test.3374074900
Short name T441
Test name
Test status
Simulation time 36851124 ps
CPU time 0.84 seconds
Started Aug 27 02:12:32 PM UTC 24
Finished Aug 27 02:12:34 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374074900 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3374074900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.1647449362
Short name T448
Test name
Test status
Simulation time 1684577631 ps
CPU time 102.25 seconds
Started Aug 27 02:11:57 PM UTC 24
Finished Aug 27 02:13:42 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647449362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1647449362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.1492106478
Short name T440
Test name
Test status
Simulation time 909594706 ps
CPU time 20.94 seconds
Started Aug 27 02:12:09 PM UTC 24
Finished Aug 27 02:12:31 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492106478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1492106478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.4132230608
Short name T512
Test name
Test status
Simulation time 7047691919 ps
CPU time 1397.95 seconds
Started Aug 27 02:12:03 PM UTC 24
Finished Aug 27 02:35:35 PM UTC 24
Peak memory 784668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132230608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4132230608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_error.1457105559
Short name T449
Test name
Test status
Simulation time 2739125586 ps
CPU time 90.67 seconds
Started Aug 27 02:12:12 PM UTC 24
Finished Aug 27 02:13:44 PM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457105559 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1457105559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_long_msg.2162785691
Short name T443
Test name
Test status
Simulation time 923188354 ps
CPU time 54.19 seconds
Started Aug 27 02:11:54 PM UTC 24
Finished Aug 27 02:12:50 PM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162785691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2162785691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_smoke.2067189563
Short name T433
Test name
Test status
Simulation time 1320873154 ps
CPU time 7.54 seconds
Started Aug 27 02:11:45 PM UTC 24
Finished Aug 27 02:11:54 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067189563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2067189563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_stress_all.560743352
Short name T524
Test name
Test status
Simulation time 257322884880 ps
CPU time 2775.78 seconds
Started Aug 27 02:12:20 PM UTC 24
Finished Aug 27 02:59:03 PM UTC 24
Peak memory 766184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560743352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.560743352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.893132152
Short name T442
Test name
Test status
Simulation time 363892765 ps
CPU time 22.09 seconds
Started Aug 27 02:12:12 PM UTC 24
Finished Aug 27 02:12:35 PM UTC 24
Peak memory 207208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893132152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.893132152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_alert_test.2389749486
Short name T451
Test name
Test status
Simulation time 51635648 ps
CPU time 0.83 seconds
Started Aug 27 02:13:46 PM UTC 24
Finished Aug 27 02:13:48 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389749486 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2389749486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.1868883430
Short name T446
Test name
Test status
Simulation time 176793899 ps
CPU time 15.21 seconds
Started Aug 27 02:12:51 PM UTC 24
Finished Aug 27 02:13:07 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868883430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1868883430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.1489694867
Short name T450
Test name
Test status
Simulation time 1217848851 ps
CPU time 38.96 seconds
Started Aug 27 02:13:06 PM UTC 24
Finished Aug 27 02:13:47 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489694867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1489694867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1018502903
Short name T513
Test name
Test status
Simulation time 29290875276 ps
CPU time 1408.59 seconds
Started Aug 27 02:12:56 PM UTC 24
Finished Aug 27 02:36:38 PM UTC 24
Peak memory 790884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018502903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1018502903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_error.4206794567
Short name T481
Test name
Test status
Simulation time 6747646448 ps
CPU time 256.35 seconds
Started Aug 27 02:13:08 PM UTC 24
Finished Aug 27 02:17:29 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206794567 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4206794567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_long_msg.264952957
Short name T447
Test name
Test status
Simulation time 23099898829 ps
CPU time 61.47 seconds
Started Aug 27 02:12:36 PM UTC 24
Finished Aug 27 02:13:40 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264952957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.264952957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_smoke.2668311242
Short name T444
Test name
Test status
Simulation time 4233153830 ps
CPU time 18.5 seconds
Started Aug 27 02:12:35 PM UTC 24
Finished Aug 27 02:12:55 PM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668311242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2668311242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_stress_all.3804316927
Short name T523
Test name
Test status
Simulation time 58326929672 ps
CPU time 2578.37 seconds
Started Aug 27 02:13:43 PM UTC 24
Finished Aug 27 02:57:06 PM UTC 24
Peak memory 833972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804316927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3804316927
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.2740108430
Short name T466
Test name
Test status
Simulation time 4700604314 ps
CPU time 122.63 seconds
Started Aug 27 02:13:40 PM UTC 24
Finished Aug 27 02:15:45 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740108430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2740108430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_alert_test.983492151
Short name T458
Test name
Test status
Simulation time 34074527 ps
CPU time 0.78 seconds
Started Aug 27 02:14:46 PM UTC 24
Finished Aug 27 02:14:48 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983492151 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.983492151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.3762852042
Short name T454
Test name
Test status
Simulation time 1922937871 ps
CPU time 26 seconds
Started Aug 27 02:13:53 PM UTC 24
Finished Aug 27 02:14:20 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762852042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3762852042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.1604033877
Short name T463
Test name
Test status
Simulation time 1758564416 ps
CPU time 71.55 seconds
Started Aug 27 02:14:13 PM UTC 24
Finished Aug 27 02:15:26 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604033877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1604033877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2856071303
Short name T508
Test name
Test status
Simulation time 5930598592 ps
CPU time 1053.09 seconds
Started Aug 27 02:13:58 PM UTC 24
Finished Aug 27 02:31:42 PM UTC 24
Peak memory 715176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856071303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2856071303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_error.4140076427
Short name T460
Test name
Test status
Simulation time 25352418483 ps
CPU time 41.04 seconds
Started Aug 27 02:14:25 PM UTC 24
Finished Aug 27 02:15:07 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140076427 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4140076427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_long_msg.4246132396
Short name T472
Test name
Test status
Simulation time 2381741486 ps
CPU time 144.6 seconds
Started Aug 27 02:13:49 PM UTC 24
Finished Aug 27 02:16:16 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246132396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4246132396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_smoke.704847141
Short name T452
Test name
Test status
Simulation time 51023238 ps
CPU time 3.22 seconds
Started Aug 27 02:13:48 PM UTC 24
Finished Aug 27 02:13:52 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704847141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.704847141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2166246364
Short name T521
Test name
Test status
Simulation time 24741834364 ps
CPU time 2119.99 seconds
Started Aug 27 02:14:29 PM UTC 24
Finished Aug 27 02:50:10 PM UTC 24
Peak memory 706800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166246364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2166246364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.3664134213
Short name T457
Test name
Test status
Simulation time 5217800336 ps
CPU time 21.44 seconds
Started Aug 27 02:14:25 PM UTC 24
Finished Aug 27 02:14:47 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664134213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3664134213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_alert_test.3354297043
Short name T467
Test name
Test status
Simulation time 14791722 ps
CPU time 0.86 seconds
Started Aug 27 02:15:44 PM UTC 24
Finished Aug 27 02:15:46 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354297043 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3354297043
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.3462664024
Short name T17
Test name
Test status
Simulation time 4411324176 ps
CPU time 105.35 seconds
Started Aug 27 02:15:04 PM UTC 24
Finished Aug 27 02:16:52 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462664024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3462664024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.4078386192
Short name T465
Test name
Test status
Simulation time 1553310899 ps
CPU time 19.31 seconds
Started Aug 27 02:15:23 PM UTC 24
Finished Aug 27 02:15:43 PM UTC 24
Peak memory 207172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078386192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4078386192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.1809722185
Short name T484
Test name
Test status
Simulation time 18570479164 ps
CPU time 192.13 seconds
Started Aug 27 02:15:09 PM UTC 24
Finished Aug 27 02:18:23 PM UTC 24
Peak memory 643352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809722185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1809722185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_error.217604399
Short name T471
Test name
Test status
Simulation time 612538260 ps
CPU time 42.53 seconds
Started Aug 27 02:15:23 PM UTC 24
Finished Aug 27 02:16:07 PM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217604399 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.217604399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_long_msg.3994079697
Short name T469
Test name
Test status
Simulation time 1070273038 ps
CPU time 66.23 seconds
Started Aug 27 02:14:49 PM UTC 24
Finished Aug 27 02:15:57 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994079697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3994079697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_smoke.2363921520
Short name T459
Test name
Test status
Simulation time 1755324910 ps
CPU time 13.62 seconds
Started Aug 27 02:14:48 PM UTC 24
Finished Aug 27 02:15:03 PM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363921520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2363921520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_stress_all.3984706673
Short name T486
Test name
Test status
Simulation time 16640961023 ps
CPU time 219.16 seconds
Started Aug 27 02:15:38 PM UTC 24
Finished Aug 27 02:19:21 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984706673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3984706673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.2647272374
Short name T479
Test name
Test status
Simulation time 17582896781 ps
CPU time 101.51 seconds
Started Aug 27 02:15:27 PM UTC 24
Finished Aug 27 02:17:11 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647272374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2647272374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_alert_test.2218954551
Short name T476
Test name
Test status
Simulation time 20912342 ps
CPU time 0.89 seconds
Started Aug 27 02:16:31 PM UTC 24
Finished Aug 27 02:16:34 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218954551 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2218954551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.325510522
Short name T474
Test name
Test status
Simulation time 1154959629 ps
CPU time 39.5 seconds
Started Aug 27 02:15:49 PM UTC 24
Finished Aug 27 02:16:30 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325510522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.325510522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.1951445284
Short name T473
Test name
Test status
Simulation time 4029578986 ps
CPU time 22.34 seconds
Started Aug 27 02:16:05 PM UTC 24
Finished Aug 27 02:16:28 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951445284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1951445284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.787270492
Short name T505
Test name
Test status
Simulation time 40819444804 ps
CPU time 829.21 seconds
Started Aug 27 02:15:58 PM UTC 24
Finished Aug 27 02:29:56 PM UTC 24
Peak memory 760064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787270492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.787270492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_error.380871685
Short name T477
Test name
Test status
Simulation time 11405943581 ps
CPU time 46.97 seconds
Started Aug 27 02:16:08 PM UTC 24
Finished Aug 27 02:16:56 PM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380871685 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.380871685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_long_msg.253779912
Short name T487
Test name
Test status
Simulation time 75141465688 ps
CPU time 218.93 seconds
Started Aug 27 02:15:47 PM UTC 24
Finished Aug 27 02:19:29 PM UTC 24
Peak memory 217924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253779912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.253779912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_smoke.3655770442
Short name T470
Test name
Test status
Simulation time 3763798662 ps
CPU time 15.57 seconds
Started Aug 27 02:15:47 PM UTC 24
Finished Aug 27 02:16:04 PM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655770442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3655770442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2130921355
Short name T507
Test name
Test status
Simulation time 127478341774 ps
CPU time 880.46 seconds
Started Aug 27 02:16:29 PM UTC 24
Finished Aug 27 02:31:20 PM UTC 24
Peak memory 707112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130921355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2130921355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.1602415652
Short name T475
Test name
Test status
Simulation time 686583314 ps
CPU time 12.71 seconds
Started Aug 27 02:16:18 PM UTC 24
Finished Aug 27 02:16:33 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602415652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1602415652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_alert_test.22479710
Short name T162
Test name
Test status
Simulation time 11029105 ps
CPU time 0.87 seconds
Started Aug 27 01:44:28 PM UTC 24
Finished Aug 27 01:44:30 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22479710 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.22479710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.4235943336
Short name T147
Test name
Test status
Simulation time 4535134269 ps
CPU time 22.99 seconds
Started Aug 27 01:44:19 PM UTC 24
Finished Aug 27 01:44:43 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235943336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4235943336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.829829235
Short name T206
Test name
Test status
Simulation time 8313538122 ps
CPU time 334.82 seconds
Started Aug 27 01:44:19 PM UTC 24
Finished Aug 27 01:49:59 PM UTC 24
Peak memory 641452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829829235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.829829235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_error.2280497349
Short name T182
Test name
Test status
Simulation time 13246399817 ps
CPU time 160.8 seconds
Started Aug 27 01:44:22 PM UTC 24
Finished Aug 27 01:47:05 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280497349 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2280497349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_long_msg.595951648
Short name T191
Test name
Test status
Simulation time 68525220580 ps
CPU time 232.42 seconds
Started Aug 27 01:44:17 PM UTC 24
Finished Aug 27 01:48:13 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595951648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.595951648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_smoke.3269651377
Short name T146
Test name
Test status
Simulation time 3151818244 ps
CPU time 10.06 seconds
Started Aug 27 01:44:16 PM UTC 24
Finished Aug 27 01:44:27 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269651377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3269651377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_stress_all.1686346208
Short name T83
Test name
Test status
Simulation time 142979135672 ps
CPU time 2104.06 seconds
Started Aug 27 01:44:26 PM UTC 24
Finished Aug 27 02:19:50 PM UTC 24
Peak memory 813368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686346208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1686346208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.717098299
Short name T122
Test name
Test status
Simulation time 20565816965 ps
CPU time 93.47 seconds
Started Aug 27 01:44:23 PM UTC 24
Finished Aug 27 01:45:59 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717098299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.717098299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_alert_test.23675120
Short name T36
Test name
Test status
Simulation time 45497728 ps
CPU time 0.8 seconds
Started Aug 27 01:45:05 PM UTC 24
Finished Aug 27 01:45:07 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23675120 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.23675120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.1928101203
Short name T43
Test name
Test status
Simulation time 683798420 ps
CPU time 49.76 seconds
Started Aug 27 01:44:44 PM UTC 24
Finished Aug 27 01:45:36 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928101203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1928101203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.3842417306
Short name T166
Test name
Test status
Simulation time 284602446 ps
CPU time 4.41 seconds
Started Aug 27 01:44:47 PM UTC 24
Finished Aug 27 01:44:53 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842417306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3842417306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1182539525
Short name T281
Test name
Test status
Simulation time 70923475434 ps
CPU time 705.2 seconds
Started Aug 27 01:44:47 PM UTC 24
Finished Aug 27 01:56:40 PM UTC 24
Peak memory 696544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182539525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1182539525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_error.3396993073
Short name T62
Test name
Test status
Simulation time 3880562663 ps
CPU time 65.12 seconds
Started Aug 27 01:44:48 PM UTC 24
Finished Aug 27 01:45:55 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396993073 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3396993073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_long_msg.562194182
Short name T41
Test name
Test status
Simulation time 7093288944 ps
CPU time 42.32 seconds
Started Aug 27 01:44:43 PM UTC 24
Finished Aug 27 01:45:27 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562194182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.562194182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_smoke.1574623494
Short name T145
Test name
Test status
Simulation time 618933167 ps
CPU time 12.58 seconds
Started Aug 27 01:44:31 PM UTC 24
Finished Aug 27 01:44:45 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574623494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1574623494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/6.hmac_stress_all_with_rand_reset.3986036973
Short name T19
Test name
Test status
Simulation time 58230747580 ps
CPU time 314.5 seconds
Started Aug 27 01:45:01 PM UTC 24
Finished Aug 27 01:50:20 PM UTC 24
Peak memory 411820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39860369
73 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3986036973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_alert_test.695328998
Short name T168
Test name
Test status
Simulation time 25159103 ps
CPU time 0.9 seconds
Started Aug 27 01:45:46 PM UTC 24
Finished Aug 27 01:45:48 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695328998 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.695328998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.4040332136
Short name T170
Test name
Test status
Simulation time 2567853368 ps
CPU time 49.62 seconds
Started Aug 27 01:45:21 PM UTC 24
Finished Aug 27 01:46:12 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040332136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4040332136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.2774313197
Short name T160
Test name
Test status
Simulation time 3680827285 ps
CPU time 43.74 seconds
Started Aug 27 01:45:26 PM UTC 24
Finished Aug 27 01:46:12 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774313197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2774313197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.2830205789
Short name T246
Test name
Test status
Simulation time 2142768823 ps
CPU time 436.94 seconds
Started Aug 27 01:45:26 PM UTC 24
Finished Aug 27 01:52:49 PM UTC 24
Peak memory 653552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830205789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2830205789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_error.162287558
Short name T188
Test name
Test status
Simulation time 17842911416 ps
CPU time 136.88 seconds
Started Aug 27 01:45:29 PM UTC 24
Finished Aug 27 01:47:48 PM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162287558 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.162287558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_long_msg.4151324624
Short name T174
Test name
Test status
Simulation time 43841571313 ps
CPU time 80 seconds
Started Aug 27 01:45:12 PM UTC 24
Finished Aug 27 01:46:34 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151324624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4151324624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_smoke.2751381171
Short name T42
Test name
Test status
Simulation time 1945356688 ps
CPU time 20.26 seconds
Started Aug 27 01:45:09 PM UTC 24
Finished Aug 27 01:45:31 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751381171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2751381171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_stress_all.95046357
Short name T256
Test name
Test status
Simulation time 34098758844 ps
CPU time 499.03 seconds
Started Aug 27 01:45:37 PM UTC 24
Finished Aug 27 01:54:03 PM UTC 24
Peak memory 282892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95046357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.95046357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3954934791
Short name T124
Test name
Test status
Simulation time 13970276646 ps
CPU time 81.36 seconds
Started Aug 27 01:45:33 PM UTC 24
Finished Aug 27 01:46:56 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954934791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3954934791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_alert_test.735091589
Short name T171
Test name
Test status
Simulation time 12058354 ps
CPU time 0.91 seconds
Started Aug 27 01:46:11 PM UTC 24
Finished Aug 27 01:46:13 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735091589 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.735091589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.3915905714
Short name T173
Test name
Test status
Simulation time 364102412 ps
CPU time 21.43 seconds
Started Aug 27 01:45:55 PM UTC 24
Finished Aug 27 01:46:18 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915905714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3915905714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.515407272
Short name T180
Test name
Test status
Simulation time 24644620460 ps
CPU time 62.72 seconds
Started Aug 27 01:45:57 PM UTC 24
Finished Aug 27 01:47:01 PM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515407272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.515407272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.3282197477
Short name T216
Test name
Test status
Simulation time 1855956002 ps
CPU time 297.79 seconds
Started Aug 27 01:45:57 PM UTC 24
Finished Aug 27 01:50:58 PM UTC 24
Peak memory 692584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282197477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3282197477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_error.3758676298
Short name T203
Test name
Test status
Simulation time 76822982880 ps
CPU time 227.68 seconds
Started Aug 27 01:45:59 PM UTC 24
Finished Aug 27 01:49:50 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758676298 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3758676298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_long_msg.790935342
Short name T150
Test name
Test status
Simulation time 5631698512 ps
CPU time 82.02 seconds
Started Aug 27 01:45:53 PM UTC 24
Finished Aug 27 01:47:17 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790935342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.790935342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_smoke.2846054129
Short name T149
Test name
Test status
Simulation time 94469383 ps
CPU time 5.15 seconds
Started Aug 27 01:45:50 PM UTC 24
Finished Aug 27 01:45:56 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846054129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2846054129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_stress_all.1235067064
Short name T526
Test name
Test status
Simulation time 42366426485 ps
CPU time 6068.69 seconds
Started Aug 27 01:46:02 PM UTC 24
Finished Aug 27 03:28:09 PM UTC 24
Peak memory 942392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235067064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1235067064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.3036123369
Short name T74
Test name
Test status
Simulation time 5362621487 ps
CPU time 213.46 seconds
Started Aug 27 01:46:10 PM UTC 24
Finished Aug 27 01:49:47 PM UTC 24
Peak memory 391452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30361233
69 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.3036123369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.1624378928
Short name T177
Test name
Test status
Simulation time 623288419 ps
CPU time 37.28 seconds
Started Aug 27 01:46:00 PM UTC 24
Finished Aug 27 01:46:39 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624378928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1624378928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_alert_test.304501855
Short name T176
Test name
Test status
Simulation time 16624760 ps
CPU time 0.8 seconds
Started Aug 27 01:46:37 PM UTC 24
Finished Aug 27 01:46:39 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304501855 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.304501855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.270054662
Short name T186
Test name
Test status
Simulation time 1520043279 ps
CPU time 83.09 seconds
Started Aug 27 01:46:14 PM UTC 24
Finished Aug 27 01:47:39 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270054662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.270054662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.2534292902
Short name T57
Test name
Test status
Simulation time 2907367560 ps
CPU time 27.34 seconds
Started Aug 27 01:46:19 PM UTC 24
Finished Aug 27 01:46:48 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534292902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2534292902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.3336726876
Short name T296
Test name
Test status
Simulation time 6503406545 ps
CPU time 698.8 seconds
Started Aug 27 01:46:15 PM UTC 24
Finished Aug 27 01:58:02 PM UTC 24
Peak memory 778544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336726876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3336726876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_error.2852755804
Short name T179
Test name
Test status
Simulation time 364689823 ps
CPU time 22.3 seconds
Started Aug 27 01:46:29 PM UTC 24
Finished Aug 27 01:46:53 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852755804 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2852755804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_long_msg.2031961704
Short name T187
Test name
Test status
Simulation time 6421256523 ps
CPU time 85.59 seconds
Started Aug 27 01:46:14 PM UTC 24
Finished Aug 27 01:47:42 PM UTC 24
Peak memory 215268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031961704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2031961704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_smoke.2994716504
Short name T172
Test name
Test status
Simulation time 23690562 ps
CPU time 1.16 seconds
Started Aug 27 01:46:12 PM UTC 24
Finished Aug 27 01:46:14 PM UTC 24
Peak memory 205456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994716504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2994716504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1165374256
Short name T184
Test name
Test status
Simulation time 1472263931 ps
CPU time 32.41 seconds
Started Aug 27 01:46:36 PM UTC 24
Finished Aug 27 01:47:09 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165374256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1165374256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.2717699668
Short name T34
Test name
Test status
Simulation time 11848085695 ps
CPU time 129.64 seconds
Started Aug 27 01:46:36 PM UTC 24
Finished Aug 27 01:48:48 PM UTC 24
Peak memory 218200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27176996
68 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2717699668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.2083130460
Short name T126
Test name
Test status
Simulation time 21505971116 ps
CPU time 108.05 seconds
Started Aug 27 01:46:31 PM UTC 24
Finished Aug 27 01:48:22 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083130460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2083130460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/hmac-sim-vcs/9.hmac_wipe_secret/latest
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