Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17357234	1			T3	1159		T4	322		T5	900
all_values[1]	17357234	1			T3	1159		T4	322		T5	900
all_values[2]	17357234	1			T3	1159		T4	322		T5	900

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212482

1

T5

20

T6

526

T8

134

auto[1]

51859220

1

T3

3477

T4

966

T5

2680

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44320189

1

T3

3235

T4

766

T5

2351

auto[1]

7751513

1

T3

242

T4

200

T5

349

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	88809	1			T5	20		T8	67		T9	40
all_values[0]	auto[0]	auto[1]	283	1			T10	3		T11	2		T128	2
all_values[0]	auto[1]	auto[0]	17248977	1			T3	1141		T4	320		T5	878
all_values[0]	auto[1]	auto[1]	19165	1			T3	18		T4	2		T5	2
all_values[1]	auto[0]	auto[0]	60707	1			T6	526		T8	67		T7	191
all_values[1]	auto[0]	auto[1]	156	1			T20	1		T26	5		T57	1
all_values[1]	auto[1]	auto[0]	17296105	1			T3	1159		T4	322		T5	900
all_values[1]	auto[1]	auto[1]	266	1			T18	4		T20	3		T29	4
all_values[2]	auto[0]	auto[0]	27980	1			T7	678		T15	2		T19	1
all_values[2]	auto[0]	auto[1]	34547	1			T7	147		T14	373		T129	1
all_values[2]	auto[1]	auto[0]	9597611	1			T3	935		T4	124		T5	553
all_values[2]	auto[1]	auto[1]	7697096	1			T3	224		T4	198		T5	347