Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

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Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115997

1

T3

24

T5

2

T8

94

auto[1]

121840

1

T3

12

T4

2

T5

2

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	88195	1			T5	2		T8	53		T7	1
len_1026_2046	5885	1			T3	7		T8	11		T10	1
len_514_1022	2701	1			T8	3		T9	1		T13	21
len_2_510	5061	1			T8	3		T13	177		T31	1
len_2056	364	1			T144	2		T145	3		T146	2
len_2048	335	1			T11	1		T14	2		T42	2
len_2040	233	1			T3	1		T145	4		T146	1
len_1032	392	1			T3	3		T47	1		T146	6
len_1024	1804	1			T8	1		T9	1		T11	1
len_1016	187	1			T3	6		T146	4		T129	4
len_520	186	1			T3	1		T4	1		T9	2
len_512	325	1			T8	1		T42	2		T116	1
len_504	236	1			T9	1		T144	3		T145	2
len_8	2412	1			T16	2		T147	5		T148	1
len_0	10601	1			T8	34		T7	1		T9	4

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

107

1

T13

2

T14

1

T118

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	44947	1			T5	1		T8	41		T7	1
auto[0]	len_1026_2046	2871	1			T3	2		T8	5		T13	34
auto[0]	len_514_1022	1719	1			T9	1		T13	11		T42	7
auto[0]	len_2_510	2492	1			T8	1		T13	55		T31	1
auto[0]	len_2056	92	1			T145	1		T146	1		T149	2
auto[0]	len_2048	184	1			T14	2		T42	1		T145	3
auto[0]	len_2040	129	1			T3	1		T145	1		T129	2
auto[0]	len_1032	314	1			T3	3		T47	1		T146	3
auto[0]	len_1024	261	1			T9	1		T42	2		T145	2
auto[0]	len_1016	117	1			T3	5		T146	1		T129	1
auto[0]	len_520	88	1			T3	1		T9	2		T145	1
auto[0]	len_512	180	1			T42	1		T18	2		T146	1
auto[0]	len_504	126	1			T144	3		T145	1		T129	3
auto[0]	len_8	22	1			T150	1		T151	1		T152	1
auto[0]	len_0	4455	1			T7	1		T13	1		T144	2
auto[1]	len_2050_plus	43248	1			T5	1		T8	12		T10	2
auto[1]	len_1026_2046	3014	1			T3	5		T8	6		T10	1
auto[1]	len_514_1022	982	1			T8	3		T13	10		T31	1
auto[1]	len_2_510	2569	1			T8	2		T13	122		T42	6
auto[1]	len_2056	272	1			T144	2		T145	2		T146	1
auto[1]	len_2048	151	1			T11	1		T42	1		T145	3
auto[1]	len_2040	104	1			T145	3		T146	1		T129	1
auto[1]	len_1032	78	1			T146	3		T129	3		T153	1
auto[1]	len_1024	1543	1			T8	1		T11	1		T17	67
auto[1]	len_1016	70	1			T3	1		T146	3		T129	3
auto[1]	len_520	98	1			T4	1		T145	3		T146	2
auto[1]	len_512	145	1			T8	1		T42	1		T116	1
auto[1]	len_504	110	1			T9	1		T145	1		T129	3
auto[1]	len_8	2390	1			T16	2		T147	5		T148	1
auto[1]	len_0	6146	1			T8	34		T9	4		T13	21

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

59

1

T14

1

T154

1

T155

3

auto[1]

len_upper

48

1

T13

2

T118

1

T18

1