Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::save_and_restore_cg

Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

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Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	9	0	9	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size_cp	3	0	3	100.00	100	1	1	0
save_and_restore_cp	3	0	3	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sar_type_x_digest_size	9	0	9	100.00	100	1	1	0

Summary for Variable digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for digest_size_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	159	1			T3	1		T5	1		T13	2
sha2_384	169	1			T8	1		T10	1		T11	4
sha2_256	169	1			T3	1		T10	2		T13	1

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Summary for Variable save_and_restore_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for save_and_restore_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	166	1			T3	2		T5	1		T10	1
different_context	164	1			T10	1		T13	1		T16	1
same_context	167	1			T8	1		T10	1		T11	3

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Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	9	0	9	100.00

Automatically Generated Cross Bins for sar_type_x_digest_size

Bins

save_and_restore_cp	digest_size_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	sha2_512	47	1			T3	1		T5	1		T13	1
stop_and_continue	sha2_384	51	1			T11	1		T13	1		T18	1
stop_and_continue	sha2_256	68	1			T3	1		T10	1		T13	1
different_context	sha2_512	53	1			T13	1		T14	1		T42	1
different_context	sha2_384	58	1			T10	1		T18	1		T156	2
different_context	sha2_256	53	1			T16	1		T14	1		T154	1
same_context	sha2_512	59	1			T42	1		T156	1		T155	1
same_context	sha2_384	60	1			T8	1		T11	3		T15	1
same_context	sha2_256	48	1			T10	1		T18	1		T146	1