Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4429334

1

T3

131

T4

37

T5

6

auto[1]

2601424

1

T3

360

T4

133

T5

445

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2638017

1

T3

262

T4

96

T5

225

auto[1]

4392741

1

T3

229

T4

74

T5

226

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3203335

1

T3

252

T4

42

T5

219

auto[1]

3827423

1

T3

239

T4

128

T5

232

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4421862

1

T3

216

T4

44

T5

247

auto[1]

2608896

1

T3

275

T4

126

T5

204

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6391358	1			T3	426		T4	163		T5	446
fifo_depth[1]	110771	1			T3	11		T4	1		T5	4
fifo_depth[2]	80646	1			T3	6		T4	1		T5	1
fifo_depth[3]	63571	1			T3	10		T4	1		T6	28
fifo_depth[4]	57998	1			T3	10		T4	1		T6	23
fifo_depth[5]	46452	1			T3	6		T6	22		T8	3
fifo_depth[6]	37541	1			T3	9		T4	1		T6	13
fifo_depth[7]	24572	1			T3	3		T4	1		T6	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639400

1

T3

65

T4

7

T5

5

auto[1]

6391358

1

T3

426

T4

163

T5

446

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7020848

1

T3

491

T4

170

T5

451

auto[1]

9910

1

T18

1013

T20

240

T29

10

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28081

1

T3

10

T7

20

T13

23

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33015

1

T10

1

T11

1

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30951

1

T5

5

T8

23

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25564

1

T8

1

T9

4

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

116426

1

T7

15

T11

1

T12

27

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27245

1

T6

65

T13

30

T47

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

32165

1

T3

4

T13

10

T14

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

37312

1

T3

5

T10

1

T15

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40581

1

T8

4

T7

17

T15

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

38110

1

T10

1

T12

72

T13

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36239

1

T3

5

T4

7

T11

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35918

1

T3

28

T8

6

T12

85

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44924

1

T6

92

T17

243

T16

12

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

44019

1

T9

2

T31

15

T116

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40202

1

T3

13

T10

1

T13

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

28648

1

T13

13

T47

28

T16

253

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

159840

1

T3

34

T6

1

T7

361

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

170689

1

T9

20

T13

287

T15

355

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

175074

1

T3

36

T4

28

T5

214

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

153749

1

T3

21

T8

16

T9

44

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1721604

1

T3

25

T7

279

T9

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

183138

1

T4

11

T6

222

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

156815

1

T3

49

T9

11

T11

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

151667

1

T3

68

T4

3

T9

43

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

457887

1

T3

1

T5

6

T8

51

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

396976

1

T3

61

T11

1

T12

291

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

450145

1

T3

16

T4

7

T9

13

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

405198

1

T3

50

T4

54

T8

48

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

533046

1

T6

166

T9

18

T17

2890

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

433753

1

T4

26

T7

20

T9

15

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

397882

1

T3

23

T4

2

T5

22

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

443895

1

T3

42

T4

32

T5

204

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

186388

1

T3

44

T6

1

T7

381

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

202842

1

T9

20

T10

1

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

205481

1

T3

36

T4

28

T5

219

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

178609

1

T3

21

T8

17

T9

48

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1836803

1

T3

25

T7

294

T9

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

209820

1

T4

11

T6

287

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

188218

1

T3

53

T9

11

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

188088

1

T3

73

T4

3

T9

43

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

498106

1

T3

1

T5

6

T8

55

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

434726

1

T3

61

T10

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

486176

1

T3

21

T4

14

T9

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

440550

1

T3

78

T4

54

T8

54

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

577845

1

T6

258

T9

18

T17

3133

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

477570

1

T4

26

T7

20

T9

17

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

437282

1

T3

36

T4

2

T5

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

472344

1

T3

42

T4

32

T5

204

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1533

1

T157

1214

T158

1

T159

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

862

1

T18

524

T29

7

T160

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

544

1

T160

8

T158

23

T161

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

704

1

T160

1

T162

1

T157

431

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1227

1

T18

472

T20

10

T163

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

563

1

T18

1

T20

168

T157

14

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

762

1

T18

14

T84

1

T161

82

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

891

1

T160

7

T84

24

T44

13

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

362

1

T158

12

T161

86

T164

135

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

360

1

T20

4

T165

7

T166

96

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

208

1

T18

1

T84

7

T158

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

566

1

T20

58

T29

2

T160

14

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

125

1

T162

3

T165

13

T166

18

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

202

1

T18

1

T22

51

T157

16

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

802

1

T29

1

T160

56

T84

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

199

1

T162

70

T44

12

T164

6

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

159840

1

T3

34

T6

1

T7

361

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

170689

1

T9

20

T13

287

T15

355

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

175074

1

T3

36

T4

28

T5

214

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

153749

1

T3

21

T8

16

T9

44

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1721604

1

T3

25

T7

279

T9

12

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

183138

1

T4

11

T6

222

T7

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

156815

1

T3

49

T9

11

T11

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

151667

1

T3

68

T4

3

T9

43

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

457887

1

T3

1

T5

6

T8

51

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

396976

1

T3

61

T11

1

T12

291

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

450145

1

T3

16

T4

7

T9

13

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

405198

1

T3

50

T4

54

T8

48

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

533046

1

T6

166

T9

18

T17

2890

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

433753

1

T4

26

T7

20

T9

15

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

397882

1

T3

23

T4

2

T5

22

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

443895

1

T3

42

T4

32

T5

204

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3388

1

T3

2

T7

15

T13

3

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3544

1

T31

6

T42

2

T118

12

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3612

1

T5

4

T8

8

T10

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3513

1

T8

1

T9

2

T12

5

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

38213

1

T7

8

T12

8

T13

13

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3452

1

T6

11

T13

8

T47

7

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3008

1

T13

2

T65

35

T18

3

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3134

1

T3

1

T15

6

T42

12

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5867

1

T7

11

T15

6

T16

11

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5123

1

T12

16

T42

2

T118

24

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5372

1

T3

2

T4

1

T144

2

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5582

1

T3

5

T8

1

T12

15

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8116

1

T6

18

T17

139

T16

3

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7141

1

T9

1

T31

12

T116

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6509

1

T3

1

T13

1

T47

5

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5197

1

T47

22

T16

50

T116

2

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2562

1

T7

5

T13

13

T14

1

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[1]

2757

1

T42

2

T118

4

T18

6

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[0]

2766

1

T5

1

T8

4

T12

20

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[1]

2762

1

T9

2

T12

6

T13

4

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[0]

21772

1

T7

6

T12

9

T13

13

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[1]

2486

1

T6

13

T13

5

T42

1

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[0]

2411

1

T13

3

T65

15

T18

4

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[1]

2696

1

T15

4

T42

15

T118

1

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[0]

5143

1

T8

3

T7

4

T15

4

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[1]

4190

1

T12

15

T118

7

T19

17

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[0]

4444

1

T4

1

T144

2

T18

2

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[1]

4653

1

T3

4

T12

17

T15

3

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[0]

6523

1

T6

16

T17

79

T16

1

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[1]

6016

1

T9

1

T31

2

T64

112

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

5345

1

T3

2

T13

2

T47

3

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[1]

4120

1

T13

6

T47

4

T16

43

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[0]

2095

1

T3

3

T14

1

T42

12

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[1]

2144

1

T18

1

T129

3

T156

17

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[0]

2252

1

T8

5

T12

14

T116

4

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[1]

2138

1

T12

4

T118

1

T64

5

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[0]

14786

1

T7

1

T12

9

T15

2

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[1]

1877

1

T6

10

T13

4

T42

1

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[0]

1761

1

T3

1

T13

2

T65

5

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[1]

2065

1

T3

1

T42

11

T118

1

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

4538

1

T7

1

T15

1

T16

17

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

3669

1

T10

1

T12

14

T42

2

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[0]

3699

1

T3

1

T4

1

T144

1

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

4010

1

T3

3

T12

16

T15

3

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

5316

1

T6

18

T17

22

T117

9

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

5230

1

T31

1

T116

1

T64

112

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

4661

1

T3

1

T47

1

T42

1

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

3330

1

T47

2

T16

47

T42

3

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

1975

1

T3

1

T13

4

T42

9

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

2587

1

T42

7

T118

1

T18

7

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

2162

1

T8

2

T12

2

T31

1

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2180

1

T12

3

T13

1

T64

6

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

10648

1

T12

1

T64

21

T18

16

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

1654

1

T6

7

T13

3

T42

1

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[0]

2015

1

T3

1

T65

1

T18

2

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

2108

1

T3

1

T42

7

T64

4

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

4504

1

T8

1

T7

1

T16

19

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

3581

1

T12

5

T13

2

T129

2

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

3712

1

T4

1

T11

1

T144

2

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

3881

1

T3

6

T8

4

T12

11

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

4745

1

T6

16

T17

3

T16

1

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

4895

1

T116

1

T64

93

T18

1

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4333

1

T3

1

T13

1

T42

25

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

3018

1

T13

5

T16

35

T42

9

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1563

1

T3

1

T42

8

T64

7

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1867

1

T18

2

T129

2

T156

9

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1737

1

T8

3

T116

6

T64

10

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1802

1

T12

1

T13

3

T64

7

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

7253

1

T11

1

T64

13

T18

20

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[1]

1368

1

T6

8

T13

5

T64

20

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[0]

1313

1

T3

1

T13

1

T18

18

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[1]

1673

1

T42

6

T64

6

T18

70

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[0]

3775

1

T16

12

T116

2

T64

19

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[1]

3164

1

T12

10

T42

3

T19

1

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[0]

3072

1

T3

1

T144

2

T18

3

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[1]

3458

1

T3

2

T12

13

T146

2

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3967

1

T6

14

T16

1

T119

10

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

4227

1

T64

67

T18

2

T146

1

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[0]

3720

1

T3

1

T19

1

T146

3

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[1]

2493

1

T16

42

T42

1

T116

3

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1340

1

T3

2

T13

3

T42

7

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

1885

1

T42

2

T18

7

T129

1

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1453

1

T8

1

T116

5

T64

20

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1405

1

T13

1

T64

6

T18

2

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

5503

1

T64

13

T18

11

T129

1

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1135

1

T6

6

T13

3

T64

12

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[0]

1233

1

T13

1

T18

4

T167

16

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[1]

1313

1

T3

1

T42

2

T64

4

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

3033

1

T16

15

T64

21

T18

1

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2630

1

T12

7

T19

1

T129

1

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2635

1

T3

1

T4

1

T144

1

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

2809

1

T3

3

T12

11

T146

1

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

3038

1

T6

7

T16

1

T61

41

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

3396

1

T64

50

T18

3

T167

8

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

2822

1

T3

2

T10

1

T153

1

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

1911

1

T13

2

T16

18

T42

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

914

1

T3

1

T14

1

T64

5

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

1107

1

T10

1

T20

2

T123

2

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

943

1

T116

6

T64

11

T20

3

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

927

1

T11

1

T64

6

T18

3

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

3240

1

T64

7

T168

1

T167

9

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

726

1

T6

4

T13

2

T64

6

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

725

1

T13

1

T14

1

T18

18

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

994

1

T3

1

T10

1

T42

2

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

2104

1

T16

6

T14

1

T116

2

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1931

1

T12

1

T42

2

T129

1

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1691

1

T4

1

T144

2

T18

1

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

1938

1

T3

1

T12

2

T146

1

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

2069

1

T6

1

T16

3

T61

5

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

2213

1

T64

19

T18

1

T169

17

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

1753

1

T42

1

T146

1

T153

2

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1297

1

T16

8

T116

3

T129

2