Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17357234	1			T3	1159		T4	322		T5	900
all_pins[1]	17357234	1			T3	1159		T4	322		T5	900
all_pins[2]	17357234	1			T3	1159		T4	322		T5	900

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44354333	1			T3	3232		T4	766		T5	2351
values[0x1]	7717369	1			T3	245		T4	200		T5	349
transitions[0x0=>0x1]	7717226	1			T3	245		T4	200		T5	349
transitions[0x1=>0x0]	7717241	1			T3	245		T4	200		T5	349

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17337249	1			T3	1138		T4	320		T5	898
all_pins[0]	values[0x1]	19985	1			T3	21		T4	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	19921	1			T3	21		T4	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	7697047	1			T3	224		T4	198		T5	347
all_pins[1]	values[0x0]	17356946	1			T3	1159		T4	322		T5	900
all_pins[1]	values[0x1]	288	1			T18	4		T20	4		T29	4
all_pins[1]	transitions[0x0=>0x1]	252	1			T18	4		T20	3		T29	4
all_pins[1]	transitions[0x1=>0x0]	19949	1			T3	21		T4	2		T5	2
all_pins[2]	values[0x0]	9660138	1			T3	935		T4	124		T5	553
all_pins[2]	values[0x1]	7697096	1			T3	224		T4	198		T5	347
all_pins[2]	transitions[0x0=>0x1]	7697053	1			T3	224		T4	198		T5	347
all_pins[2]	transitions[0x1=>0x0]	245	1			T18	4		T20	4		T29	4