Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 753 1 T20 7 T26 7 T57 8
all_values[1] 753 1 T20 7 T26 7 T57 8
all_values[2] 753 1 T20 7 T26 7 T57 8


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1133 1 T20 9 T26 11 T57 9
auto[1] 1126 1 T20 12 T26 10 T57 15


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 809 1 T20 13 T26 2 T57 6
auto[1] 1450 1 T20 8 T26 19 T57 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1281 1 T20 15 T26 10 T57 13
auto[1] 978 1 T20 6 T26 11 T57 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 165 1 T20 3 T130 5 T131 5
all_values[0] auto[0] auto[0] auto[1] 68 1 T26 3 T57 2 T132 2
all_values[0] auto[0] auto[1] auto[0] 133 1 T20 1 T57 1 T132 7
all_values[0] auto[0] auto[1] auto[1] 70 1 T20 1 T26 2 T57 1
all_values[0] auto[1] auto[0] auto[1] 170 1 T26 1 T57 3 T132 3
all_values[0] auto[1] auto[1] auto[1] 147 1 T20 2 T26 1 T57 1
all_values[1] auto[0] auto[0] auto[0] 117 1 T20 1 T132 1 T130 2
all_values[1] auto[0] auto[0] auto[1] 88 1 T26 1 T57 1 T132 2
all_values[1] auto[0] auto[1] auto[0] 123 1 T20 3 T26 1 T57 2
all_values[1] auto[0] auto[1] auto[1] 94 1 T20 1 T57 1 T132 3
all_values[1] auto[1] auto[0] auto[1] 158 1 T26 4 T57 1 T130 3
all_values[1] auto[1] auto[1] auto[1] 173 1 T20 2 T26 1 T57 3
all_values[2] auto[0] auto[0] auto[0] 138 1 T20 4 T132 3 T130 2
all_values[2] auto[0] auto[0] auto[1] 73 1 T26 1 T57 1 T132 1
all_values[2] auto[0] auto[1] auto[0] 133 1 T20 1 T26 1 T57 3
all_values[2] auto[0] auto[1] auto[1] 79 1 T26 1 T57 1 T130 4
all_values[2] auto[1] auto[0] auto[1] 156 1 T20 1 T26 1 T57 1
all_values[2] auto[1] auto[1] auto[1] 174 1 T20 1 T26 3 T57 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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