Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4031	1			T3	2		T4	2		T5	1
sha2_none	4154	1			T3	6		T4	5		T7	2
sha2_512	7414	1			T3	6		T4	1		T5	2
sha2_384	7167	1			T3	2		T4	1		T6	1
sha2_256	6082	1			T3	4		T4	1		T5	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18425

1

T3

7

T4

2

T5

1

auto[1]

10821

1

T3

13

T4

8

T5

3

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10834

1

T3

11

T4

3

T5

2

auto[1]

18412

1

T3

9

T4

7

T5

2

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15176

1

T3

9

T4

7

T5

3

disabled

14070

1

T3

11

T4

3

T5

1

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4439	1			T3	1		T5	1		T6	1
key_none	7655	1			T3	2		T4	2		T5	1
key_1024	4266	1			T3	1		T4	2		T5	2
key_512	3755	1			T3	6		T4	2		T9	2
key_384	3194	1			T3	4		T4	2		T7	1
key_256	2961	1			T3	5		T6	1		T8	3
key_128	2906	1			T3	1		T4	2		T6	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18555

1

T3

10

T4

4

T5

3

auto[1]

10691

1

T3

10

T4

6

T5

1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29044

1

T3

20

T4

10

T5

4

disabled

202

1

T12

2

T46

1

T47

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1558

1

T3

1

T5

1

T8

1

enabled

auto[0]

auto[0]

auto[1]

1503

1

T3

3

T10

1

T11

1

enabled

auto[0]

auto[1]

auto[0]

1548

1

T3

1

T4

1

T9

2

enabled

auto[0]

auto[1]

auto[1]

1522

1

T3

2

T4

1

T8

2

enabled

auto[1]

auto[0]

auto[0]

4346

1

T6

1

T9

1

T17

135

enabled

auto[1]

auto[0]

auto[1]

1522

1

T4

1

T7

1

T9

1

enabled

auto[1]

auto[1]

auto[0]

1644

1

T3

1

T4

2

T5

1

enabled

auto[1]

auto[1]

auto[1]

1533

1

T3

1

T4

2

T5

1

disabled

auto[0]

auto[0]

auto[0]

1172

1

T3

1

T6

1

T7

1

disabled

auto[0]

auto[0]

auto[1]

1163

1

T9

1

T10

1

T11

1

disabled

auto[0]

auto[1]

auto[0]

1198

1

T3

2

T4

1

T5

1

disabled

auto[0]

auto[1]

auto[1]

1170

1

T3

1

T8

1

T9

1

disabled

auto[1]

auto[0]

auto[0]

5984

1

T3

2

T7

1

T9

1

disabled

auto[1]

auto[0]

auto[1]

1177

1

T4

1

T6

1

T7

1

disabled

auto[1]

auto[1]

auto[0]

1105

1

T3

2

T9

1

T11

1

disabled

auto[1]

auto[1]

auto[1]

1101

1

T3

3

T4

1

T9

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15107

1

T3

9

T4

7

T5

3

enabled

disabled

69

1

T12

1

T47

1

T143

1

disabled

disabled

133

1

T12

1

T46

1

T20

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13937

1

T3

11

T4

3

T5

1

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1068	1			T5	1		T6	1		T11	1
key_invalid	sha2_none	859	1			T11	1		T12	1		T13	2
key_invalid	sha2_512	816	1			T3	1		T7	2		T9	1
key_invalid	sha2_384	805	1			T9	2		T10	2		T11	1
key_invalid	sha2_256	784	1			T9	2		T10	1		T13	1
key_none	sha2_invalid	495	1			T13	2		T144	2		T116	1
key_none	sha2_none	526	1			T4	2		T7	1		T11	1
key_none	sha2_512	2507	1			T5	1		T10	1		T12	3
key_none	sha2_384	2497	1			T9	1		T10	1		T12	1
key_none	sha2_256	1581	1			T3	2		T8	1		T7	1
key_1024	sha2_invalid	492	1			T11	1		T16	1		T42	3
key_1024	sha2_none	541	1			T4	1		T7	1		T13	4
key_1024	sha2_512	1736	1			T3	1		T5	1		T9	1
key_1024	sha2_384	863	1			T11	3		T12	1		T13	3
key_512	sha2_invalid	523	1			T4	1		T9	1		T15	1
key_512	sha2_none	558	1			T3	3		T4	1		T10	1
key_512	sha2_512	593	1			T3	1		T9	1		T13	1
key_512	sha2_384	1197	1			T3	2		T10	1		T11	2
key_512	sha2_256	834	1			T17	45		T13	1		T42	1
key_384	sha2_invalid	486	1			T3	1		T4	1		T12	1
key_384	sha2_none	543	1			T3	1		T4	1		T11	1
key_384	sha2_512	556	1			T3	2		T7	1		T11	1
key_384	sha2_384	562	1			T11	3		T16	1		T14	1
key_384	sha2_256	1005	1			T9	1		T10	2		T17	90
key_256	sha2_invalid	489	1			T13	1		T46	1		T16	1
key_256	sha2_none	554	1			T3	2		T9	1		T10	1
key_256	sha2_512	580	1			T3	1		T8	1		T12	1
key_256	sha2_384	612	1			T6	1		T8	2		T10	1
key_256	sha2_256	678	1			T3	2		T13	2		T15	2
key_128	sha2_invalid	457	1			T3	1		T12	1		T13	1
key_128	sha2_none	562	1			T9	1		T10	1		T13	2
key_128	sha2_512	615	1			T4	1		T8	1		T12	1
key_128	sha2_384	617	1			T4	1		T8	1		T12	3
key_128	sha2_256	604	1			T6	1		T11	1		T16	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

587

1

T4

1

T5

1

T9

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1068	1			T5	1		T6	1		T11	1
key_invalid	sha2_none	859	1			T11	1		T12	1		T13	2
key_invalid	sha2_512	816	1			T3	1		T7	2		T9	1
key_invalid	sha2_384	805	1			T9	2		T10	2		T11	1
key_invalid	sha2_256	784	1			T9	2		T10	1		T13	1
key_none	sha2_invalid	495	1			T13	2		T144	2		T116	1
key_none	sha2_none	526	1			T4	2		T7	1		T11	1
key_none	sha2_512	2507	1			T5	1		T10	1		T12	3
key_none	sha2_384	2497	1			T9	1		T10	1		T12	1
key_none	sha2_256	1581	1			T3	2		T8	1		T7	1
key_1024	sha2_invalid	492	1			T11	1		T16	1		T42	3
key_1024	sha2_none	541	1			T4	1		T7	1		T13	4
key_1024	sha2_512	1736	1			T3	1		T5	1		T9	1
key_1024	sha2_384	863	1			T11	3		T12	1		T13	3
key_1024	sha2_256	587	1			T4	1		T5	1		T9	1
key_512	sha2_invalid	523	1			T4	1		T9	1		T15	1
key_512	sha2_none	558	1			T3	3		T4	1		T10	1
key_512	sha2_512	593	1			T3	1		T9	1		T13	1
key_512	sha2_384	1197	1			T3	2		T10	1		T11	2
key_512	sha2_256	834	1			T17	45		T13	1		T42	1
key_384	sha2_invalid	486	1			T3	1		T4	1		T12	1
key_384	sha2_none	543	1			T3	1		T4	1		T11	1
key_384	sha2_512	556	1			T3	2		T7	1		T11	1
key_384	sha2_384	562	1			T11	3		T16	1		T14	1
key_384	sha2_256	1005	1			T9	1		T10	2		T17	90
key_256	sha2_invalid	489	1			T13	1		T46	1		T16	1
key_256	sha2_none	554	1			T3	2		T9	1		T10	1
key_256	sha2_512	580	1			T3	1		T8	1		T12	1
key_256	sha2_384	612	1			T6	1		T8	2		T10	1
key_256	sha2_256	678	1			T3	2		T13	2		T15	2
key_128	sha2_invalid	457	1			T3	1		T12	1		T13	1
key_128	sha2_none	562	1			T9	1		T10	1		T13	2
key_128	sha2_512	615	1			T4	1		T8	1		T12	1
key_128	sha2_384	617	1			T4	1		T8	1		T12	3
key_128	sha2_256	604	1			T6	1		T11	1		T16	2