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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85


Total test records in report: 654
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T60 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.635391562 Aug 29 07:37:24 AM UTC 24 Aug 29 07:37:28 AM UTC 24 43274144 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.4256976991 Aug 29 07:37:22 AM UTC 24 Aug 29 07:37:28 AM UTC 24 388114996 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1424118865 Aug 29 07:37:26 AM UTC 24 Aug 29 07:37:29 AM UTC 24 16605394 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.4026614587 Aug 29 07:37:20 AM UTC 24 Aug 29 07:37:29 AM UTC 24 385768405 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1254173584 Aug 29 07:37:24 AM UTC 24 Aug 29 07:37:29 AM UTC 24 375138730 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.477897858 Aug 29 07:37:28 AM UTC 24 Aug 29 07:37:30 AM UTC 24 25921945 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.4101301017 Aug 29 07:37:28 AM UTC 24 Aug 29 07:37:30 AM UTC 24 133196733 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.75113200 Aug 29 07:37:26 AM UTC 24 Aug 29 07:37:30 AM UTC 24 90593364 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.481407125 Aug 29 07:37:24 AM UTC 24 Aug 29 07:37:32 AM UTC 24 106731926 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.489074201 Aug 29 07:37:30 AM UTC 24 Aug 29 07:37:33 AM UTC 24 83736511 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.295264038 Aug 29 07:37:31 AM UTC 24 Aug 29 07:37:33 AM UTC 24 44054431 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3370703599 Aug 29 07:37:30 AM UTC 24 Aug 29 07:37:33 AM UTC 24 121860494 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3965355232 Aug 29 07:37:31 AM UTC 24 Aug 29 07:37:34 AM UTC 24 30905988 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.2741482811 Aug 29 07:37:31 AM UTC 24 Aug 29 07:37:34 AM UTC 24 37931791 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1471543031 Aug 29 07:37:31 AM UTC 24 Aug 29 07:37:35 AM UTC 24 178416363 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.675689399 Aug 29 07:37:30 AM UTC 24 Aug 29 07:37:35 AM UTC 24 644456915 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1411061116 Aug 29 07:37:33 AM UTC 24 Aug 29 07:37:36 AM UTC 24 44812376 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3966942264 Aug 29 07:37:35 AM UTC 24 Aug 29 07:37:36 AM UTC 24 68952161 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.828255927 Aug 29 07:37:33 AM UTC 24 Aug 29 07:37:37 AM UTC 24 748369443 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2612338361 Aug 29 07:37:36 AM UTC 24 Aug 29 07:37:38 AM UTC 24 28882103 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3696497422 Aug 29 07:37:29 AM UTC 24 Aug 29 07:37:38 AM UTC 24 752602508 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.3177741533 Aug 29 07:37:36 AM UTC 24 Aug 29 07:37:38 AM UTC 24 123692071 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4059299031 Aug 29 07:37:24 AM UTC 24 Aug 29 07:37:40 AM UTC 24 1575529038 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.4012227239 Aug 29 07:37:20 AM UTC 24 Aug 29 07:37:40 AM UTC 24 3412449520 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1749008230 Aug 29 07:37:34 AM UTC 24 Aug 29 07:37:41 AM UTC 24 285022569 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.535426799 Aug 29 07:37:37 AM UTC 24 Aug 29 07:37:41 AM UTC 24 119018751 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.1155038570 Aug 29 07:37:39 AM UTC 24 Aug 29 07:37:41 AM UTC 24 17901797 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1756474122 Aug 29 07:37:35 AM UTC 24 Aug 29 07:37:41 AM UTC 24 446166471 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.3616021522 Aug 29 07:37:39 AM UTC 24 Aug 29 07:37:42 AM UTC 24 37688001 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1596928439 Aug 29 07:37:36 AM UTC 24 Aug 29 07:37:42 AM UTC 24 183688480 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.786123438 Aug 29 07:37:38 AM UTC 24 Aug 29 07:37:42 AM UTC 24 97895317 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.538274934 Aug 29 07:37:41 AM UTC 24 Aug 29 07:37:43 AM UTC 24 18886577 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1803534267 Aug 29 07:37:41 AM UTC 24 Aug 29 07:37:44 AM UTC 24 23272314 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1558909572 Aug 29 07:37:40 AM UTC 24 Aug 29 07:37:45 AM UTC 24 412199593 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1994891776 Aug 29 07:37:43 AM UTC 24 Aug 29 07:37:45 AM UTC 24 145376236 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2961945844 Aug 29 07:37:33 AM UTC 24 Aug 29 07:37:45 AM UTC 24 1853722204 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1967168633 Aug 29 07:37:43 AM UTC 24 Aug 29 07:37:45 AM UTC 24 492573741 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3421833833 Aug 29 07:37:43 AM UTC 24 Aug 29 07:37:46 AM UTC 24 37653409 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.3298191258 Aug 29 07:37:39 AM UTC 24 Aug 29 07:37:46 AM UTC 24 3714461394 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3212364762 Aug 29 07:37:41 AM UTC 24 Aug 29 07:37:46 AM UTC 24 70140892 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3107994178 Aug 29 07:37:41 AM UTC 24 Aug 29 07:37:47 AM UTC 24 406710963 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.932626251 Aug 29 07:37:45 AM UTC 24 Aug 29 07:37:47 AM UTC 24 13432639 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1593636290 Aug 29 07:37:44 AM UTC 24 Aug 29 07:37:48 AM UTC 24 270000145 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2130225125 Aug 29 07:37:32 AM UTC 24 Aug 29 07:37:48 AM UTC 24 1602307925 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3707530768 Aug 29 07:37:29 AM UTC 24 Aug 29 07:37:48 AM UTC 24 1210871312 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3216931212 Aug 29 07:37:46 AM UTC 24 Aug 29 07:37:48 AM UTC 24 34017707 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2200522543 Aug 29 07:37:43 AM UTC 24 Aug 29 07:37:48 AM UTC 24 57254081 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.164196056 Aug 29 07:37:46 AM UTC 24 Aug 29 07:37:49 AM UTC 24 35733801 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.254521293 Aug 29 07:37:48 AM UTC 24 Aug 29 07:37:50 AM UTC 24 23413766 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.4234264667 Aug 29 07:37:48 AM UTC 24 Aug 29 07:37:50 AM UTC 24 32774317 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3100615541 Aug 29 07:37:52 AM UTC 24 Aug 29 07:37:55 AM UTC 24 580963488 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2101598159 Aug 29 07:37:46 AM UTC 24 Aug 29 07:37:50 AM UTC 24 50731262 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3281547169 Aug 29 07:37:48 AM UTC 24 Aug 29 07:37:51 AM UTC 24 64980345 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.2670713454 Aug 29 07:37:50 AM UTC 24 Aug 29 07:37:52 AM UTC 24 48237537 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.2628459985 Aug 29 07:37:50 AM UTC 24 Aug 29 07:37:52 AM UTC 24 13013354 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.568388067 Aug 29 07:37:48 AM UTC 24 Aug 29 07:37:52 AM UTC 24 51741674 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4125806749 Aug 29 07:37:36 AM UTC 24 Aug 29 07:37:52 AM UTC 24 10046201641 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3649957084 Aug 29 07:37:51 AM UTC 24 Aug 29 07:37:53 AM UTC 24 112296192 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.82267577 Aug 29 07:37:50 AM UTC 24 Aug 29 07:37:53 AM UTC 24 74404748 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.2238022130 Aug 29 07:37:51 AM UTC 24 Aug 29 07:37:53 AM UTC 24 23046891 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.796362133 Aug 29 07:37:51 AM UTC 24 Aug 29 07:37:54 AM UTC 24 188240815 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.3329040777 Aug 29 07:37:48 AM UTC 24 Aug 29 07:37:54 AM UTC 24 194574607 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1841988395 Aug 29 07:37:50 AM UTC 24 Aug 29 07:37:55 AM UTC 24 188933646 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.2802388787 Aug 29 07:37:53 AM UTC 24 Aug 29 07:37:55 AM UTC 24 18299753 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.394819977 Aug 29 07:37:48 AM UTC 24 Aug 29 07:37:55 AM UTC 24 224481311 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2500048919 Aug 29 07:37:53 AM UTC 24 Aug 29 07:37:55 AM UTC 24 25818329 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.2846185621 Aug 29 07:37:52 AM UTC 24 Aug 29 07:37:55 AM UTC 24 66631340 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1574052449 Aug 29 07:37:52 AM UTC 24 Aug 29 07:37:56 AM UTC 24 26669961 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.335294530 Aug 29 07:37:52 AM UTC 24 Aug 29 07:37:56 AM UTC 24 164718882 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1515472646 Aug 29 07:37:51 AM UTC 24 Aug 29 07:37:57 AM UTC 24 890970053 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.830805085 Aug 29 07:37:56 AM UTC 24 Aug 29 07:37:58 AM UTC 24 59943429 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2445699761 Aug 29 07:37:55 AM UTC 24 Aug 29 07:37:58 AM UTC 24 855167308 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.557740324 Aug 29 07:37:56 AM UTC 24 Aug 29 07:37:58 AM UTC 24 55982371 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1620454331 Aug 29 07:37:54 AM UTC 24 Aug 29 07:37:58 AM UTC 24 62756563 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.430461299 Aug 29 07:37:54 AM UTC 24 Aug 29 07:37:59 AM UTC 24 454758294 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1603886034 Aug 29 07:37:57 AM UTC 24 Aug 29 07:37:59 AM UTC 24 27186811 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.252117309 Aug 29 07:37:56 AM UTC 24 Aug 29 07:37:59 AM UTC 24 106757411 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1000754713 Aug 29 07:37:57 AM UTC 24 Aug 29 07:37:59 AM UTC 24 29250604 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3348253594 Aug 29 07:37:56 AM UTC 24 Aug 29 07:38:01 AM UTC 24 41223388 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2780486638 Aug 29 07:37:57 AM UTC 24 Aug 29 07:38:01 AM UTC 24 95137223 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.742161936 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:01 AM UTC 24 12860006 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1459623004 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:02 AM UTC 24 56639785 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.710965283 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:02 AM UTC 24 64211828 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2648048674 Aug 29 07:37:56 AM UTC 24 Aug 29 07:38:02 AM UTC 24 375041133 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.900930743 Aug 29 07:37:56 AM UTC 24 Aug 29 07:38:03 AM UTC 24 444154379 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.846780261 Aug 29 07:37:56 AM UTC 24 Aug 29 07:38:03 AM UTC 24 135225007 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.5717483 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:03 AM UTC 24 93654238 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2643478160 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:03 AM UTC 24 131587258 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.905530652 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:04 AM UTC 24 446721814 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3204467148 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:04 AM UTC 24 73653709 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2621426726 Aug 29 07:38:01 AM UTC 24 Aug 29 07:38:04 AM UTC 24 112893806 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1248315674 Aug 29 07:38:02 AM UTC 24 Aug 29 07:38:04 AM UTC 24 35348151 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3539229995 Aug 29 07:38:02 AM UTC 24 Aug 29 07:38:05 AM UTC 24 37685121 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.256009590 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:05 AM UTC 24 82281502 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2354174349 Aug 29 07:38:03 AM UTC 24 Aug 29 07:38:05 AM UTC 24 13445952 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.1504056673 Aug 29 07:38:04 AM UTC 24 Aug 29 07:38:05 AM UTC 24 28713820 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1137930464 Aug 29 07:38:03 AM UTC 24 Aug 29 07:38:06 AM UTC 24 17293738 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2910955736 Aug 29 07:38:04 AM UTC 24 Aug 29 07:38:06 AM UTC 24 37973570 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.291377189 Aug 29 07:38:04 AM UTC 24 Aug 29 07:38:06 AM UTC 24 25670123 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2137389411 Aug 29 07:38:00 AM UTC 24 Aug 29 07:38:06 AM UTC 24 368839251 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.433281072 Aug 29 07:38:04 AM UTC 24 Aug 29 07:38:07 AM UTC 24 62145589 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2798188771 Aug 29 07:38:02 AM UTC 24 Aug 29 07:38:07 AM UTC 24 269634893 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3468243960 Aug 29 07:38:05 AM UTC 24 Aug 29 07:38:07 AM UTC 24 91471512 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2988563779 Aug 29 07:38:03 AM UTC 24 Aug 29 07:38:07 AM UTC 24 166850674 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2366081667 Aug 29 07:38:04 AM UTC 24 Aug 29 07:38:09 AM UTC 24 167717843 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2513528012 Aug 29 07:38:07 AM UTC 24 Aug 29 07:38:09 AM UTC 24 57956794 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2770936363 Aug 29 07:38:07 AM UTC 24 Aug 29 07:38:09 AM UTC 24 129804696 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.888022432 Aug 29 07:38:05 AM UTC 24 Aug 29 07:38:10 AM UTC 24 156516464 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.1458183072 Aug 29 07:38:08 AM UTC 24 Aug 29 07:38:10 AM UTC 24 22856380 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.3117358558 Aug 29 07:38:08 AM UTC 24 Aug 29 07:38:10 AM UTC 24 54925017 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3331507629 Aug 29 07:38:08 AM UTC 24 Aug 29 07:38:10 AM UTC 24 18196674 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.1025564364 Aug 29 07:38:05 AM UTC 24 Aug 29 07:38:10 AM UTC 24 665352461 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2875025180 Aug 29 07:38:08 AM UTC 24 Aug 29 07:38:10 AM UTC 24 25089846 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.3934508102 Aug 29 07:38:03 AM UTC 24 Aug 29 07:38:11 AM UTC 24 227672699 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.230752466 Aug 29 07:38:07 AM UTC 24 Aug 29 07:38:11 AM UTC 24 545965056 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.28632184 Aug 29 07:38:09 AM UTC 24 Aug 29 07:38:11 AM UTC 24 93801077 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1361925030 Aug 29 07:38:09 AM UTC 24 Aug 29 07:38:11 AM UTC 24 45622375 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.2302708262 Aug 29 07:38:09 AM UTC 24 Aug 29 07:38:11 AM UTC 24 37731283 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3956814647 Aug 29 07:37:21 AM UTC 24 Aug 29 07:38:12 AM UTC 24 3730496886 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2394461367 Aug 29 07:38:08 AM UTC 24 Aug 29 07:38:12 AM UTC 24 438122191 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.2555606696 Aug 29 07:38:07 AM UTC 24 Aug 29 07:38:12 AM UTC 24 281021113 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3555027318 Aug 29 07:38:05 AM UTC 24 Aug 29 07:38:13 AM UTC 24 448962540 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.1246529259 Aug 29 07:38:11 AM UTC 24 Aug 29 07:38:13 AM UTC 24 44420921 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2719969865 Aug 29 07:38:08 AM UTC 24 Aug 29 07:38:13 AM UTC 24 117476759 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1606089169 Aug 29 07:38:11 AM UTC 24 Aug 29 07:38:13 AM UTC 24 43197160 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.2201517199 Aug 29 07:38:11 AM UTC 24 Aug 29 07:38:13 AM UTC 24 23430275 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2117295240 Aug 29 07:38:11 AM UTC 24 Aug 29 07:38:13 AM UTC 24 49409217 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3725597652 Aug 29 07:38:11 AM UTC 24 Aug 29 07:38:13 AM UTC 24 121642715 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1628247355 Aug 29 07:38:07 AM UTC 24 Aug 29 07:38:13 AM UTC 24 124193618 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1013924063 Aug 29 07:38:12 AM UTC 24 Aug 29 07:38:14 AM UTC 24 56152149 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.561570117 Aug 29 07:38:12 AM UTC 24 Aug 29 07:38:14 AM UTC 24 13350737 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2043283438 Aug 29 07:38:12 AM UTC 24 Aug 29 07:38:14 AM UTC 24 52949843 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.45311694 Aug 29 07:38:12 AM UTC 24 Aug 29 07:38:14 AM UTC 24 11526880 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3037579898 Aug 29 07:38:12 AM UTC 24 Aug 29 07:38:14 AM UTC 24 11240931 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.159378623 Aug 29 07:38:12 AM UTC 24 Aug 29 07:38:14 AM UTC 24 15538900 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2209580648 Aug 29 07:38:13 AM UTC 24 Aug 29 07:38:15 AM UTC 24 11441646 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.3796665703 Aug 29 07:38:13 AM UTC 24 Aug 29 07:38:15 AM UTC 24 46045026 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3894324897 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:15 AM UTC 24 56863813 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3380493587 Aug 29 07:38:13 AM UTC 24 Aug 29 07:38:15 AM UTC 24 11935079 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.726379104 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:16 AM UTC 24 24658727 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1649231901 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:16 AM UTC 24 26146428 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.1335714073 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:16 AM UTC 24 23635997 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.3497878709 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:16 AM UTC 24 83166350 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.1624582480 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:16 AM UTC 24 19087058 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.691479118 Aug 29 07:38:14 AM UTC 24 Aug 29 07:38:16 AM UTC 24 19110115 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2210165482 Aug 29 07:38:15 AM UTC 24 Aug 29 07:38:17 AM UTC 24 11171188 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.2558566936 Aug 29 07:38:15 AM UTC 24 Aug 29 07:38:17 AM UTC 24 13232353 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.2589463879 Aug 29 07:38:15 AM UTC 24 Aug 29 07:38:17 AM UTC 24 12923166 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1179989122 Aug 29 07:37:37 AM UTC 24 Aug 29 07:39:25 AM UTC 24 21431536183 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.800049517 Aug 29 07:38:05 AM UTC 24 Aug 29 07:43:30 AM UTC 24 219016541079 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1000227123 Aug 29 07:37:46 AM UTC 24 Aug 29 07:45:05 AM UTC 24 95356073211 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1132518782 Aug 29 07:38:07 AM UTC 24 Aug 29 07:53:15 AM UTC 24 107084667723 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3439633344 Aug 29 07:37:48 AM UTC 24 Aug 29 07:56:03 AM UTC 24 236702438922 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1917091010 Aug 29 07:37:57 AM UTC 24 Aug 29 07:56:05 AM UTC 24 159016178087 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_smoke.2241522743
Short name T3
Test name
Test status
Simulation time 151353122 ps
CPU time 6.13 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:32:39 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241522743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2241522743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.1560480270
Short name T14
Test name
Test status
Simulation time 2870673037 ps
CPU time 52.76 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:33:30 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560480270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1560480270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3103129915
Short name T20
Test name
Test status
Simulation time 2148720030 ps
CPU time 106.15 seconds
Started Aug 28 09:34:48 PM UTC 24
Finished Aug 28 09:36:36 PM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31031299
15 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3103129915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.2857647082
Short name T18
Test name
Test status
Simulation time 1912528866 ps
CPU time 53.5 seconds
Started Aug 28 09:33:55 PM UTC 24
Finished Aug 28 09:34:50 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857647082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2857647082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_smoke.458215764
Short name T145
Test name
Test status
Simulation time 1449685361 ps
CPU time 15.69 seconds
Started Aug 28 09:33:50 PM UTC 24
Finished Aug 28 09:34:07 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458215764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.458215764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.1427996856
Short name T54
Test name
Test status
Simulation time 254156070 ps
CPU time 5.88 seconds
Started Aug 29 07:37:16 AM UTC 24
Finished Aug 29 07:37:23 AM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427996856 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1427996856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.3111714733
Short name T21
Test name
Test status
Simulation time 61563307779 ps
CPU time 801.65 seconds
Started Aug 28 09:33:45 PM UTC 24
Finished Aug 28 09:47:16 PM UTC 24
Peak memory 543128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31117147
33 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3111714733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.1117148141
Short name T28
Test name
Test status
Simulation time 431918226 ps
CPU time 1.48 seconds
Started Aug 28 09:32:45 PM UTC 24
Finished Aug 28 09:32:48 PM UTC 24
Peak memory 235560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117148141 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1117148141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.2482498028
Short name T31
Test name
Test status
Simulation time 2296573959 ps
CPU time 30.89 seconds
Started Aug 28 09:32:58 PM UTC 24
Finished Aug 28 09:33:30 PM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482498028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2482498028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_stress_all.2012465683
Short name T25
Test name
Test status
Simulation time 23659149697 ps
CPU time 1509.11 seconds
Started Aug 28 09:44:47 PM UTC 24
Finished Aug 28 10:10:12 PM UTC 24
Peak memory 465184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012465683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2012465683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_error.121503526
Short name T12
Test name
Test status
Simulation time 8593935988 ps
CPU time 135.97 seconds
Started Aug 28 09:33:56 PM UTC 24
Finished Aug 28 09:36:15 PM UTC 24
Peak memory 207372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121503526 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.121503526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.4026614587
Short name T95
Test name
Test status
Simulation time 385768405 ps
CPU time 8.03 seconds
Started Aug 29 07:37:20 AM UTC 24
Finished Aug 29 07:37:29 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026614587 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4026614587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.2801047969
Short name T16
Test name
Test status
Simulation time 1978678698 ps
CPU time 53.88 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:33:27 PM UTC 24
Peak memory 250004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801047969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2801047969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3107994178
Short name T133
Test name
Test status
Simulation time 406710963 ps
CPU time 3.98 seconds
Started Aug 29 07:37:41 AM UTC 24
Finished Aug 29 07:37:47 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107994178 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3107994178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.2288561051
Short name T19
Test name
Test status
Simulation time 5610775693 ps
CPU time 118.54 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:34:36 PM UTC 24
Peak memory 358672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22885610
51 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2288561051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_stress_all.398009409
Short name T57
Test name
Test status
Simulation time 31431968791 ps
CPU time 443.18 seconds
Started Aug 28 09:33:40 PM UTC 24
Finished Aug 28 09:41:09 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398009409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.398009409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_alert_test.3065613343
Short name T27
Test name
Test status
Simulation time 15460132 ps
CPU time 0.88 seconds
Started Aug 28 09:32:45 PM UTC 24
Finished Aug 28 09:32:48 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065613343 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3065613343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.900930743
Short name T140
Test name
Test status
Simulation time 444154379 ps
CPU time 5.6 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:38:03 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900930743 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.900930743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.2057917020
Short name T212
Test name
Test status
Simulation time 2383951167 ps
CPU time 55.47 seconds
Started Aug 28 09:37:39 PM UTC 24
Finished Aug 28 09:38:36 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057917020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2057917020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.4026523188
Short name T110
Test name
Test status
Simulation time 31708242 ps
CPU time 1.48 seconds
Started Aug 29 07:37:18 AM UTC 24
Finished Aug 29 07:37:21 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026523188 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4026523188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.3712228295
Short name T11
Test name
Test status
Simulation time 2316116520 ps
CPU time 37.54 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:33:11 PM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712228295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3712228295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.2960830032
Short name T150
Test name
Test status
Simulation time 49612840046 ps
CPU time 651.64 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:43:36 PM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960830032 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2960830032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_stress_all.2173409322
Short name T32
Test name
Test status
Simulation time 114425236727 ps
CPU time 4344.59 seconds
Started Aug 28 09:37:01 PM UTC 24
Finished Aug 28 10:50:12 PM UTC 24
Peak memory 801148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173409322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2173409322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_stress_all.3596905572
Short name T495
Test name
Test status
Simulation time 18804941059 ps
CPU time 1816.81 seconds
Started Aug 28 09:37:30 PM UTC 24
Finished Aug 28 10:08:06 PM UTC 24
Peak memory 708840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596905572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3596905572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.2479322592
Short name T26
Test name
Test status
Simulation time 13957149209 ps
CPU time 219.69 seconds
Started Aug 28 09:36:29 PM UTC 24
Finished Aug 28 09:40:12 PM UTC 24
Peak memory 244140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24793225
92 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2479322592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.4012227239
Short name T103
Test name
Test status
Simulation time 3412449520 ps
CPU time 19.22 seconds
Started Aug 29 07:37:20 AM UTC 24
Finished Aug 29 07:37:40 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012227239 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4012227239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3104149486
Short name T531
Test name
Test status
Simulation time 61633781 ps
CPU time 1.12 seconds
Started Aug 29 07:37:17 AM UTC 24
Finished Aug 29 07:37:19 AM UTC 24
Peak memory 205928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104149486 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3104149486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3956814647
Short name T619
Test name
Test status
Simulation time 3730496886 ps
CPU time 49.4 seconds
Started Aug 29 07:37:21 AM UTC 24
Finished Aug 29 07:38:12 AM UTC 24
Peak memory 224308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3956814647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.3956814647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.3998224577
Short name T75
Test name
Test status
Simulation time 53943326 ps
CPU time 0.85 seconds
Started Aug 29 07:37:17 AM UTC 24
Finished Aug 29 07:37:19 AM UTC 24
Peak memory 204712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998224577 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3998224577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1914270688
Short name T111
Test name
Test status
Simulation time 53714505 ps
CPU time 1.75 seconds
Started Aug 29 07:37:21 AM UTC 24
Finished Aug 29 07:37:23 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914270688 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.1914270688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.4121778813
Short name T58
Test name
Test status
Simulation time 187353270 ps
CPU time 5.35 seconds
Started Aug 29 07:37:15 AM UTC 24
Finished Aug 29 07:37:22 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121778813 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.4121778813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.481407125
Short name T97
Test name
Test status
Simulation time 106731926 ps
CPU time 6.52 seconds
Started Aug 29 07:37:24 AM UTC 24
Finished Aug 29 07:37:32 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481407125 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.481407125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4059299031
Short name T102
Test name
Test status
Simulation time 1575529038 ps
CPU time 14.28 seconds
Started Aug 29 07:37:24 AM UTC 24
Finished Aug 29 07:37:40 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059299031 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4059299031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2635333553
Short name T94
Test name
Test status
Simulation time 70060649 ps
CPU time 1.44 seconds
Started Aug 29 07:37:23 AM UTC 24
Finished Aug 29 07:37:26 AM UTC 24
Peak memory 206632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635333553 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2635333553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1254173584
Short name T85
Test name
Test status
Simulation time 375138730 ps
CPU time 3.67 seconds
Started Aug 29 07:37:24 AM UTC 24
Finished Aug 29 07:37:29 AM UTC 24
Peak memory 217984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1254173584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.1254173584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.2144779148
Short name T533
Test name
Test status
Simulation time 29702918 ps
CPU time 1.01 seconds
Started Aug 29 07:37:23 AM UTC 24
Finished Aug 29 07:37:25 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144779148 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2144779148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1942876510
Short name T532
Test name
Test status
Simulation time 13854323 ps
CPU time 0.91 seconds
Started Aug 29 07:37:22 AM UTC 24
Finished Aug 29 07:37:24 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942876510 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1942876510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2814532323
Short name T112
Test name
Test status
Simulation time 164162537 ps
CPU time 1.34 seconds
Started Aug 29 07:37:24 AM UTC 24
Finished Aug 29 07:37:27 AM UTC 24
Peak memory 206848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814532323 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.2814532323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2519548514
Short name T59
Test name
Test status
Simulation time 132193975 ps
CPU time 3.4 seconds
Started Aug 29 07:37:22 AM UTC 24
Finished Aug 29 07:37:26 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519548514 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2519548514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.4256976991
Short name T55
Test name
Test status
Simulation time 388114996 ps
CPU time 5.08 seconds
Started Aug 29 07:37:22 AM UTC 24
Finished Aug 29 07:37:28 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256976991 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4256976991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1574052449
Short name T572
Test name
Test status
Simulation time 26669961 ps
CPU time 2.54 seconds
Started Aug 29 07:37:52 AM UTC 24
Finished Aug 29 07:37:56 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1574052449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.1574052449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.2238022130
Short name T565
Test name
Test status
Simulation time 23046891 ps
CPU time 1.29 seconds
Started Aug 29 07:37:51 AM UTC 24
Finished Aug 29 07:37:53 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238022130 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2238022130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3649957084
Short name T563
Test name
Test status
Simulation time 112296192 ps
CPU time 0.82 seconds
Started Aug 29 07:37:51 AM UTC 24
Finished Aug 29 07:37:53 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649957084 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3649957084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3100615541
Short name T557
Test name
Test status
Simulation time 580963488 ps
CPU time 1.83 seconds
Started Aug 29 07:37:52 AM UTC 24
Finished Aug 29 07:37:55 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100615541 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.3100615541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1515472646
Short name T574
Test name
Test status
Simulation time 890970053 ps
CPU time 5.09 seconds
Started Aug 29 07:37:51 AM UTC 24
Finished Aug 29 07:37:57 AM UTC 24
Peak memory 207872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515472646 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1515472646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.796362133
Short name T566
Test name
Test status
Simulation time 188240815 ps
CPU time 2.08 seconds
Started Aug 29 07:37:51 AM UTC 24
Finished Aug 29 07:37:54 AM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796362133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.796362133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1620454331
Short name T578
Test name
Test status
Simulation time 62756563 ps
CPU time 3.01 seconds
Started Aug 29 07:37:54 AM UTC 24
Finished Aug 29 07:37:58 AM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1620454331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.1620454331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2500048919
Short name T570
Test name
Test status
Simulation time 25818329 ps
CPU time 1.03 seconds
Started Aug 29 07:37:53 AM UTC 24
Finished Aug 29 07:37:55 AM UTC 24
Peak memory 205980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500048919 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2500048919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.2802388787
Short name T568
Test name
Test status
Simulation time 18299753 ps
CPU time 0.88 seconds
Started Aug 29 07:37:53 AM UTC 24
Finished Aug 29 07:37:55 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802388787 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2802388787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.430461299
Short name T579
Test name
Test status
Simulation time 454758294 ps
CPU time 3.55 seconds
Started Aug 29 07:37:54 AM UTC 24
Finished Aug 29 07:37:59 AM UTC 24
Peak memory 208008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430461299 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.430461299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.2846185621
Short name T571
Test name
Test status
Simulation time 66631340 ps
CPU time 2.36 seconds
Started Aug 29 07:37:52 AM UTC 24
Finished Aug 29 07:37:55 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846185621 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2846185621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.335294530
Short name T573
Test name
Test status
Simulation time 164718882 ps
CPU time 2.71 seconds
Started Aug 29 07:37:52 AM UTC 24
Finished Aug 29 07:37:56 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335294530 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.335294530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3348253594
Short name T583
Test name
Test status
Simulation time 41223388 ps
CPU time 3.66 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:38:01 AM UTC 24
Peak memory 217968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3348253594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.3348253594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.557740324
Short name T577
Test name
Test status
Simulation time 55982371 ps
CPU time 1.38 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:37:58 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557740324 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.557740324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.830805085
Short name T575
Test name
Test status
Simulation time 59943429 ps
CPU time 0.91 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:37:58 AM UTC 24
Peak memory 203556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830805085 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.830805085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.252117309
Short name T581
Test name
Test status
Simulation time 106757411 ps
CPU time 2.19 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:37:59 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252117309 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.252117309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2445699761
Short name T576
Test name
Test status
Simulation time 855167308 ps
CPU time 2.48 seconds
Started Aug 29 07:37:55 AM UTC 24
Finished Aug 29 07:37:58 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445699761 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2445699761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.846780261
Short name T141
Test name
Test status
Simulation time 135225007 ps
CPU time 5.92 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:38:03 AM UTC 24
Peak memory 207872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846780261 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.846780261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1917091010
Short name T654
Test name
Test status
Simulation time 159016178087 ps
CPU time 1074.42 seconds
Started Aug 29 07:37:57 AM UTC 24
Finished Aug 29 07:56:05 AM UTC 24
Peak memory 232700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1917091010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.1917091010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1000754713
Short name T582
Test name
Test status
Simulation time 29250604 ps
CPU time 1.23 seconds
Started Aug 29 07:37:57 AM UTC 24
Finished Aug 29 07:37:59 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000754713 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1000754713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1603886034
Short name T580
Test name
Test status
Simulation time 27186811 ps
CPU time 0.92 seconds
Started Aug 29 07:37:57 AM UTC 24
Finished Aug 29 07:37:59 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603886034 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1603886034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2780486638
Short name T584
Test name
Test status
Simulation time 95137223 ps
CPU time 2.72 seconds
Started Aug 29 07:37:57 AM UTC 24
Finished Aug 29 07:38:01 AM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780486638 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.2780486638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2648048674
Short name T588
Test name
Test status
Simulation time 375041133 ps
CPU time 5.28 seconds
Started Aug 29 07:37:56 AM UTC 24
Finished Aug 29 07:38:02 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648048674 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2648048674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3204467148
Short name T592
Test name
Test status
Simulation time 73653709 ps
CPU time 2.9 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:04 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3204467148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.3204467148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1459623004
Short name T586
Test name
Test status
Simulation time 56639785 ps
CPU time 1.02 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:02 AM UTC 24
Peak memory 205716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459623004 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1459623004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.742161936
Short name T585
Test name
Test status
Simulation time 12860006 ps
CPU time 0.87 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:01 AM UTC 24
Peak memory 203472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742161936 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.742161936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2643478160
Short name T590
Test name
Test status
Simulation time 131587258 ps
CPU time 2.21 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:03 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643478160 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.2643478160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.5717483
Short name T589
Test name
Test status
Simulation time 93654238 ps
CPU time 2.31 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:03 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5717483 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.5717483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.256009590
Short name T134
Test name
Test status
Simulation time 82281502 ps
CPU time 4.08 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:05 AM UTC 24
Peak memory 207980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256009590 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.256009590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3539229995
Short name T595
Test name
Test status
Simulation time 37685121 ps
CPU time 2.04 seconds
Started Aug 29 07:38:02 AM UTC 24
Finished Aug 29 07:38:05 AM UTC 24
Peak memory 207848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3539229995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.3539229995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2621426726
Short name T593
Test name
Test status
Simulation time 112893806 ps
CPU time 1.35 seconds
Started Aug 29 07:38:01 AM UTC 24
Finished Aug 29 07:38:04 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621426726 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2621426726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.710965283
Short name T587
Test name
Test status
Simulation time 64211828 ps
CPU time 0.92 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:02 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710965283 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.710965283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1248315674
Short name T594
Test name
Test status
Simulation time 35348151 ps
CPU time 1.7 seconds
Started Aug 29 07:38:02 AM UTC 24
Finished Aug 29 07:38:04 AM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248315674 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.1248315674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2137389411
Short name T601
Test name
Test status
Simulation time 368839251 ps
CPU time 5.57 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:06 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137389411 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2137389411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.905530652
Short name T591
Test name
Test status
Simulation time 446721814 ps
CPU time 2.7 seconds
Started Aug 29 07:38:00 AM UTC 24
Finished Aug 29 07:38:04 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905530652 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.905530652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.291377189
Short name T600
Test name
Test status
Simulation time 25670123 ps
CPU time 1.86 seconds
Started Aug 29 07:38:04 AM UTC 24
Finished Aug 29 07:38:06 AM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=291377189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_r
eset.291377189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1137930464
Short name T598
Test name
Test status
Simulation time 17293738 ps
CPU time 1.34 seconds
Started Aug 29 07:38:03 AM UTC 24
Finished Aug 29 07:38:06 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137930464 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1137930464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2354174349
Short name T596
Test name
Test status
Simulation time 13445952 ps
CPU time 0.9 seconds
Started Aug 29 07:38:03 AM UTC 24
Finished Aug 29 07:38:05 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354174349 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2354174349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2988563779
Short name T605
Test name
Test status
Simulation time 166850674 ps
CPU time 2.71 seconds
Started Aug 29 07:38:03 AM UTC 24
Finished Aug 29 07:38:07 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988563779 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.2988563779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2798188771
Short name T603
Test name
Test status
Simulation time 269634893 ps
CPU time 3.88 seconds
Started Aug 29 07:38:02 AM UTC 24
Finished Aug 29 07:38:07 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798188771 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2798188771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.3934508102
Short name T614
Test name
Test status
Simulation time 227672699 ps
CPU time 6.25 seconds
Started Aug 29 07:38:03 AM UTC 24
Finished Aug 29 07:38:11 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934508102 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3934508102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.800049517
Short name T650
Test name
Test status
Simulation time 219016541079 ps
CPU time 320.61 seconds
Started Aug 29 07:38:05 AM UTC 24
Finished Aug 29 07:43:30 AM UTC 24
Peak memory 218428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=800049517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_r
eset.800049517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2910955736
Short name T599
Test name
Test status
Simulation time 37973570 ps
CPU time 1.06 seconds
Started Aug 29 07:38:04 AM UTC 24
Finished Aug 29 07:38:06 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910955736 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2910955736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.1504056673
Short name T597
Test name
Test status
Simulation time 28713820 ps
CPU time 0.82 seconds
Started Aug 29 07:38:04 AM UTC 24
Finished Aug 29 07:38:05 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504056673 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1504056673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.888022432
Short name T608
Test name
Test status
Simulation time 156516464 ps
CPU time 3.62 seconds
Started Aug 29 07:38:05 AM UTC 24
Finished Aug 29 07:38:10 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888022432 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.888022432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.433281072
Short name T602
Test name
Test status
Simulation time 62145589 ps
CPU time 1.88 seconds
Started Aug 29 07:38:04 AM UTC 24
Finished Aug 29 07:38:07 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433281072 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.433281072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2366081667
Short name T138
Test name
Test status
Simulation time 167717843 ps
CPU time 3.88 seconds
Started Aug 29 07:38:04 AM UTC 24
Finished Aug 29 07:38:09 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366081667 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2366081667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1132518782
Short name T652
Test name
Test status
Simulation time 107084667723 ps
CPU time 896.27 seconds
Started Aug 29 07:38:07 AM UTC 24
Finished Aug 29 07:53:15 AM UTC 24
Peak memory 218360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1132518782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.1132518782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2770936363
Short name T607
Test name
Test status
Simulation time 129804696 ps
CPU time 1.29 seconds
Started Aug 29 07:38:07 AM UTC 24
Finished Aug 29 07:38:09 AM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770936363 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2770936363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3468243960
Short name T604
Test name
Test status
Simulation time 91471512 ps
CPU time 0.74 seconds
Started Aug 29 07:38:05 AM UTC 24
Finished Aug 29 07:38:07 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468243960 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3468243960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.230752466
Short name T615
Test name
Test status
Simulation time 545965056 ps
CPU time 3.37 seconds
Started Aug 29 07:38:07 AM UTC 24
Finished Aug 29 07:38:11 AM UTC 24
Peak memory 207916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230752466 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.230752466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.1025564364
Short name T612
Test name
Test status
Simulation time 665352461 ps
CPU time 4.23 seconds
Started Aug 29 07:38:05 AM UTC 24
Finished Aug 29 07:38:10 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025564364 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1025564364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3555027318
Short name T622
Test name
Test status
Simulation time 448962540 ps
CPU time 6.46 seconds
Started Aug 29 07:38:05 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 207936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555027318 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3555027318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2719969865
Short name T624
Test name
Test status
Simulation time 117476759 ps
CPU time 3.49 seconds
Started Aug 29 07:38:08 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 209836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2719969865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.2719969865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2875025180
Short name T613
Test name
Test status
Simulation time 25089846 ps
CPU time 1.29 seconds
Started Aug 29 07:38:08 AM UTC 24
Finished Aug 29 07:38:10 AM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875025180 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2875025180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2513528012
Short name T606
Test name
Test status
Simulation time 57956794 ps
CPU time 0.72 seconds
Started Aug 29 07:38:07 AM UTC 24
Finished Aug 29 07:38:09 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513528012 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2513528012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2394461367
Short name T620
Test name
Test status
Simulation time 438122191 ps
CPU time 2.89 seconds
Started Aug 29 07:38:08 AM UTC 24
Finished Aug 29 07:38:12 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394461367 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.2394461367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.2555606696
Short name T621
Test name
Test status
Simulation time 281021113 ps
CPU time 4.38 seconds
Started Aug 29 07:38:07 AM UTC 24
Finished Aug 29 07:38:12 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555606696 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2555606696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1628247355
Short name T629
Test name
Test status
Simulation time 124193618 ps
CPU time 5.36 seconds
Started Aug 29 07:38:07 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628247355 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1628247355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3696497422
Short name T100
Test name
Test status
Simulation time 752602508 ps
CPU time 8.08 seconds
Started Aug 29 07:37:29 AM UTC 24
Finished Aug 29 07:37:38 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696497422 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3696497422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3707530768
Short name T106
Test name
Test status
Simulation time 1210871312 ps
CPU time 18.19 seconds
Started Aug 29 07:37:29 AM UTC 24
Finished Aug 29 07:37:48 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707530768 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3707530768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.4101301017
Short name T535
Test name
Test status
Simulation time 133196733 ps
CPU time 1.36 seconds
Started Aug 29 07:37:28 AM UTC 24
Finished Aug 29 07:37:30 AM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101301017 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.4101301017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3370703599
Short name T86
Test name
Test status
Simulation time 121860494 ps
CPU time 2.48 seconds
Started Aug 29 07:37:30 AM UTC 24
Finished Aug 29 07:37:33 AM UTC 24
Peak memory 218040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3370703599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.3370703599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.477897858
Short name T96
Test name
Test status
Simulation time 25921945 ps
CPU time 1.22 seconds
Started Aug 29 07:37:28 AM UTC 24
Finished Aug 29 07:37:30 AM UTC 24
Peak memory 206532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477897858 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.477897858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1424118865
Short name T534
Test name
Test status
Simulation time 16605394 ps
CPU time 0.92 seconds
Started Aug 29 07:37:26 AM UTC 24
Finished Aug 29 07:37:29 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424118865 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1424118865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.489074201
Short name T113
Test name
Test status
Simulation time 83736511 ps
CPU time 1.74 seconds
Started Aug 29 07:37:30 AM UTC 24
Finished Aug 29 07:37:33 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489074201 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.489074201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.635391562
Short name T60
Test name
Test status
Simulation time 43274144 ps
CPU time 1.93 seconds
Started Aug 29 07:37:24 AM UTC 24
Finished Aug 29 07:37:28 AM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635391562 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.635391562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.75113200
Short name T56
Test name
Test status
Simulation time 90593364 ps
CPU time 2.52 seconds
Started Aug 29 07:37:26 AM UTC 24
Finished Aug 29 07:37:30 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75113200 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.75113200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.1458183072
Short name T609
Test name
Test status
Simulation time 22856380 ps
CPU time 0.89 seconds
Started Aug 29 07:38:08 AM UTC 24
Finished Aug 29 07:38:10 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458183072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1458183072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.3117358558
Short name T610
Test name
Test status
Simulation time 54925017 ps
CPU time 0.91 seconds
Started Aug 29 07:38:08 AM UTC 24
Finished Aug 29 07:38:10 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117358558 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3117358558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3331507629
Short name T611
Test name
Test status
Simulation time 18196674 ps
CPU time 0.92 seconds
Started Aug 29 07:38:08 AM UTC 24
Finished Aug 29 07:38:10 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331507629 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3331507629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.28632184
Short name T616
Test name
Test status
Simulation time 93801077 ps
CPU time 0.95 seconds
Started Aug 29 07:38:09 AM UTC 24
Finished Aug 29 07:38:11 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28632184 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.28632184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.2302708262
Short name T618
Test name
Test status
Simulation time 37731283 ps
CPU time 0.88 seconds
Started Aug 29 07:38:09 AM UTC 24
Finished Aug 29 07:38:11 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302708262 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2302708262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1361925030
Short name T617
Test name
Test status
Simulation time 45622375 ps
CPU time 0.88 seconds
Started Aug 29 07:38:09 AM UTC 24
Finished Aug 29 07:38:11 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361925030 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1361925030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1606089169
Short name T625
Test name
Test status
Simulation time 43197160 ps
CPU time 0.9 seconds
Started Aug 29 07:38:11 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606089169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1606089169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.1246529259
Short name T623
Test name
Test status
Simulation time 44420921 ps
CPU time 0.87 seconds
Started Aug 29 07:38:11 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246529259 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1246529259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.2201517199
Short name T626
Test name
Test status
Simulation time 23430275 ps
CPU time 0.93 seconds
Started Aug 29 07:38:11 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201517199 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2201517199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3725597652
Short name T628
Test name
Test status
Simulation time 121642715 ps
CPU time 0.88 seconds
Started Aug 29 07:38:11 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725597652 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3725597652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2961945844
Short name T548
Test name
Test status
Simulation time 1853722204 ps
CPU time 10.69 seconds
Started Aug 29 07:37:33 AM UTC 24
Finished Aug 29 07:37:45 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961945844 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2961945844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2130225125
Short name T553
Test name
Test status
Simulation time 1602307925 ps
CPU time 14.69 seconds
Started Aug 29 07:37:32 AM UTC 24
Finished Aug 29 07:37:48 AM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130225125 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2130225125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3965355232
Short name T537
Test name
Test status
Simulation time 30905988 ps
CPU time 1.31 seconds
Started Aug 29 07:37:31 AM UTC 24
Finished Aug 29 07:37:34 AM UTC 24
Peak memory 206780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965355232 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3965355232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1411061116
Short name T539
Test name
Test status
Simulation time 44812376 ps
CPU time 1.85 seconds
Started Aug 29 07:37:33 AM UTC 24
Finished Aug 29 07:37:36 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1411061116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.1411061116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.2741482811
Short name T98
Test name
Test status
Simulation time 37931791 ps
CPU time 1.47 seconds
Started Aug 29 07:37:31 AM UTC 24
Finished Aug 29 07:37:34 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741482811 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2741482811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.295264038
Short name T536
Test name
Test status
Simulation time 44054431 ps
CPU time 0.88 seconds
Started Aug 29 07:37:31 AM UTC 24
Finished Aug 29 07:37:33 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295264038 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.295264038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.828255927
Short name T114
Test name
Test status
Simulation time 748369443 ps
CPU time 2.49 seconds
Started Aug 29 07:37:33 AM UTC 24
Finished Aug 29 07:37:37 AM UTC 24
Peak memory 207920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828255927 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.828255927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.675689399
Short name T538
Test name
Test status
Simulation time 644456915 ps
CPU time 3.78 seconds
Started Aug 29 07:37:30 AM UTC 24
Finished Aug 29 07:37:35 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675689399 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.675689399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1471543031
Short name T135
Test name
Test status
Simulation time 178416363 ps
CPU time 2.78 seconds
Started Aug 29 07:37:31 AM UTC 24
Finished Aug 29 07:37:35 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471543031 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1471543031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2117295240
Short name T627
Test name
Test status
Simulation time 49409217 ps
CPU time 0.87 seconds
Started Aug 29 07:38:11 AM UTC 24
Finished Aug 29 07:38:13 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117295240 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2117295240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2043283438
Short name T632
Test name
Test status
Simulation time 52949843 ps
CPU time 0.89 seconds
Started Aug 29 07:38:12 AM UTC 24
Finished Aug 29 07:38:14 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043283438 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2043283438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1013924063
Short name T630
Test name
Test status
Simulation time 56152149 ps
CPU time 0.85 seconds
Started Aug 29 07:38:12 AM UTC 24
Finished Aug 29 07:38:14 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013924063 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1013924063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.561570117
Short name T631
Test name
Test status
Simulation time 13350737 ps
CPU time 0.88 seconds
Started Aug 29 07:38:12 AM UTC 24
Finished Aug 29 07:38:14 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561570117 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.561570117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.45311694
Short name T633
Test name
Test status
Simulation time 11526880 ps
CPU time 0.88 seconds
Started Aug 29 07:38:12 AM UTC 24
Finished Aug 29 07:38:14 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45311694 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.45311694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3037579898
Short name T634
Test name
Test status
Simulation time 11240931 ps
CPU time 0.83 seconds
Started Aug 29 07:38:12 AM UTC 24
Finished Aug 29 07:38:14 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037579898 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3037579898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.159378623
Short name T635
Test name
Test status
Simulation time 15538900 ps
CPU time 0.88 seconds
Started Aug 29 07:38:12 AM UTC 24
Finished Aug 29 07:38:14 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159378623 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.159378623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.3796665703
Short name T637
Test name
Test status
Simulation time 46045026 ps
CPU time 0.9 seconds
Started Aug 29 07:38:13 AM UTC 24
Finished Aug 29 07:38:15 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796665703 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3796665703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2209580648
Short name T636
Test name
Test status
Simulation time 11441646 ps
CPU time 0.79 seconds
Started Aug 29 07:38:13 AM UTC 24
Finished Aug 29 07:38:15 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209580648 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2209580648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3380493587
Short name T639
Test name
Test status
Simulation time 11935079 ps
CPU time 0.94 seconds
Started Aug 29 07:38:13 AM UTC 24
Finished Aug 29 07:38:15 AM UTC 24
Peak memory 202920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380493587 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3380493587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1596928439
Short name T543
Test name
Test status
Simulation time 183688480 ps
CPU time 4.75 seconds
Started Aug 29 07:37:36 AM UTC 24
Finished Aug 29 07:37:42 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596928439 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1596928439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4125806749
Short name T109
Test name
Test status
Simulation time 10046201641 ps
CPU time 15.08 seconds
Started Aug 29 07:37:36 AM UTC 24
Finished Aug 29 07:37:52 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125806749 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4125806749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.3177741533
Short name T101
Test name
Test status
Simulation time 123692071 ps
CPU time 1.38 seconds
Started Aug 29 07:37:36 AM UTC 24
Finished Aug 29 07:37:38 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177741533 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3177741533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1179989122
Short name T649
Test name
Test status
Simulation time 21431536183 ps
CPU time 105.84 seconds
Started Aug 29 07:37:37 AM UTC 24
Finished Aug 29 07:39:25 AM UTC 24
Peak memory 218092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1179989122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.1179989122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2612338361
Short name T99
Test name
Test status
Simulation time 28882103 ps
CPU time 1.24 seconds
Started Aug 29 07:37:36 AM UTC 24
Finished Aug 29 07:37:38 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612338361 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2612338361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3966942264
Short name T540
Test name
Test status
Simulation time 68952161 ps
CPU time 0.91 seconds
Started Aug 29 07:37:35 AM UTC 24
Finished Aug 29 07:37:36 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966942264 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3966942264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.535426799
Short name T115
Test name
Test status
Simulation time 119018751 ps
CPU time 2.91 seconds
Started Aug 29 07:37:37 AM UTC 24
Finished Aug 29 07:37:41 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535426799 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.535426799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1749008230
Short name T541
Test name
Test status
Simulation time 285022569 ps
CPU time 5.01 seconds
Started Aug 29 07:37:34 AM UTC 24
Finished Aug 29 07:37:41 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749008230 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1749008230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1756474122
Short name T142
Test name
Test status
Simulation time 446166471 ps
CPU time 5.86 seconds
Started Aug 29 07:37:35 AM UTC 24
Finished Aug 29 07:37:41 AM UTC 24
Peak memory 207660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756474122 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1756474122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3894324897
Short name T638
Test name
Test status
Simulation time 56863813 ps
CPU time 0.93 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:15 AM UTC 24
Peak memory 205252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894324897 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3894324897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.726379104
Short name T640
Test name
Test status
Simulation time 24658727 ps
CPU time 0.9 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:16 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726379104 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.726379104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1649231901
Short name T641
Test name
Test status
Simulation time 26146428 ps
CPU time 0.87 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:16 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649231901 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1649231901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.1335714073
Short name T642
Test name
Test status
Simulation time 23635997 ps
CPU time 0.89 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:16 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335714073 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1335714073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.3497878709
Short name T643
Test name
Test status
Simulation time 83166350 ps
CPU time 0.89 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:16 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497878709 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3497878709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.691479118
Short name T645
Test name
Test status
Simulation time 19110115 ps
CPU time 0.87 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:16 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691479118 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.691479118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.1624582480
Short name T644
Test name
Test status
Simulation time 19087058 ps
CPU time 0.87 seconds
Started Aug 29 07:38:14 AM UTC 24
Finished Aug 29 07:38:16 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624582480 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1624582480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.2558566936
Short name T647
Test name
Test status
Simulation time 13232353 ps
CPU time 0.89 seconds
Started Aug 29 07:38:15 AM UTC 24
Finished Aug 29 07:38:17 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558566936 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2558566936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2210165482
Short name T646
Test name
Test status
Simulation time 11171188 ps
CPU time 0.89 seconds
Started Aug 29 07:38:15 AM UTC 24
Finished Aug 29 07:38:17 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210165482 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2210165482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.2589463879
Short name T648
Test name
Test status
Simulation time 12923166 ps
CPU time 0.91 seconds
Started Aug 29 07:38:15 AM UTC 24
Finished Aug 29 07:38:17 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589463879 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2589463879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1803534267
Short name T546
Test name
Test status
Simulation time 23272314 ps
CPU time 2.06 seconds
Started Aug 29 07:37:41 AM UTC 24
Finished Aug 29 07:37:44 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1803534267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.1803534267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.3616021522
Short name T104
Test name
Test status
Simulation time 37688001 ps
CPU time 1.43 seconds
Started Aug 29 07:37:39 AM UTC 24
Finished Aug 29 07:37:42 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616021522 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3616021522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.1155038570
Short name T542
Test name
Test status
Simulation time 17901797 ps
CPU time 0.9 seconds
Started Aug 29 07:37:39 AM UTC 24
Finished Aug 29 07:37:41 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155038570 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1155038570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1558909572
Short name T547
Test name
Test status
Simulation time 412199593 ps
CPU time 3.55 seconds
Started Aug 29 07:37:40 AM UTC 24
Finished Aug 29 07:37:45 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558909572 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.1558909572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.786123438
Short name T544
Test name
Test status
Simulation time 97895317 ps
CPU time 2.89 seconds
Started Aug 29 07:37:38 AM UTC 24
Finished Aug 29 07:37:42 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786123438 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.786123438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.3298191258
Short name T136
Test name
Test status
Simulation time 3714461394 ps
CPU time 6.09 seconds
Started Aug 29 07:37:39 AM UTC 24
Finished Aug 29 07:37:46 AM UTC 24
Peak memory 207872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298191258 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3298191258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1967168633
Short name T549
Test name
Test status
Simulation time 492573741 ps
CPU time 1.78 seconds
Started Aug 29 07:37:43 AM UTC 24
Finished Aug 29 07:37:45 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1967168633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.1967168633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1994891776
Short name T105
Test name
Test status
Simulation time 145376236 ps
CPU time 1.3 seconds
Started Aug 29 07:37:43 AM UTC 24
Finished Aug 29 07:37:45 AM UTC 24
Peak memory 206660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994891776 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1994891776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.538274934
Short name T545
Test name
Test status
Simulation time 18886577 ps
CPU time 0.99 seconds
Started Aug 29 07:37:41 AM UTC 24
Finished Aug 29 07:37:43 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538274934 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.538274934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3421833833
Short name T550
Test name
Test status
Simulation time 37653409 ps
CPU time 2.35 seconds
Started Aug 29 07:37:43 AM UTC 24
Finished Aug 29 07:37:46 AM UTC 24
Peak memory 207640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421833833 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.3421833833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3212364762
Short name T551
Test name
Test status
Simulation time 70140892 ps
CPU time 4.08 seconds
Started Aug 29 07:37:41 AM UTC 24
Finished Aug 29 07:37:46 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212364762 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3212364762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1000227123
Short name T651
Test name
Test status
Simulation time 95356073211 ps
CPU time 432.57 seconds
Started Aug 29 07:37:46 AM UTC 24
Finished Aug 29 07:45:05 AM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1000227123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.1000227123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3216931212
Short name T107
Test name
Test status
Simulation time 34017707 ps
CPU time 1.37 seconds
Started Aug 29 07:37:46 AM UTC 24
Finished Aug 29 07:37:48 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216931212 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3216931212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.932626251
Short name T552
Test name
Test status
Simulation time 13432639 ps
CPU time 0.84 seconds
Started Aug 29 07:37:45 AM UTC 24
Finished Aug 29 07:37:47 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932626251 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.932626251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.164196056
Short name T555
Test name
Test status
Simulation time 35733801 ps
CPU time 2.37 seconds
Started Aug 29 07:37:46 AM UTC 24
Finished Aug 29 07:37:49 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164196056 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.164196056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2200522543
Short name T554
Test name
Test status
Simulation time 57254081 ps
CPU time 4.52 seconds
Started Aug 29 07:37:43 AM UTC 24
Finished Aug 29 07:37:48 AM UTC 24
Peak memory 207808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200522543 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2200522543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1593636290
Short name T139
Test name
Test status
Simulation time 270000145 ps
CPU time 3.06 seconds
Started Aug 29 07:37:44 AM UTC 24
Finished Aug 29 07:37:48 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593636290 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1593636290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3439633344
Short name T653
Test name
Test status
Simulation time 236702438922 ps
CPU time 1081.29 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:56:03 AM UTC 24
Peak memory 236480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3439633344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.3439633344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.254521293
Short name T108
Test name
Test status
Simulation time 23413766 ps
CPU time 0.8 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:37:50 AM UTC 24
Peak memory 206508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254521293 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.254521293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.4234264667
Short name T556
Test name
Test status
Simulation time 32774317 ps
CPU time 0.82 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:37:50 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234264667 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4234264667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3281547169
Short name T559
Test name
Test status
Simulation time 64980345 ps
CPU time 1.23 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:37:51 AM UTC 24
Peak memory 206848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281547169 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.3281547169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2101598159
Short name T558
Test name
Test status
Simulation time 50731262 ps
CPU time 3 seconds
Started Aug 29 07:37:46 AM UTC 24
Finished Aug 29 07:37:50 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101598159 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2101598159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.568388067
Short name T562
Test name
Test status
Simulation time 51741674 ps
CPU time 2.38 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:37:52 AM UTC 24
Peak memory 207808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568388067 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.568388067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1841988395
Short name T567
Test name
Test status
Simulation time 188933646 ps
CPU time 4.23 seconds
Started Aug 29 07:37:50 AM UTC 24
Finished Aug 29 07:37:55 AM UTC 24
Peak memory 208052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1841988395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.1841988395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.2628459985
Short name T561
Test name
Test status
Simulation time 13013354 ps
CPU time 1.02 seconds
Started Aug 29 07:37:50 AM UTC 24
Finished Aug 29 07:37:52 AM UTC 24
Peak memory 206192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628459985 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2628459985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.2670713454
Short name T560
Test name
Test status
Simulation time 48237537 ps
CPU time 0.97 seconds
Started Aug 29 07:37:50 AM UTC 24
Finished Aug 29 07:37:52 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670713454 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2670713454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.82267577
Short name T564
Test name
Test status
Simulation time 74404748 ps
CPU time 2.4 seconds
Started Aug 29 07:37:50 AM UTC 24
Finished Aug 29 07:37:53 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82267577 -assert nopostproc +UVM_
TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.82267577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.394819977
Short name T569
Test name
Test status
Simulation time 224481311 ps
CPU time 5.68 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:37:55 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394819977 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.394819977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.3329040777
Short name T137
Test name
Test status
Simulation time 194574607 ps
CPU time 4.86 seconds
Started Aug 29 07:37:48 AM UTC 24
Finished Aug 29 07:37:54 AM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329040777 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3329040777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_alert_test.868054344
Short name T1
Test name
Test status
Simulation time 26223572 ps
CPU time 0.64 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:32:37 PM UTC 24
Peak memory 204532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868054344 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.868054344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.3677686540
Short name T13
Test name
Test status
Simulation time 8488195887 ps
CPU time 46.27 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:33:20 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677686540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3677686540
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_error.3652406380
Short name T47
Test name
Test status
Simulation time 2329932300 ps
CPU time 52.65 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:33:26 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652406380 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3652406380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_long_msg.851551375
Short name T5
Test name
Test status
Simulation time 285764496 ps
CPU time 7.75 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:32:40 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851551375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.851551375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1139001565
Short name T2
Test name
Test status
Simulation time 143446421 ps
CPU time 1.39 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:32:37 PM UTC 24
Peak memory 235560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139001565 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1139001565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_stress_all.495647892
Short name T24
Test name
Test status
Simulation time 21380982773 ps
CPU time 893.63 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:47:39 PM UTC 24
Peak memory 716972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495647892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.495647892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.4016750142
Short name T17
Test name
Test status
Simulation time 2743500470 ps
CPU time 38.74 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:33:15 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016750142 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.4016750142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.4263685238
Short name T172
Test name
Test status
Simulation time 13642112141 ps
CPU time 137.66 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:34:55 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263685238 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4263685238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.3465115928
Short name T61
Test name
Test status
Simulation time 2931943274 ps
CPU time 119.18 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:34:36 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465115928 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3465115928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.1626593264
Short name T499
Test name
Test status
Simulation time 210354074659 ps
CPU time 2367.26 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 10:12:30 PM UTC 24
Peak memory 221252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626593264 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1626593264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.1381248802
Short name T512
Test name
Test status
Simulation time 686601889811 ps
CPU time 2649.77 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 10:17:18 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381248802 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1381248802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3946670786
Short name T7
Test name
Test status
Simulation time 8380104182 ps
CPU time 11.96 seconds
Started Aug 28 09:32:32 PM UTC 24
Finished Aug 28 09:32:45 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946670786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3946670786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.3028804134
Short name T8
Test name
Test status
Simulation time 685167254 ps
CPU time 6.9 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:32:43 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028804134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3028804134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.3152838777
Short name T260
Test name
Test status
Simulation time 7544894404 ps
CPU time 592.4 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:42:34 PM UTC 24
Peak memory 702820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152838777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3152838777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_error.1206266711
Short name T171
Test name
Test status
Simulation time 4706793846 ps
CPU time 108.66 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:34:26 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206266711 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1206266711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2311049897
Short name T15
Test name
Test status
Simulation time 2208549982 ps
CPU time 47.61 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:33:24 PM UTC 24
Peak memory 206856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311049897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2311049897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_smoke.163705383
Short name T4
Test name
Test status
Simulation time 221890893 ps
CPU time 4.05 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:32:40 PM UTC 24
Peak memory 206668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163705383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.163705383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_stress_all.2125248491
Short name T48
Test name
Test status
Simulation time 80649961438 ps
CPU time 124.89 seconds
Started Aug 28 09:32:41 PM UTC 24
Finished Aug 28 09:34:49 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125248491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2125248491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.1538090276
Short name T119
Test name
Test status
Simulation time 3751978633 ps
CPU time 73.09 seconds
Started Aug 28 09:32:39 PM UTC 24
Finished Aug 28 09:33:54 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538090276 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1538090276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.3209534685
Short name T120
Test name
Test status
Simulation time 4482184585 ps
CPU time 74.49 seconds
Started Aug 28 09:32:39 PM UTC 24
Finished Aug 28 09:33:55 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209534685 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3209534685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.1564414954
Short name T175
Test name
Test status
Simulation time 12766233437 ps
CPU time 144.59 seconds
Started Aug 28 09:32:41 PM UTC 24
Finished Aug 28 09:35:09 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564414954 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1564414954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.4038343771
Short name T312
Test name
Test status
Simulation time 54498075040 ps
CPU time 826.93 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:46:33 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038343771 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.4038343771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.1722592411
Short name T507
Test name
Test status
Simulation time 156199574807 ps
CPU time 2537.5 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 10:15:23 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722592411 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1722592411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.1676860564
Short name T521
Test name
Test status
Simulation time 428155028044 ps
CPU time 3023.73 seconds
Started Aug 28 09:32:38 PM UTC 24
Finished Aug 28 10:23:36 PM UTC 24
Peak memory 227388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676860564 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1676860564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.3812211008
Short name T6
Test name
Test status
Simulation time 699143956 ps
CPU time 6.65 seconds
Started Aug 28 09:32:35 PM UTC 24
Finished Aug 28 09:32:43 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812211008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3812211008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_alert_test.2090235865
Short name T193
Test name
Test status
Simulation time 148944474 ps
CPU time 0.88 seconds
Started Aug 28 09:36:45 PM UTC 24
Finished Aug 28 09:36:47 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090235865 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2090235865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.4015508536
Short name T23
Test name
Test status
Simulation time 5190825951 ps
CPU time 81.55 seconds
Started Aug 28 09:36:34 PM UTC 24
Finished Aug 28 09:37:58 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015508536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4015508536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.1914885452
Short name T29
Test name
Test status
Simulation time 1246316783 ps
CPU time 18.8 seconds
Started Aug 28 09:36:39 PM UTC 24
Finished Aug 28 09:36:59 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914885452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1914885452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.1336216361
Short name T487
Test name
Test status
Simulation time 15175600702 ps
CPU time 1584.15 seconds
Started Aug 28 09:36:38 PM UTC 24
Finished Aug 28 10:03:19 PM UTC 24
Peak memory 719144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336216361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1336216361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_error.2053761270
Short name T38
Test name
Test status
Simulation time 8452281986 ps
CPU time 95.31 seconds
Started Aug 28 09:36:39 PM UTC 24
Finished Aug 28 09:38:17 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053761270 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2053761270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_long_msg.1512539337
Short name T39
Test name
Test status
Simulation time 6559244545 ps
CPU time 102.65 seconds
Started Aug 28 09:36:32 PM UTC 24
Finished Aug 28 09:38:17 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512539337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1512539337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_smoke.3111907045
Short name T192
Test name
Test status
Simulation time 360606484 ps
CPU time 10.01 seconds
Started Aug 28 09:36:32 PM UTC 24
Finished Aug 28 09:36:44 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111907045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3111907045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_stress_all.3941389627
Short name T73
Test name
Test status
Simulation time 1315187528017 ps
CPU time 3444.23 seconds
Started Aug 28 09:36:45 PM UTC 24
Finished Aug 28 10:34:47 PM UTC 24
Peak memory 798840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941389627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3941389627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.4098312140
Short name T197
Test name
Test status
Simulation time 13950345168 ps
CPU time 17.74 seconds
Started Aug 28 09:36:41 PM UTC 24
Finished Aug 28 09:37:01 PM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098312140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4098312140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_alert_test.2581666858
Short name T199
Test name
Test status
Simulation time 51132224 ps
CPU time 0.84 seconds
Started Aug 28 09:37:08 PM UTC 24
Finished Aug 28 09:37:10 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581666858 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2581666858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.3565645318
Short name T209
Test name
Test status
Simulation time 4067093208 ps
CPU time 60.84 seconds
Started Aug 28 09:36:51 PM UTC 24
Finished Aug 28 09:37:53 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565645318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3565645318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.362825487
Short name T206
Test name
Test status
Simulation time 13499576930 ps
CPU time 40.3 seconds
Started Aug 28 09:36:56 PM UTC 24
Finished Aug 28 09:37:38 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362825487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.362825487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.2695691473
Short name T195
Test name
Test status
Simulation time 14941873 ps
CPU time 1.22 seconds
Started Aug 28 09:36:53 PM UTC 24
Finished Aug 28 09:36:55 PM UTC 24
Peak memory 206868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695691473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2695691473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_error.3141380152
Short name T230
Test name
Test status
Simulation time 9384944361 ps
CPU time 173.41 seconds
Started Aug 28 09:37:01 PM UTC 24
Finished Aug 28 09:39:58 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141380152 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3141380152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_long_msg.949895204
Short name T205
Test name
Test status
Simulation time 23713127339 ps
CPU time 46.83 seconds
Started Aug 28 09:36:49 PM UTC 24
Finished Aug 28 09:37:37 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949895204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.949895204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_smoke.3716552786
Short name T200
Test name
Test status
Simulation time 4323499868 ps
CPU time 19.81 seconds
Started Aug 28 09:36:49 PM UTC 24
Finished Aug 28 09:37:10 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716552786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3716552786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.3371725950
Short name T220
Test name
Test status
Simulation time 2641105975 ps
CPU time 145.84 seconds
Started Aug 28 09:37:01 PM UTC 24
Finished Aug 28 09:39:30 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371725950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3371725950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_alert_test.2549816731
Short name T202
Test name
Test status
Simulation time 22788780 ps
CPU time 0.69 seconds
Started Aug 28 09:37:30 PM UTC 24
Finished Aug 28 09:37:31 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549816731 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2549816731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.1183242201
Short name T215
Test name
Test status
Simulation time 5468581081 ps
CPU time 99.7 seconds
Started Aug 28 09:37:11 PM UTC 24
Finished Aug 28 09:38:53 PM UTC 24
Peak memory 223816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183242201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1183242201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.377958602
Short name T162
Test name
Test status
Simulation time 1666187534 ps
CPU time 19.15 seconds
Started Aug 28 09:37:11 PM UTC 24
Finished Aug 28 09:37:32 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377958602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.377958602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.4216260423
Short name T442
Test name
Test status
Simulation time 10924566404 ps
CPU time 1163.99 seconds
Started Aug 28 09:37:11 PM UTC 24
Finished Aug 28 09:56:48 PM UTC 24
Peak memory 750060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216260423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4216260423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_error.4009982238
Short name T33
Test name
Test status
Simulation time 697366708 ps
CPU time 42.39 seconds
Started Aug 28 09:37:19 PM UTC 24
Finished Aug 28 09:38:03 PM UTC 24
Peak memory 207052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009982238 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.4009982238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2677737349
Short name T207
Test name
Test status
Simulation time 527603717 ps
CPU time 37.66 seconds
Started Aug 28 09:37:08 PM UTC 24
Finished Aug 28 09:37:47 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677737349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2677737349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_smoke.94190344
Short name T201
Test name
Test status
Simulation time 8372812348 ps
CPU time 19.9 seconds
Started Aug 28 09:37:08 PM UTC 24
Finished Aug 28 09:37:29 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94190344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 12.hmac_smoke.94190344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.2339246321
Short name T37
Test name
Test status
Simulation time 2683094558 ps
CPU time 48.54 seconds
Started Aug 28 09:37:26 PM UTC 24
Finished Aug 28 09:38:16 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339246321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2339246321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_alert_test.1156376499
Short name T208
Test name
Test status
Simulation time 15828637 ps
CPU time 0.94 seconds
Started Aug 28 09:37:48 PM UTC 24
Finished Aug 28 09:37:50 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156376499 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1156376499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.2923340136
Short name T43
Test name
Test status
Simulation time 1738342309 ps
CPU time 111.48 seconds
Started Aug 28 09:37:39 PM UTC 24
Finished Aug 28 09:39:33 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923340136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2923340136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.2868033151
Short name T246
Test name
Test status
Simulation time 1153694270 ps
CPU time 222.76 seconds
Started Aug 28 09:37:39 PM UTC 24
Finished Aug 28 09:41:25 PM UTC 24
Peak memory 475504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868033151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2868033151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_error.3945923054
Short name T82
Test name
Test status
Simulation time 11394593872 ps
CPU time 179.1 seconds
Started Aug 28 09:37:39 PM UTC 24
Finished Aug 28 09:40:41 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945923054 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3945923054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_long_msg.3400543047
Short name T225
Test name
Test status
Simulation time 8867541022 ps
CPU time 124.35 seconds
Started Aug 28 09:37:33 PM UTC 24
Finished Aug 28 09:39:39 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400543047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3400543047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_smoke.1849037988
Short name T204
Test name
Test status
Simulation time 223635233 ps
CPU time 4.3 seconds
Started Aug 28 09:37:32 PM UTC 24
Finished Aug 28 09:37:37 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849037988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1849037988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_stress_all.1431861021
Short name T127
Test name
Test status
Simulation time 1426879027 ps
CPU time 80.2 seconds
Started Aug 28 09:37:47 PM UTC 24
Finished Aug 28 09:39:09 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431861021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1431861021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.3334269068
Short name T35
Test name
Test status
Simulation time 1022744904 ps
CPU time 29.38 seconds
Started Aug 28 09:37:41 PM UTC 24
Finished Aug 28 09:38:11 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334269068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3334269068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_alert_test.2010606398
Short name T40
Test name
Test status
Simulation time 11855234 ps
CPU time 0.81 seconds
Started Aug 28 09:38:18 PM UTC 24
Finished Aug 28 09:38:20 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010606398 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2010606398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.2256076455
Short name T34
Test name
Test status
Simulation time 201038975 ps
CPU time 11.25 seconds
Started Aug 28 09:37:57 PM UTC 24
Finished Aug 28 09:38:09 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256076455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2256076455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.890219406
Short name T214
Test name
Test status
Simulation time 2437413141 ps
CPU time 46.42 seconds
Started Aug 28 09:38:04 PM UTC 24
Finished Aug 28 09:38:52 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890219406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.890219406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.613718296
Short name T477
Test name
Test status
Simulation time 82394488578 ps
CPU time 1310.44 seconds
Started Aug 28 09:37:59 PM UTC 24
Finished Aug 28 10:00:03 PM UTC 24
Peak memory 794908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613718296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.613718296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_error.1847753912
Short name T241
Test name
Test status
Simulation time 12489588059 ps
CPU time 167.18 seconds
Started Aug 28 09:38:09 PM UTC 24
Finished Aug 28 09:40:59 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847753912 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1847753912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_long_msg.4085323757
Short name T219
Test name
Test status
Simulation time 1112884644 ps
CPU time 81.41 seconds
Started Aug 28 09:37:55 PM UTC 24
Finished Aug 28 09:39:18 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085323757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4085323757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_smoke.4141638813
Short name T210
Test name
Test status
Simulation time 279992961 ps
CPU time 3.79 seconds
Started Aug 28 09:37:51 PM UTC 24
Finished Aug 28 09:37:56 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141638813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4141638813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_stress_all.3992596183
Short name T166
Test name
Test status
Simulation time 51990992408 ps
CPU time 805.71 seconds
Started Aug 28 09:38:12 PM UTC 24
Finished Aug 28 09:51:48 PM UTC 24
Peak memory 366820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992596183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3992596183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.2904795648
Short name T229
Test name
Test status
Simulation time 30844410381 ps
CPU time 103.25 seconds
Started Aug 28 09:38:10 PM UTC 24
Finished Aug 28 09:39:55 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904795648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2904795648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_alert_test.937095534
Short name T216
Test name
Test status
Simulation time 39394262 ps
CPU time 0.83 seconds
Started Aug 28 09:38:53 PM UTC 24
Finished Aug 28 09:38:55 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937095534 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.937095534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.3897406038
Short name T217
Test name
Test status
Simulation time 1810932693 ps
CPU time 34.16 seconds
Started Aug 28 09:38:20 PM UTC 24
Finished Aug 28 09:38:55 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897406038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3897406038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.2573226986
Short name T157
Test name
Test status
Simulation time 1639265048 ps
CPU time 56.95 seconds
Started Aug 28 09:38:31 PM UTC 24
Finished Aug 28 09:39:30 PM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573226986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2573226986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.73799893
Short name T367
Test name
Test status
Simulation time 11025435799 ps
CPU time 730.4 seconds
Started Aug 28 09:38:21 PM UTC 24
Finished Aug 28 09:50:40 PM UTC 24
Peak memory 764164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73799893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.73799893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_error.1797849425
Short name T224
Test name
Test status
Simulation time 11837883030 ps
CPU time 62.63 seconds
Started Aug 28 09:38:32 PM UTC 24
Finished Aug 28 09:39:37 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797849425 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1797849425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_long_msg.683358435
Short name T233
Test name
Test status
Simulation time 1310550586 ps
CPU time 102.43 seconds
Started Aug 28 09:38:18 PM UTC 24
Finished Aug 28 09:40:03 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683358435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.683358435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_smoke.1269494356
Short name T211
Test name
Test status
Simulation time 423759082 ps
CPU time 10.56 seconds
Started Aug 28 09:38:18 PM UTC 24
Finished Aug 28 09:38:30 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269494356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1269494356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_stress_all.2682560958
Short name T132
Test name
Test status
Simulation time 7887797372 ps
CPU time 515.82 seconds
Started Aug 28 09:38:37 PM UTC 24
Finished Aug 28 09:47:20 PM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682560958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2682560958
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.1126463192
Short name T221
Test name
Test status
Simulation time 12754805563 ps
CPU time 55.99 seconds
Started Aug 28 09:38:35 PM UTC 24
Finished Aug 28 09:39:32 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126463192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1126463192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_alert_test.3159642879
Short name T222
Test name
Test status
Simulation time 25880684 ps
CPU time 0.91 seconds
Started Aug 28 09:39:32 PM UTC 24
Finished Aug 28 09:39:34 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159642879 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3159642879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1295891888
Short name T223
Test name
Test status
Simulation time 5644510990 ps
CPU time 38.14 seconds
Started Aug 28 09:38:56 PM UTC 24
Finished Aug 28 09:39:36 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295891888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1295891888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.95002539
Short name T80
Test name
Test status
Simulation time 16651066420 ps
CPU time 77.53 seconds
Started Aug 28 09:39:05 PM UTC 24
Finished Aug 28 09:40:24 PM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95002539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.95002539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.1212512816
Short name T337
Test name
Test status
Simulation time 9872009249 ps
CPU time 567.07 seconds
Started Aug 28 09:38:57 PM UTC 24
Finished Aug 28 09:48:31 PM UTC 24
Peak memory 715020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212512816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1212512816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_error.4041047808
Short name T250
Test name
Test status
Simulation time 2470188207 ps
CPU time 159.07 seconds
Started Aug 28 09:39:10 PM UTC 24
Finished Aug 28 09:41:52 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041047808 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4041047808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_long_msg.2209736984
Short name T253
Test name
Test status
Simulation time 9010901797 ps
CPU time 196.69 seconds
Started Aug 28 09:38:55 PM UTC 24
Finished Aug 28 09:42:15 PM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209736984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2209736984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_smoke.2711913438
Short name T218
Test name
Test status
Simulation time 1631214525 ps
CPU time 10.04 seconds
Started Aug 28 09:38:53 PM UTC 24
Finished Aug 28 09:39:04 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711913438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2711913438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2774471435
Short name T486
Test name
Test status
Simulation time 9018467564 ps
CPU time 1399.04 seconds
Started Aug 28 09:39:32 PM UTC 24
Finished Aug 28 10:03:07 PM UTC 24
Peak memory 717028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774471435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2774471435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2285827646
Short name T249
Test name
Test status
Simulation time 36859504818 ps
CPU time 147.94 seconds
Started Aug 28 09:39:20 PM UTC 24
Finished Aug 28 09:41:50 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285827646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2285827646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_alert_test.4123983214
Short name T227
Test name
Test status
Simulation time 39389374 ps
CPU time 0.87 seconds
Started Aug 28 09:39:46 PM UTC 24
Finished Aug 28 09:39:48 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123983214 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4123983214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.1277769766
Short name T231
Test name
Test status
Simulation time 1204817257 ps
CPU time 24.21 seconds
Started Aug 28 09:39:35 PM UTC 24
Finished Aug 28 09:40:01 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277769766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1277769766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.2784666737
Short name T78
Test name
Test status
Simulation time 5011584243 ps
CPU time 37.1 seconds
Started Aug 28 09:39:39 PM UTC 24
Finished Aug 28 09:40:18 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784666737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2784666737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.276148732
Short name T386
Test name
Test status
Simulation time 3562831999 ps
CPU time 759.47 seconds
Started Aug 28 09:39:37 PM UTC 24
Finished Aug 28 09:52:26 PM UTC 24
Peak memory 663776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276148732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.276148732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_error.3292615534
Short name T279
Test name
Test status
Simulation time 38074748375 ps
CPU time 248.98 seconds
Started Aug 28 09:39:42 PM UTC 24
Finished Aug 28 09:43:54 PM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292615534 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3292615534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_long_msg.144574698
Short name T228
Test name
Test status
Simulation time 3185569165 ps
CPU time 15.48 seconds
Started Aug 28 09:39:35 PM UTC 24
Finished Aug 28 09:39:52 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144574698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.144574698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_smoke.2427290547
Short name T226
Test name
Test status
Simulation time 1060092816 ps
CPU time 10.89 seconds
Started Aug 28 09:39:33 PM UTC 24
Finished Aug 28 09:39:45 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427290547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2427290547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_stress_all.3218926093
Short name T514
Test name
Test status
Simulation time 59835652399 ps
CPU time 2349.07 seconds
Started Aug 28 09:39:45 PM UTC 24
Finished Aug 28 10:19:20 PM UTC 24
Peak memory 768428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218926093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3218926093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.2454697382
Short name T234
Test name
Test status
Simulation time 523794075 ps
CPU time 20.83 seconds
Started Aug 28 09:39:42 PM UTC 24
Finished Aug 28 09:40:04 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454697382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2454697382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_alert_test.4071763673
Short name T236
Test name
Test status
Simulation time 29189368 ps
CPU time 0.81 seconds
Started Aug 28 09:40:05 PM UTC 24
Finished Aug 28 09:40:07 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071763673 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.4071763673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.2587536775
Short name T76
Test name
Test status
Simulation time 767844387 ps
CPU time 16.84 seconds
Started Aug 28 09:39:57 PM UTC 24
Finished Aug 28 09:40:15 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587536775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2587536775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.2202698493
Short name T84
Test name
Test status
Simulation time 3268280852 ps
CPU time 42.68 seconds
Started Aug 28 09:40:00 PM UTC 24
Finished Aug 28 09:40:45 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202698493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2202698493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.4155160300
Short name T382
Test name
Test status
Simulation time 7708947267 ps
CPU time 718.56 seconds
Started Aug 28 09:39:59 PM UTC 24
Finished Aug 28 09:52:06 PM UTC 24
Peak memory 710888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155160300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.4155160300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_error.3205300856
Short name T79
Test name
Test status
Simulation time 4796185926 ps
CPU time 19.29 seconds
Started Aug 28 09:40:03 PM UTC 24
Finished Aug 28 09:40:24 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205300856 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3205300856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_long_msg.3340020063
Short name T238
Test name
Test status
Simulation time 772725996 ps
CPU time 53.27 seconds
Started Aug 28 09:39:53 PM UTC 24
Finished Aug 28 09:40:48 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340020063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3340020063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_smoke.904377326
Short name T235
Test name
Test status
Simulation time 699360714 ps
CPU time 16.37 seconds
Started Aug 28 09:39:49 PM UTC 24
Finished Aug 28 09:40:07 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904377326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.904377326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2888271896
Short name T511
Test name
Test status
Simulation time 20619190000 ps
CPU time 2173.93 seconds
Started Aug 28 09:40:05 PM UTC 24
Finished Aug 28 10:16:43 PM UTC 24
Peak memory 741664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888271896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2888271896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.1741202542
Short name T87
Test name
Test status
Simulation time 18217998023 ps
CPU time 150.94 seconds
Started Aug 28 09:40:03 PM UTC 24
Finished Aug 28 09:42:37 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741202542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1741202542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_alert_test.316808448
Short name T83
Test name
Test status
Simulation time 33116199 ps
CPU time 0.81 seconds
Started Aug 28 09:40:43 PM UTC 24
Finished Aug 28 09:40:45 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316808448 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.316808448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.4047496608
Short name T81
Test name
Test status
Simulation time 425402915 ps
CPU time 25.3 seconds
Started Aug 28 09:40:14 PM UTC 24
Finished Aug 28 09:40:41 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047496608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4047496608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.2349244083
Short name T44
Test name
Test status
Simulation time 507809042 ps
CPU time 31.88 seconds
Started Aug 28 09:40:17 PM UTC 24
Finished Aug 28 09:40:51 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349244083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2349244083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.416688593
Short name T494
Test name
Test status
Simulation time 97125448621 ps
CPU time 1592.89 seconds
Started Aug 28 09:40:15 PM UTC 24
Finished Aug 28 10:07:06 PM UTC 24
Peak memory 778536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416688593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.416688593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_error.2111728365
Short name T261
Test name
Test status
Simulation time 7352941561 ps
CPU time 134.26 seconds
Started Aug 28 09:40:19 PM UTC 24
Finished Aug 28 09:42:35 PM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111728365 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2111728365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3493985815
Short name T276
Test name
Test status
Simulation time 160699047535 ps
CPU time 213.47 seconds
Started Aug 28 09:40:07 PM UTC 24
Finished Aug 28 09:43:44 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493985815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3493985815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_smoke.806731483
Short name T77
Test name
Test status
Simulation time 402105666 ps
CPU time 8.39 seconds
Started Aug 28 09:40:07 PM UTC 24
Finished Aug 28 09:40:17 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806731483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.806731483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_stress_all.3723708300
Short name T523
Test name
Test status
Simulation time 238952922612 ps
CPU time 2795.43 seconds
Started Aug 28 09:40:25 PM UTC 24
Finished Aug 28 10:27:31 PM UTC 24
Peak memory 800928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723708300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3723708300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.2230794143
Short name T263
Test name
Test status
Simulation time 13448716999 ps
CPU time 130.73 seconds
Started Aug 28 09:40:25 PM UTC 24
Finished Aug 28 09:42:38 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230794143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2230794143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_alert_test.4181604703
Short name T49
Test name
Test status
Simulation time 23904983 ps
CPU time 0.88 seconds
Started Aug 28 09:33:22 PM UTC 24
Finished Aug 28 09:33:23 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181604703 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4181604703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.312252816
Short name T10
Test name
Test status
Simulation time 456067491 ps
CPU time 16.58 seconds
Started Aug 28 09:32:50 PM UTC 24
Finished Aug 28 09:33:07 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312252816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.312252816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.238911918
Short name T42
Test name
Test status
Simulation time 28443271216 ps
CPU time 40.14 seconds
Started Aug 28 09:32:54 PM UTC 24
Finished Aug 28 09:33:35 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238911918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.238911918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.613419797
Short name T309
Test name
Test status
Simulation time 4458340451 ps
CPU time 804.31 seconds
Started Aug 28 09:32:50 PM UTC 24
Finished Aug 28 09:46:23 PM UTC 24
Peak memory 706784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613419797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.613419797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_error.3750712587
Short name T46
Test name
Test status
Simulation time 6671901449 ps
CPU time 28.13 seconds
Started Aug 28 09:32:56 PM UTC 24
Finished Aug 28 09:33:25 PM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750712587 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3750712587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_long_msg.2046056159
Short name T118
Test name
Test status
Simulation time 3733231281 ps
CPU time 60.01 seconds
Started Aug 28 09:32:49 PM UTC 24
Finished Aug 28 09:33:51 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046056159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2046056159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.2531302943
Short name T51
Test name
Test status
Simulation time 108979010 ps
CPU time 1.43 seconds
Started Aug 28 09:33:17 PM UTC 24
Finished Aug 28 09:33:20 PM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531302943 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2531302943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_smoke.2408465136
Short name T9
Test name
Test status
Simulation time 942101242 ps
CPU time 5.88 seconds
Started Aug 28 09:32:47 PM UTC 24
Finished Aug 28 09:32:55 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408465136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2408465136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_stress_all.2519011396
Short name T148
Test name
Test status
Simulation time 9065273091 ps
CPU time 174.42 seconds
Started Aug 28 09:33:13 PM UTC 24
Finished Aug 28 09:36:10 PM UTC 24
Peak memory 284964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519011396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2519011396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.274510622
Short name T117
Test name
Test status
Simulation time 3359722975 ps
CPU time 39.75 seconds
Started Aug 28 09:33:02 PM UTC 24
Finished Aug 28 09:33:44 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274510622 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.274510622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.1447400751
Short name T67
Test name
Test status
Simulation time 2237364877 ps
CPU time 102.57 seconds
Started Aug 28 09:33:02 PM UTC 24
Finished Aug 28 09:34:47 PM UTC 24
Peak memory 206928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447400751 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1447400751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.1673292243
Short name T182
Test name
Test status
Simulation time 25186024198 ps
CPU time 174.78 seconds
Started Aug 28 09:33:08 PM UTC 24
Finished Aug 28 09:36:06 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673292243 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1673292243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.2697388013
Short name T152
Test name
Test status
Simulation time 149396340318 ps
CPU time 674.89 seconds
Started Aug 28 09:32:58 PM UTC 24
Finished Aug 28 09:44:21 PM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697388013 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2697388013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.3383865049
Short name T515
Test name
Test status
Simulation time 1898751751502 ps
CPU time 2784.07 seconds
Started Aug 28 09:32:58 PM UTC 24
Finished Aug 28 10:19:54 PM UTC 24
Peak memory 225348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383865049 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3383865049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1774514618
Short name T513
Test name
Test status
Simulation time 212371065091 ps
CPU time 2630.8 seconds
Started Aug 28 09:33:00 PM UTC 24
Finished Aug 28 10:17:21 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774514618 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1774514618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_alert_test.223878851
Short name T242
Test name
Test status
Simulation time 169189489 ps
CPU time 0.85 seconds
Started Aug 28 09:41:01 PM UTC 24
Finished Aug 28 09:41:03 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223878851 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.223878851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.1504775649
Short name T239
Test name
Test status
Simulation time 148034244 ps
CPU time 5.49 seconds
Started Aug 28 09:40:45 PM UTC 24
Finished Aug 28 09:40:52 PM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504775649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1504775649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.2852047115
Short name T247
Test name
Test status
Simulation time 2934546141 ps
CPU time 56.46 seconds
Started Aug 28 09:40:49 PM UTC 24
Finished Aug 28 09:41:47 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852047115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2852047115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.916927628
Short name T438
Test name
Test status
Simulation time 16973073773 ps
CPU time 921.99 seconds
Started Aug 28 09:40:49 PM UTC 24
Finished Aug 28 09:56:21 PM UTC 24
Peak memory 729576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916927628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.916927628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_error.1590686632
Short name T285
Test name
Test status
Simulation time 51044198398 ps
CPU time 193.02 seconds
Started Aug 28 09:40:52 PM UTC 24
Finished Aug 28 09:44:08 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590686632 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1590686632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_long_msg.2013022380
Short name T240
Test name
Test status
Simulation time 1044424117 ps
CPU time 5.68 seconds
Started Aug 28 09:40:45 PM UTC 24
Finished Aug 28 09:40:52 PM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013022380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2013022380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_smoke.2807239535
Short name T237
Test name
Test status
Simulation time 281541196 ps
CPU time 3.71 seconds
Started Aug 28 09:40:43 PM UTC 24
Finished Aug 28 09:40:48 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807239535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2807239535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_stress_all.2917413484
Short name T517
Test name
Test status
Simulation time 19589664404 ps
CPU time 2346.11 seconds
Started Aug 28 09:40:53 PM UTC 24
Finished Aug 28 10:20:23 PM UTC 24
Peak memory 784884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917413484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2917413484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.2553309372
Short name T270
Test name
Test status
Simulation time 22838746250 ps
CPU time 141.26 seconds
Started Aug 28 09:40:53 PM UTC 24
Finished Aug 28 09:43:17 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553309372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2553309372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_alert_test.3041312943
Short name T248
Test name
Test status
Simulation time 34732454 ps
CPU time 0.78 seconds
Started Aug 28 09:41:48 PM UTC 24
Finished Aug 28 09:41:50 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041312943 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3041312943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.4023558299
Short name T259
Test name
Test status
Simulation time 2732446776 ps
CPU time 74.93 seconds
Started Aug 28 09:41:15 PM UTC 24
Finished Aug 28 09:42:31 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023558299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4023558299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.3673893592
Short name T163
Test name
Test status
Simulation time 1476188797 ps
CPU time 14.36 seconds
Started Aug 28 09:41:26 PM UTC 24
Finished Aug 28 09:41:42 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673893592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3673893592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.1869861413
Short name T317
Test name
Test status
Simulation time 3954045404 ps
CPU time 334.7 seconds
Started Aug 28 09:41:17 PM UTC 24
Finished Aug 28 09:46:56 PM UTC 24
Peak memory 682212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869861413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1869861413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_error.287772877
Short name T266
Test name
Test status
Simulation time 1174270044 ps
CPU time 85.14 seconds
Started Aug 28 09:41:27 PM UTC 24
Finished Aug 28 09:42:54 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287772877 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.287772877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_long_msg.4268146019
Short name T251
Test name
Test status
Simulation time 731677887 ps
CPU time 46.36 seconds
Started Aug 28 09:41:12 PM UTC 24
Finished Aug 28 09:42:01 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268146019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4268146019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_smoke.2802266162
Short name T243
Test name
Test status
Simulation time 1468087884 ps
CPU time 8.72 seconds
Started Aug 28 09:41:04 PM UTC 24
Finished Aug 28 09:41:14 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802266162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2802266162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_stress_all.2787681541
Short name T311
Test name
Test status
Simulation time 7485397429 ps
CPU time 283.79 seconds
Started Aug 28 09:41:43 PM UTC 24
Finished Aug 28 09:46:31 PM UTC 24
Peak memory 454964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787681541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2787681541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.3309136349
Short name T256
Test name
Test status
Simulation time 1389767962 ps
CPU time 46.19 seconds
Started Aug 28 09:41:39 PM UTC 24
Finished Aug 28 09:42:26 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309136349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3309136349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_alert_test.383203157
Short name T257
Test name
Test status
Simulation time 22319645 ps
CPU time 0.83 seconds
Started Aug 28 09:42:28 PM UTC 24
Finished Aug 28 09:42:30 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383203157 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.383203157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.466253520
Short name T269
Test name
Test status
Simulation time 2178957709 ps
CPU time 69.29 seconds
Started Aug 28 09:41:53 PM UTC 24
Finished Aug 28 09:43:04 PM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466253520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.466253520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.1286052303
Short name T272
Test name
Test status
Simulation time 6362689833 ps
CPU time 68.04 seconds
Started Aug 28 09:42:08 PM UTC 24
Finished Aug 28 09:43:18 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286052303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1286052303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.1650382115
Short name T323
Test name
Test status
Simulation time 1565134056 ps
CPU time 319.7 seconds
Started Aug 28 09:42:02 PM UTC 24
Finished Aug 28 09:47:26 PM UTC 24
Peak memory 637084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650382115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1650382115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_error.3700884329
Short name T258
Test name
Test status
Simulation time 352087838 ps
CPU time 12.33 seconds
Started Aug 28 09:42:17 PM UTC 24
Finished Aug 28 09:42:31 PM UTC 24
Peak memory 207052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700884329 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3700884329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_long_msg.2898488189
Short name T287
Test name
Test status
Simulation time 8994842980 ps
CPU time 139.99 seconds
Started Aug 28 09:41:52 PM UTC 24
Finished Aug 28 09:44:14 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898488189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2898488189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_smoke.1160149988
Short name T252
Test name
Test status
Simulation time 241703391 ps
CPU time 14.43 seconds
Started Aug 28 09:41:52 PM UTC 24
Finished Aug 28 09:42:07 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160149988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1160149988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_stress_all.983157709
Short name T527
Test name
Test status
Simulation time 245464467825 ps
CPU time 3291.52 seconds
Started Aug 28 09:42:24 PM UTC 24
Finished Aug 28 10:37:50 PM UTC 24
Peak memory 798964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983157709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.983157709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.1399639304
Short name T255
Test name
Test status
Simulation time 19273060 ps
CPU time 0.97 seconds
Started Aug 28 09:42:21 PM UTC 24
Finished Aug 28 09:42:23 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399639304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1399639304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_alert_test.1668627430
Short name T265
Test name
Test status
Simulation time 25206131 ps
CPU time 0.87 seconds
Started Aug 28 09:42:47 PM UTC 24
Finished Aug 28 09:42:49 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668627430 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1668627430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.3416177045
Short name T264
Test name
Test status
Simulation time 1665929153 ps
CPU time 11.49 seconds
Started Aug 28 09:42:33 PM UTC 24
Finished Aug 28 09:42:46 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416177045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3416177045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.273463124
Short name T273
Test name
Test status
Simulation time 2936937215 ps
CPU time 48.07 seconds
Started Aug 28 09:42:38 PM UTC 24
Finished Aug 28 09:43:28 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273463124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.273463124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.3225597712
Short name T275
Test name
Test status
Simulation time 929198303 ps
CPU time 56.46 seconds
Started Aug 28 09:42:37 PM UTC 24
Finished Aug 28 09:43:36 PM UTC 24
Peak memory 348260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225597712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3225597712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_error.1458421203
Short name T295
Test name
Test status
Simulation time 21003717141 ps
CPU time 135.66 seconds
Started Aug 28 09:42:40 PM UTC 24
Finished Aug 28 09:44:59 PM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458421203 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1458421203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_long_msg.2322288139
Short name T307
Test name
Test status
Simulation time 47923428543 ps
CPU time 218.99 seconds
Started Aug 28 09:42:33 PM UTC 24
Finished Aug 28 09:46:15 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322288139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2322288139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_smoke.3669756180
Short name T262
Test name
Test status
Simulation time 178828244 ps
CPU time 5.71 seconds
Started Aug 28 09:42:31 PM UTC 24
Finished Aug 28 09:42:38 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669756180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3669756180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_stress_all.1537468856
Short name T268
Test name
Test status
Simulation time 5078724974 ps
CPU time 21.06 seconds
Started Aug 28 09:42:40 PM UTC 24
Finished Aug 28 09:43:03 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537468856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1537468856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.4044193139
Short name T284
Test name
Test status
Simulation time 4125026671 ps
CPU time 85.12 seconds
Started Aug 28 09:42:40 PM UTC 24
Finished Aug 28 09:44:08 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044193139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4044193139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_alert_test.2621096307
Short name T274
Test name
Test status
Simulation time 24258964 ps
CPU time 0.85 seconds
Started Aug 28 09:43:29 PM UTC 24
Finished Aug 28 09:43:31 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621096307 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2621096307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.1717574138
Short name T281
Test name
Test status
Simulation time 791236058 ps
CPU time 60.88 seconds
Started Aug 28 09:42:58 PM UTC 24
Finished Aug 28 09:44:01 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717574138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1717574138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2823332793
Short name T289
Test name
Test status
Simulation time 15836056833 ps
CPU time 71.41 seconds
Started Aug 28 09:43:06 PM UTC 24
Finished Aug 28 09:44:19 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823332793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2823332793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.441112459
Short name T489
Test name
Test status
Simulation time 12582788361 ps
CPU time 1252.87 seconds
Started Aug 28 09:43:04 PM UTC 24
Finished Aug 28 10:04:10 PM UTC 24
Peak memory 750116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441112459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.441112459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_error.2590235963
Short name T313
Test name
Test status
Simulation time 13241441635 ps
CPU time 192.19 seconds
Started Aug 28 09:43:18 PM UTC 24
Finished Aug 28 09:46:33 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590235963 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2590235963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_long_msg.2822560480
Short name T303
Test name
Test status
Simulation time 7523732721 ps
CPU time 169.9 seconds
Started Aug 28 09:42:55 PM UTC 24
Finished Aug 28 09:45:48 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822560480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2822560480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_smoke.1452370865
Short name T267
Test name
Test status
Simulation time 5234284191 ps
CPU time 6.66 seconds
Started Aug 28 09:42:50 PM UTC 24
Finished Aug 28 09:42:58 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452370865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1452370865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_stress_all.1701672008
Short name T496
Test name
Test status
Simulation time 56513816821 ps
CPU time 1510.59 seconds
Started Aug 28 09:43:21 PM UTC 24
Finished Aug 28 10:08:48 PM UTC 24
Peak memory 754096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701672008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1701672008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.258938771
Short name T280
Test name
Test status
Simulation time 1029062214 ps
CPU time 35.89 seconds
Started Aug 28 09:43:21 PM UTC 24
Finished Aug 28 09:43:58 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258938771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.258938771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_alert_test.523509472
Short name T282
Test name
Test status
Simulation time 26574793 ps
CPU time 0.81 seconds
Started Aug 28 09:44:03 PM UTC 24
Finished Aug 28 09:44:04 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523509472 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.523509472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.3857212437
Short name T277
Test name
Test status
Simulation time 52761478 ps
CPU time 4.26 seconds
Started Aug 28 09:43:39 PM UTC 24
Finished Aug 28 09:43:45 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857212437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3857212437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.740588199
Short name T161
Test name
Test status
Simulation time 3873696005 ps
CPU time 50.99 seconds
Started Aug 28 09:43:47 PM UTC 24
Finished Aug 28 09:44:39 PM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740588199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.740588199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2824752833
Short name T353
Test name
Test status
Simulation time 1603630635 ps
CPU time 342.62 seconds
Started Aug 28 09:43:46 PM UTC 24
Finished Aug 28 09:49:35 PM UTC 24
Peak memory 680092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824752833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2824752833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_error.783972989
Short name T308
Test name
Test status
Simulation time 13807663991 ps
CPU time 148.76 seconds
Started Aug 28 09:43:48 PM UTC 24
Finished Aug 28 09:46:19 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783972989 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.783972989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3529219294
Short name T314
Test name
Test status
Simulation time 9467521166 ps
CPU time 171.35 seconds
Started Aug 28 09:43:39 PM UTC 24
Finished Aug 28 09:46:33 PM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529219294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3529219294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_smoke.2371569344
Short name T278
Test name
Test status
Simulation time 1614476564 ps
CPU time 13.98 seconds
Started Aug 28 09:43:32 PM UTC 24
Finished Aug 28 09:43:47 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371569344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2371569344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_stress_all.1055723645
Short name T131
Test name
Test status
Simulation time 18709483764 ps
CPU time 322.55 seconds
Started Aug 28 09:43:59 PM UTC 24
Finished Aug 28 09:49:26 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055723645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1055723645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.2222241418
Short name T283
Test name
Test status
Simulation time 1777355562 ps
CPU time 8.08 seconds
Started Aug 28 09:43:57 PM UTC 24
Finished Aug 28 09:44:06 PM UTC 24
Peak memory 207128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222241418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2222241418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_alert_test.497968202
Short name T290
Test name
Test status
Simulation time 21476441 ps
CPU time 0.81 seconds
Started Aug 28 09:44:20 PM UTC 24
Finished Aug 28 09:44:21 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497968202 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.497968202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.2757456668
Short name T291
Test name
Test status
Simulation time 2324507984 ps
CPU time 25.43 seconds
Started Aug 28 09:44:10 PM UTC 24
Finished Aug 28 09:44:37 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757456668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2757456668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.2564841611
Short name T159
Test name
Test status
Simulation time 1264747340 ps
CPU time 69.19 seconds
Started Aug 28 09:44:11 PM UTC 24
Finished Aug 28 09:45:22 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564841611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2564841611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.3680767929
Short name T346
Test name
Test status
Simulation time 1135695828 ps
CPU time 286.18 seconds
Started Aug 28 09:44:10 PM UTC 24
Finished Aug 28 09:49:00 PM UTC 24
Peak memory 706736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680767929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3680767929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_error.3568304571
Short name T321
Test name
Test status
Simulation time 44341776340 ps
CPU time 182.38 seconds
Started Aug 28 09:44:18 PM UTC 24
Finished Aug 28 09:47:24 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568304571 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3568304571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_long_msg.969034237
Short name T294
Test name
Test status
Simulation time 2356231304 ps
CPU time 48.43 seconds
Started Aug 28 09:44:07 PM UTC 24
Finished Aug 28 09:44:57 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969034237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.969034237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_smoke.2739438895
Short name T286
Test name
Test status
Simulation time 68144127 ps
CPU time 3.12 seconds
Started Aug 28 09:44:06 PM UTC 24
Finished Aug 28 09:44:10 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739438895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2739438895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_stress_all.1619459004
Short name T72
Test name
Test status
Simulation time 588373860798 ps
CPU time 2798.69 seconds
Started Aug 28 09:44:18 PM UTC 24
Finished Aug 28 10:31:29 PM UTC 24
Peak memory 729636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619459004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1619459004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.3049513006
Short name T292
Test name
Test status
Simulation time 2700308721 ps
CPU time 24.73 seconds
Started Aug 28 09:44:18 PM UTC 24
Finished Aug 28 09:44:45 PM UTC 24
Peak memory 206924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049513006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3049513006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_alert_test.3799297370
Short name T296
Test name
Test status
Simulation time 186014194 ps
CPU time 0.89 seconds
Started Aug 28 09:44:58 PM UTC 24
Finished Aug 28 09:45:00 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799297370 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3799297370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.979874730
Short name T30
Test name
Test status
Simulation time 5361217887 ps
CPU time 76.33 seconds
Started Aug 28 09:44:36 PM UTC 24
Finished Aug 28 09:45:54 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979874730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.979874730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.2761132037
Short name T164
Test name
Test status
Simulation time 1636601280 ps
CPU time 41.64 seconds
Started Aug 28 09:44:40 PM UTC 24
Finished Aug 28 09:45:23 PM UTC 24
Peak memory 215688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761132037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2761132037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.3610021256
Short name T385
Test name
Test status
Simulation time 9375762020 ps
CPU time 460.74 seconds
Started Aug 28 09:44:38 PM UTC 24
Finished Aug 28 09:52:24 PM UTC 24
Peak memory 678108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610021256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3610021256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_error.88470943
Short name T306
Test name
Test status
Simulation time 13608549538 ps
CPU time 81.74 seconds
Started Aug 28 09:44:42 PM UTC 24
Finished Aug 28 09:46:06 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88470943 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.88470943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_long_msg.3590129340
Short name T339
Test name
Test status
Simulation time 16287317215 ps
CPU time 252.07 seconds
Started Aug 28 09:44:26 PM UTC 24
Finished Aug 28 09:48:42 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590129340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3590129340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_smoke.118232744
Short name T293
Test name
Test status
Simulation time 1051614382 ps
CPU time 18.53 seconds
Started Aug 28 09:44:26 PM UTC 24
Finished Aug 28 09:44:45 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118232744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.118232744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.820734561
Short name T301
Test name
Test status
Simulation time 8268035787 ps
CPU time 54.82 seconds
Started Aug 28 09:44:45 PM UTC 24
Finished Aug 28 09:45:42 PM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820734561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.820734561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1551206453
Short name T302
Test name
Test status
Simulation time 15199844 ps
CPU time 0.89 seconds
Started Aug 28 09:45:43 PM UTC 24
Finished Aug 28 09:45:45 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551206453 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1551206453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.1197723035
Short name T300
Test name
Test status
Simulation time 306133359 ps
CPU time 15.87 seconds
Started Aug 28 09:45:21 PM UTC 24
Finished Aug 28 09:45:38 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197723035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1197723035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.348293535
Short name T328
Test name
Test status
Simulation time 15702907954 ps
CPU time 128.31 seconds
Started Aug 28 09:45:23 PM UTC 24
Finished Aug 28 09:47:34 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348293535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.348293535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.4145980416
Short name T335
Test name
Test status
Simulation time 1939228186 ps
CPU time 176.9 seconds
Started Aug 28 09:45:21 PM UTC 24
Finished Aug 28 09:48:21 PM UTC 24
Peak memory 667812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145980416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4145980416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_error.302927374
Short name T338
Test name
Test status
Simulation time 42190930500 ps
CPU time 183.89 seconds
Started Aug 28 09:45:24 PM UTC 24
Finished Aug 28 09:48:31 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302927374 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.302927374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_long_msg.785683281
Short name T299
Test name
Test status
Simulation time 1252674063 ps
CPU time 29.65 seconds
Started Aug 28 09:45:00 PM UTC 24
Finished Aug 28 09:45:31 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785683281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.785683281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_smoke.3106170448
Short name T298
Test name
Test status
Simulation time 620536244 ps
CPU time 16.67 seconds
Started Aug 28 09:44:59 PM UTC 24
Finished Aug 28 09:45:17 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106170448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3106170448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_stress_all.1144716053
Short name T530
Test name
Test status
Simulation time 739683464060 ps
CPU time 5706.48 seconds
Started Aug 28 09:45:39 PM UTC 24
Finished Aug 28 11:21:48 PM UTC 24
Peak memory 813184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144716053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1144716053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.1855744217
Short name T331
Test name
Test status
Simulation time 6494572049 ps
CPU time 147.1 seconds
Started Aug 28 09:45:32 PM UTC 24
Finished Aug 28 09:48:02 PM UTC 24
Peak memory 207584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855744217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1855744217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_alert_test.3419181812
Short name T310
Test name
Test status
Simulation time 18384855 ps
CPU time 0.81 seconds
Started Aug 28 09:46:25 PM UTC 24
Finished Aug 28 09:46:27 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419181812 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3419181812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.738615119
Short name T304
Test name
Test status
Simulation time 99934432 ps
CPU time 4.18 seconds
Started Aug 28 09:45:56 PM UTC 24
Finished Aug 28 09:46:01 PM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738615119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.738615119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.301893538
Short name T320
Test name
Test status
Simulation time 9623982837 ps
CPU time 69.65 seconds
Started Aug 28 09:46:03 PM UTC 24
Finished Aug 28 09:47:14 PM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301893538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.301893538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.802640457
Short name T348
Test name
Test status
Simulation time 5082194810 ps
CPU time 188.7 seconds
Started Aug 28 09:46:02 PM UTC 24
Finished Aug 28 09:49:13 PM UTC 24
Peak memory 653728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802640457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.802640457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_error.2984027549
Short name T330
Test name
Test status
Simulation time 2504226854 ps
CPU time 90.22 seconds
Started Aug 28 09:46:07 PM UTC 24
Finished Aug 28 09:47:40 PM UTC 24
Peak memory 207172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984027549 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2984027549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_long_msg.1545240738
Short name T271
Test name
Test status
Simulation time 7742307691 ps
CPU time 134.64 seconds
Started Aug 28 09:45:50 PM UTC 24
Finished Aug 28 09:48:07 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545240738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1545240738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_smoke.2855311259
Short name T305
Test name
Test status
Simulation time 4511130796 ps
CPU time 15.11 seconds
Started Aug 28 09:45:46 PM UTC 24
Finished Aug 28 09:46:02 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855311259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2855311259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_stress_all.2319626041
Short name T519
Test name
Test status
Simulation time 44186980579 ps
CPU time 2054.59 seconds
Started Aug 28 09:46:20 PM UTC 24
Finished Aug 28 10:20:58 PM UTC 24
Peak memory 723312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319626041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2319626041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.1207989783
Short name T315
Test name
Test status
Simulation time 926898486 ps
CPU time 17.01 seconds
Started Aug 28 09:46:18 PM UTC 24
Finished Aug 28 09:46:36 PM UTC 24
Peak memory 207124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207989783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1207989783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_alert_test.3822241784
Short name T50
Test name
Test status
Simulation time 50225253 ps
CPU time 0.85 seconds
Started Aug 28 09:33:50 PM UTC 24
Finished Aug 28 09:33:52 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822241784 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3822241784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.1260126078
Short name T154
Test name
Test status
Simulation time 1523569031 ps
CPU time 101.62 seconds
Started Aug 28 09:33:24 PM UTC 24
Finished Aug 28 09:35:07 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260126078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1260126078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.1390467005
Short name T116
Test name
Test status
Simulation time 1361734031 ps
CPU time 12.33 seconds
Started Aug 28 09:33:26 PM UTC 24
Finished Aug 28 09:33:40 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390467005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1390467005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.4173949853
Short name T254
Test name
Test status
Simulation time 6072995707 ps
CPU time 526.3 seconds
Started Aug 28 09:33:26 PM UTC 24
Finished Aug 28 09:42:19 PM UTC 24
Peak memory 715104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173949853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4173949853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_error.1968602680
Short name T178
Test name
Test status
Simulation time 34884618121 ps
CPU time 133.32 seconds
Started Aug 28 09:33:26 PM UTC 24
Finished Aug 28 09:35:42 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968602680 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1968602680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2407747556
Short name T155
Test name
Test status
Simulation time 9418056760 ps
CPU time 155.21 seconds
Started Aug 28 09:33:22 PM UTC 24
Finished Aug 28 09:35:59 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407747556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2407747556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.814025016
Short name T52
Test name
Test status
Simulation time 78768386 ps
CPU time 1.26 seconds
Started Aug 28 09:33:47 PM UTC 24
Finished Aug 28 09:33:49 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814025016 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.814025016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_smoke.1929768801
Short name T144
Test name
Test status
Simulation time 41877277 ps
CPU time 2.73 seconds
Started Aug 28 09:33:22 PM UTC 24
Finished Aug 28 09:33:25 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929768801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1929768801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.703690496
Short name T173
Test name
Test status
Simulation time 8690305395 ps
CPU time 82.8 seconds
Started Aug 28 09:33:35 PM UTC 24
Finished Aug 28 09:35:00 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703690496 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.703690496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.3698664683
Short name T63
Test name
Test status
Simulation time 3711477319 ps
CPU time 59.28 seconds
Started Aug 28 09:33:37 PM UTC 24
Finished Aug 28 09:34:38 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698664683 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3698664683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.3835804126
Short name T174
Test name
Test status
Simulation time 2268284407 ps
CPU time 81.86 seconds
Started Aug 28 09:33:38 PM UTC 24
Finished Aug 28 09:35:02 PM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835804126 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3835804126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.3014460660
Short name T297
Test name
Test status
Simulation time 70172057531 ps
CPU time 699.14 seconds
Started Aug 28 09:33:29 PM UTC 24
Finished Aug 28 09:45:17 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014460660 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3014460660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.2736714600
Short name T504
Test name
Test status
Simulation time 245405163072 ps
CPU time 2458.03 seconds
Started Aug 28 09:33:31 PM UTC 24
Finished Aug 28 10:14:57 PM UTC 24
Peak memory 221436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736714600 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2736714600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.758095883
Short name T516
Test name
Test status
Simulation time 544385563337 ps
CPU time 2775.07 seconds
Started Aug 28 09:33:32 PM UTC 24
Finished Aug 28 10:20:18 PM UTC 24
Peak memory 227396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758095883 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.758095883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.2247380889
Short name T65
Test name
Test status
Simulation time 6499784321 ps
CPU time 72.64 seconds
Started Aug 28 09:33:29 PM UTC 24
Finished Aug 28 09:34:43 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247380889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2247380889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_alert_test.2492120505
Short name T318
Test name
Test status
Simulation time 94877946 ps
CPU time 0.93 seconds
Started Aug 28 09:47:07 PM UTC 24
Finished Aug 28 09:47:09 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492120505 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2492120505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3668206270
Short name T319
Test name
Test status
Simulation time 1003757380 ps
CPU time 29.22 seconds
Started Aug 28 09:46:39 PM UTC 24
Finished Aug 28 09:47:09 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668206270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3668206270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.4148830895
Short name T322
Test name
Test status
Simulation time 3409750460 ps
CPU time 45.02 seconds
Started Aug 28 09:46:39 PM UTC 24
Finished Aug 28 09:47:26 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148830895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4148830895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.416028050
Short name T420
Test name
Test status
Simulation time 2533215816 ps
CPU time 500.56 seconds
Started Aug 28 09:46:39 PM UTC 24
Finished Aug 28 09:55:06 PM UTC 24
Peak memory 522536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416028050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.416028050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_error.420408106
Short name T368
Test name
Test status
Simulation time 22244723712 ps
CPU time 238.54 seconds
Started Aug 28 09:46:39 PM UTC 24
Finished Aug 28 09:50:42 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420408106 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.420408106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_long_msg.1718611083
Short name T336
Test name
Test status
Simulation time 2954822282 ps
CPU time 111.56 seconds
Started Aug 28 09:46:32 PM UTC 24
Finished Aug 28 09:48:26 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718611083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1718611083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_smoke.624181129
Short name T316
Test name
Test status
Simulation time 1051931376 ps
CPU time 19.31 seconds
Started Aug 28 09:46:28 PM UTC 24
Finished Aug 28 09:46:50 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624181129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.624181129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_stress_all.2987986273
Short name T483
Test name
Test status
Simulation time 10706315002 ps
CPU time 886.67 seconds
Started Aug 28 09:46:58 PM UTC 24
Finished Aug 28 10:01:55 PM UTC 24
Peak memory 655716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987986273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2987986273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.2066769953
Short name T325
Test name
Test status
Simulation time 747230206 ps
CPU time 36.34 seconds
Started Aug 28 09:46:50 PM UTC 24
Finished Aug 28 09:47:28 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066769953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2066769953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_alert_test.280044887
Short name T326
Test name
Test status
Simulation time 20500726 ps
CPU time 0.86 seconds
Started Aug 28 09:47:29 PM UTC 24
Finished Aug 28 09:47:30 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280044887 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.280044887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.661082501
Short name T345
Test name
Test status
Simulation time 2816024186 ps
CPU time 99.48 seconds
Started Aug 28 09:47:16 PM UTC 24
Finished Aug 28 09:48:57 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661082501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.661082501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.3886324561
Short name T324
Test name
Test status
Simulation time 141248222 ps
CPU time 3.93 seconds
Started Aug 28 09:47:23 PM UTC 24
Finished Aug 28 09:47:28 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886324561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3886324561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.310105897
Short name T350
Test name
Test status
Simulation time 847015897 ps
CPU time 114.77 seconds
Started Aug 28 09:47:19 PM UTC 24
Finished Aug 28 09:49:16 PM UTC 24
Peak memory 371048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310105897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.310105897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_error.2556430124
Short name T392
Test name
Test status
Simulation time 8357368537 ps
CPU time 307.88 seconds
Started Aug 28 09:47:26 PM UTC 24
Finished Aug 28 09:52:38 PM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556430124 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2556430124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_long_msg.374544476
Short name T366
Test name
Test status
Simulation time 3017900560 ps
CPU time 203.59 seconds
Started Aug 28 09:47:11 PM UTC 24
Finished Aug 28 09:50:38 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374544476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.374544476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_smoke.922701650
Short name T327
Test name
Test status
Simulation time 840108019 ps
CPU time 19.56 seconds
Started Aug 28 09:47:11 PM UTC 24
Finished Aug 28 09:47:32 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922701650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.922701650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_stress_all.358800826
Short name T69
Test name
Test status
Simulation time 46473480042 ps
CPU time 1064.2 seconds
Started Aug 28 09:47:27 PM UTC 24
Finished Aug 28 10:05:25 PM UTC 24
Peak memory 721124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358800826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.358800826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1686631412
Short name T354
Test name
Test status
Simulation time 5454300510 ps
CPU time 126.33 seconds
Started Aug 28 09:47:27 PM UTC 24
Finished Aug 28 09:49:36 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686631412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1686631412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_alert_test.2914154730
Short name T332
Test name
Test status
Simulation time 18701380 ps
CPU time 0.82 seconds
Started Aug 28 09:48:07 PM UTC 24
Finished Aug 28 09:48:09 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914154730 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2914154730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.1647464165
Short name T356
Test name
Test status
Simulation time 6108421686 ps
CPU time 126.6 seconds
Started Aug 28 09:47:33 PM UTC 24
Finished Aug 28 09:49:42 PM UTC 24
Peak memory 217740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647464165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1647464165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.2090136970
Short name T334
Test name
Test status
Simulation time 1828763381 ps
CPU time 35.64 seconds
Started Aug 28 09:47:44 PM UTC 24
Finished Aug 28 09:48:21 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090136970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2090136970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.1928635427
Short name T463
Test name
Test status
Simulation time 17931704455 ps
CPU time 647.38 seconds
Started Aug 28 09:47:34 PM UTC 24
Finished Aug 28 09:58:29 PM UTC 24
Peak memory 694564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928635427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1928635427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_error.1822370774
Short name T376
Test name
Test status
Simulation time 36756012620 ps
CPU time 227.97 seconds
Started Aug 28 09:47:45 PM UTC 24
Finished Aug 28 09:51:37 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822370774 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1822370774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_long_msg.1080248257
Short name T343
Test name
Test status
Simulation time 40438390307 ps
CPU time 73.44 seconds
Started Aug 28 09:47:31 PM UTC 24
Finished Aug 28 09:48:46 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080248257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1080248257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_smoke.3341219999
Short name T329
Test name
Test status
Simulation time 677295484 ps
CPU time 8.72 seconds
Started Aug 28 09:47:30 PM UTC 24
Finished Aug 28 09:47:40 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341219999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3341219999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_stress_all.3956624408
Short name T130
Test name
Test status
Simulation time 27526635 ps
CPU time 0.96 seconds
Started Aug 28 09:48:04 PM UTC 24
Finished Aug 28 09:48:06 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956624408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3956624408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.1438486662
Short name T341
Test name
Test status
Simulation time 2113886916 ps
CPU time 58.26 seconds
Started Aug 28 09:47:45 PM UTC 24
Finished Aug 28 09:48:45 PM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438486662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1438486662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_alert_test.3772712111
Short name T342
Test name
Test status
Simulation time 23593269 ps
CPU time 0.84 seconds
Started Aug 28 09:48:43 PM UTC 24
Finished Aug 28 09:48:45 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772712111 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3772712111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.2710284881
Short name T344
Test name
Test status
Simulation time 580902788 ps
CPU time 32.43 seconds
Started Aug 28 09:48:21 PM UTC 24
Finished Aug 28 09:48:55 PM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710284881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2710284881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.1530331227
Short name T355
Test name
Test status
Simulation time 13510553398 ps
CPU time 77.8 seconds
Started Aug 28 09:48:22 PM UTC 24
Finished Aug 28 09:49:42 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530331227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1530331227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.2128676758
Short name T497
Test name
Test status
Simulation time 20317438013 ps
CPU time 1348.13 seconds
Started Aug 28 09:48:22 PM UTC 24
Finished Aug 28 10:11:05 PM UTC 24
Peak memory 776396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128676758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2128676758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_error.3023139729
Short name T340
Test name
Test status
Simulation time 963095492 ps
CPU time 16.43 seconds
Started Aug 28 09:48:27 PM UTC 24
Finished Aug 28 09:48:45 PM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023139729 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3023139729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_long_msg.1346421429
Short name T370
Test name
Test status
Simulation time 23824206215 ps
CPU time 156.54 seconds
Started Aug 28 09:48:10 PM UTC 24
Finished Aug 28 09:50:49 PM UTC 24
Peak memory 217820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346421429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1346421429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_smoke.1294315504
Short name T333
Test name
Test status
Simulation time 253867321 ps
CPU time 10.04 seconds
Started Aug 28 09:48:09 PM UTC 24
Finished Aug 28 09:48:20 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294315504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1294315504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_stress_all.1828853118
Short name T380
Test name
Test status
Simulation time 107114386571 ps
CPU time 197.58 seconds
Started Aug 28 09:48:34 PM UTC 24
Finished Aug 28 09:51:55 PM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828853118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1828853118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.3993608978
Short name T88
Test name
Test status
Simulation time 22902606670 ps
CPU time 178.19 seconds
Started Aug 28 09:48:34 PM UTC 24
Finished Aug 28 09:51:35 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993608978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3993608978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_alert_test.426731915
Short name T351
Test name
Test status
Simulation time 52907501 ps
CPU time 0.9 seconds
Started Aug 28 09:49:15 PM UTC 24
Finished Aug 28 09:49:17 PM UTC 24
Peak memory 203292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426731915 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.426731915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.959523702
Short name T361
Test name
Test status
Simulation time 4459720714 ps
CPU time 82.97 seconds
Started Aug 28 09:48:47 PM UTC 24
Finished Aug 28 09:50:12 PM UTC 24
Peak memory 206964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959523702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.959523702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.3524373203
Short name T165
Test name
Test status
Simulation time 2711079839 ps
CPU time 91.23 seconds
Started Aug 28 09:48:55 PM UTC 24
Finished Aug 28 09:50:29 PM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524373203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3524373203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.4193547478
Short name T478
Test name
Test status
Simulation time 7113584160 ps
CPU time 675.48 seconds
Started Aug 28 09:48:48 PM UTC 24
Finished Aug 28 10:00:11 PM UTC 24
Peak memory 727528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193547478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4193547478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_error.3845289905
Short name T400
Test name
Test status
Simulation time 57937688366 ps
CPU time 234.41 seconds
Started Aug 28 09:48:59 PM UTC 24
Finished Aug 28 09:52:57 PM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845289905 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3845289905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_long_msg.207398873
Short name T377
Test name
Test status
Simulation time 2286071375 ps
CPU time 170.3 seconds
Started Aug 28 09:48:47 PM UTC 24
Finished Aug 28 09:51:40 PM UTC 24
Peak memory 207060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207398873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.207398873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_smoke.3968246699
Short name T347
Test name
Test status
Simulation time 2922813448 ps
CPU time 15.32 seconds
Started Aug 28 09:48:45 PM UTC 24
Finished Aug 28 09:49:02 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968246699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3968246699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_stress_all.739291327
Short name T449
Test name
Test status
Simulation time 57984075208 ps
CPU time 484.6 seconds
Started Aug 28 09:49:03 PM UTC 24
Finished Aug 28 09:57:13 PM UTC 24
Peak memory 708892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739291327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.739291327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.2488973927
Short name T349
Test name
Test status
Simulation time 591943937 ps
CPU time 12.18 seconds
Started Aug 28 09:49:01 PM UTC 24
Finished Aug 28 09:49:15 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488973927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2488973927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_alert_test.733043784
Short name T357
Test name
Test status
Simulation time 168090334 ps
CPU time 0.83 seconds
Started Aug 28 09:49:44 PM UTC 24
Finished Aug 28 09:49:46 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733043784 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.733043784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.1139570011
Short name T362
Test name
Test status
Simulation time 2869276946 ps
CPU time 53.7 seconds
Started Aug 28 09:49:18 PM UTC 24
Finished Aug 28 09:50:13 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139570011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1139570011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.2710596445
Short name T363
Test name
Test status
Simulation time 6265805016 ps
CPU time 59.91 seconds
Started Aug 28 09:49:32 PM UTC 24
Finished Aug 28 09:50:33 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710596445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2710596445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1779215604
Short name T501
Test name
Test status
Simulation time 27340521513 ps
CPU time 1392.23 seconds
Started Aug 28 09:49:29 PM UTC 24
Finished Aug 28 10:12:57 PM UTC 24
Peak memory 739560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779215604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1779215604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_error.2914097874
Short name T411
Test name
Test status
Simulation time 26310969635 ps
CPU time 240.73 seconds
Started Aug 28 09:49:36 PM UTC 24
Finished Aug 28 09:53:40 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914097874 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2914097874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_long_msg.980621654
Short name T359
Test name
Test status
Simulation time 642162027 ps
CPU time 36.9 seconds
Started Aug 28 09:49:17 PM UTC 24
Finished Aug 28 09:49:55 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980621654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.980621654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_smoke.1804854608
Short name T352
Test name
Test status
Simulation time 3284340418 ps
CPU time 14.52 seconds
Started Aug 28 09:49:15 PM UTC 24
Finished Aug 28 09:49:31 PM UTC 24
Peak memory 206932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804854608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1804854608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_stress_all.2815612168
Short name T74
Test name
Test status
Simulation time 93251220755 ps
CPU time 3086.36 seconds
Started Aug 28 09:49:44 PM UTC 24
Finished Aug 28 10:41:44 PM UTC 24
Peak memory 833884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815612168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2815612168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.2240457732
Short name T360
Test name
Test status
Simulation time 9520817596 ps
CPU time 31.73 seconds
Started Aug 28 09:49:37 PM UTC 24
Finished Aug 28 09:50:10 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240457732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2240457732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_alert_test.3019356828
Short name T364
Test name
Test status
Simulation time 36379244 ps
CPU time 0.86 seconds
Started Aug 28 09:50:35 PM UTC 24
Finished Aug 28 09:50:37 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019356828 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3019356828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.4161630022
Short name T41
Test name
Test status
Simulation time 3484822631 ps
CPU time 73.98 seconds
Started Aug 28 09:49:56 PM UTC 24
Finished Aug 28 09:51:12 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161630022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4161630022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.1567224616
Short name T490
Test name
Test status
Simulation time 19117292819 ps
CPU time 831.2 seconds
Started Aug 28 09:50:11 PM UTC 24
Finished Aug 28 10:04:11 PM UTC 24
Peak memory 727316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567224616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1567224616
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_error.2787354181
Short name T384
Test name
Test status
Simulation time 3681163318 ps
CPU time 126.32 seconds
Started Aug 28 09:50:14 PM UTC 24
Finished Aug 28 09:52:23 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787354181 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2787354181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_long_msg.3129320795
Short name T371
Test name
Test status
Simulation time 10447575961 ps
CPU time 67.49 seconds
Started Aug 28 09:49:55 PM UTC 24
Finished Aug 28 09:51:04 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129320795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3129320795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_smoke.1109338065
Short name T358
Test name
Test status
Simulation time 157211977 ps
CPU time 5.28 seconds
Started Aug 28 09:49:47 PM UTC 24
Finished Aug 28 09:49:54 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109338065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1109338065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_stress_all.2993509088
Short name T71
Test name
Test status
Simulation time 71612070092 ps
CPU time 1427.49 seconds
Started Aug 28 09:50:30 PM UTC 24
Finished Aug 28 10:14:34 PM UTC 24
Peak memory 686296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993509088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2993509088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.2538972156
Short name T365
Test name
Test status
Simulation time 414544614 ps
CPU time 8.78 seconds
Started Aug 28 09:50:27 PM UTC 24
Finished Aug 28 09:50:37 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538972156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2538972156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_alert_test.3527745226
Short name T372
Test name
Test status
Simulation time 19389158 ps
CPU time 0.86 seconds
Started Aug 28 09:51:14 PM UTC 24
Finished Aug 28 09:51:15 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527745226 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3527745226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.324500151
Short name T373
Test name
Test status
Simulation time 761203165 ps
CPU time 46.03 seconds
Started Aug 28 09:50:40 PM UTC 24
Finished Aug 28 09:51:27 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324500151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.324500151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.585687869
Short name T383
Test name
Test status
Simulation time 5002038600 ps
CPU time 92.98 seconds
Started Aug 28 09:50:43 PM UTC 24
Finished Aug 28 09:52:19 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585687869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.585687869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.2431116687
Short name T498
Test name
Test status
Simulation time 7390310491 ps
CPU time 1289.96 seconds
Started Aug 28 09:50:43 PM UTC 24
Finished Aug 28 10:12:27 PM UTC 24
Peak memory 770280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431116687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2431116687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_error.4138144541
Short name T402
Test name
Test status
Simulation time 6450458940 ps
CPU time 135.16 seconds
Started Aug 28 09:50:46 PM UTC 24
Finished Aug 28 09:53:03 PM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138144541 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4138144541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_long_msg.106003138
Short name T374
Test name
Test status
Simulation time 6014745340 ps
CPU time 51.66 seconds
Started Aug 28 09:50:38 PM UTC 24
Finished Aug 28 09:51:31 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106003138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.106003138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_smoke.1494121351
Short name T369
Test name
Test status
Simulation time 101065437 ps
CPU time 5.71 seconds
Started Aug 28 09:50:38 PM UTC 24
Finished Aug 28 09:50:44 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494121351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1494121351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_stress_all.2781522653
Short name T394
Test name
Test status
Simulation time 18008675385 ps
CPU time 95.9 seconds
Started Aug 28 09:51:05 PM UTC 24
Finished Aug 28 09:52:43 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781522653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2781522653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2311024253
Short name T397
Test name
Test status
Simulation time 8972921400 ps
CPU time 114.87 seconds
Started Aug 28 09:50:51 PM UTC 24
Finished Aug 28 09:52:48 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311024253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2311024253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_alert_test.4290809409
Short name T379
Test name
Test status
Simulation time 92792960 ps
CPU time 0.79 seconds
Started Aug 28 09:51:51 PM UTC 24
Finished Aug 28 09:51:53 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290809409 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4290809409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.1369210690
Short name T378
Test name
Test status
Simulation time 415568599 ps
CPU time 7.9 seconds
Started Aug 28 09:51:32 PM UTC 24
Finished Aug 28 09:51:41 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369210690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1369210690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.2970014132
Short name T390
Test name
Test status
Simulation time 7608267796 ps
CPU time 54.22 seconds
Started Aug 28 09:51:37 PM UTC 24
Finished Aug 28 09:52:33 PM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970014132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2970014132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2564812525
Short name T510
Test name
Test status
Simulation time 7113181718 ps
CPU time 1485.59 seconds
Started Aug 28 09:51:34 PM UTC 24
Finished Aug 28 10:16:36 PM UTC 24
Peak memory 784680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564812525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2564812525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_error.3709789551
Short name T387
Test name
Test status
Simulation time 885254755 ps
CPU time 46.73 seconds
Started Aug 28 09:51:39 PM UTC 24
Finished Aug 28 09:52:28 PM UTC 24
Peak memory 207180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709789551 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3709789551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_long_msg.1180053601
Short name T423
Test name
Test status
Simulation time 13396125000 ps
CPU time 224.87 seconds
Started Aug 28 09:51:29 PM UTC 24
Finished Aug 28 09:55:18 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180053601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1180053601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_smoke.2066638826
Short name T375
Test name
Test status
Simulation time 1044545893 ps
CPU time 15.76 seconds
Started Aug 28 09:51:17 PM UTC 24
Finished Aug 28 09:51:34 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066638826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2066638826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_stress_all.2166333826
Short name T520
Test name
Test status
Simulation time 95464260489 ps
CPU time 1841.3 seconds
Started Aug 28 09:51:43 PM UTC 24
Finished Aug 28 10:22:46 PM UTC 24
Peak memory 747876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166333826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2166333826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.3430071220
Short name T405
Test name
Test status
Simulation time 1391319312 ps
CPU time 83.69 seconds
Started Aug 28 09:51:41 PM UTC 24
Finished Aug 28 09:53:07 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430071220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3430071220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_alert_test.3198970133
Short name T388
Test name
Test status
Simulation time 45875490 ps
CPU time 0.88 seconds
Started Aug 28 09:52:26 PM UTC 24
Finished Aug 28 09:52:28 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198970133 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3198970133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.3200973048
Short name T393
Test name
Test status
Simulation time 2989032959 ps
CPU time 35.88 seconds
Started Aug 28 09:52:04 PM UTC 24
Finished Aug 28 09:52:41 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200973048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3200973048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.3807099879
Short name T403
Test name
Test status
Simulation time 19672768883 ps
CPU time 44.24 seconds
Started Aug 28 09:52:20 PM UTC 24
Finished Aug 28 09:53:05 PM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807099879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3807099879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.2929440149
Short name T415
Test name
Test status
Simulation time 1072173086 ps
CPU time 106.27 seconds
Started Aug 28 09:52:08 PM UTC 24
Finished Aug 28 09:53:57 PM UTC 24
Peak memory 391200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929440149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2929440149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_error.3301227216
Short name T407
Test name
Test status
Simulation time 3891884748 ps
CPU time 51.43 seconds
Started Aug 28 09:52:21 PM UTC 24
Finished Aug 28 09:53:14 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301227216 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3301227216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_long_msg.3710947623
Short name T391
Test name
Test status
Simulation time 7581596815 ps
CPU time 38.32 seconds
Started Aug 28 09:51:57 PM UTC 24
Finished Aug 28 09:52:37 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710947623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3710947623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_smoke.3748888557
Short name T381
Test name
Test status
Simulation time 299383960 ps
CPU time 8.13 seconds
Started Aug 28 09:51:54 PM UTC 24
Finished Aug 28 09:52:03 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748888557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3748888557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_stress_all.1621835023
Short name T528
Test name
Test status
Simulation time 81602494663 ps
CPU time 2863.54 seconds
Started Aug 28 09:52:24 PM UTC 24
Finished Aug 28 10:40:41 PM UTC 24
Peak memory 760092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621835023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1621835023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.3249163646
Short name T419
Test name
Test status
Simulation time 5353121766 ps
CPU time 116.21 seconds
Started Aug 28 09:52:22 PM UTC 24
Finished Aug 28 09:54:20 PM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249163646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3249163646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_alert_test.966359532
Short name T62
Test name
Test status
Simulation time 27848583 ps
CPU time 0.83 seconds
Started Aug 28 09:34:35 PM UTC 24
Finished Aug 28 09:34:37 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966359532 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.966359532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.3655977496
Short name T121
Test name
Test status
Simulation time 430865628 ps
CPU time 8.03 seconds
Started Aug 28 09:33:52 PM UTC 24
Finished Aug 28 09:34:01 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655977496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3655977496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1544044977
Short name T389
Test name
Test status
Simulation time 6307341096 ps
CPU time 1105.73 seconds
Started Aug 28 09:33:53 PM UTC 24
Finished Aug 28 09:52:31 PM UTC 24
Peak memory 743652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544044977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1544044977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_long_msg.2933333414
Short name T64
Test name
Test status
Simulation time 1414028274 ps
CPU time 49.16 seconds
Started Aug 28 09:33:52 PM UTC 24
Finished Aug 28 09:34:43 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933333414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2933333414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.442768359
Short name T53
Test name
Test status
Simulation time 90706822 ps
CPU time 1.6 seconds
Started Aug 28 09:34:32 PM UTC 24
Finished Aug 28 09:34:34 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442768359 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.442768359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_stress_all.2662995161
Short name T158
Test name
Test status
Simulation time 8964061904 ps
CPU time 595.36 seconds
Started Aug 28 09:34:27 PM UTC 24
Finished Aug 28 09:44:31 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662995161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2662995161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.2187162110
Short name T177
Test name
Test status
Simulation time 3124589685 ps
CPU time 71.69 seconds
Started Aug 28 09:34:23 PM UTC 24
Finished Aug 28 09:35:37 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187162110 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2187162110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.3756493403
Short name T187
Test name
Test status
Simulation time 27328169705 ps
CPU time 124.93 seconds
Started Aug 28 09:34:23 PM UTC 24
Finished Aug 28 09:36:31 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756493403 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3756493403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.1374981927
Short name T191
Test name
Test status
Simulation time 22068419182 ps
CPU time 136.42 seconds
Started Aug 28 09:34:24 PM UTC 24
Finished Aug 28 09:36:43 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374981927 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1374981927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.1650747627
Short name T151
Test name
Test status
Simulation time 37955105341 ps
CPU time 602.9 seconds
Started Aug 28 09:34:03 PM UTC 24
Finished Aug 28 09:44:13 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650747627 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1650747627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.1495822961
Short name T509
Test name
Test status
Simulation time 299847191845 ps
CPU time 2479.05 seconds
Started Aug 28 09:34:08 PM UTC 24
Finished Aug 28 10:15:54 PM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495822961 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1495822961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1631031375
Short name T518
Test name
Test status
Simulation time 705418594603 ps
CPU time 2741.49 seconds
Started Aug 28 09:34:16 PM UTC 24
Finished Aug 28 10:20:29 PM UTC 24
Peak memory 227452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631031375 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1631031375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.614479331
Short name T170
Test name
Test status
Simulation time 762102529 ps
CPU time 18.16 seconds
Started Aug 28 09:34:02 PM UTC 24
Finished Aug 28 09:34:22 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614479331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.614479331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_alert_test.766458301
Short name T396
Test name
Test status
Simulation time 48182181 ps
CPU time 0.88 seconds
Started Aug 28 09:52:45 PM UTC 24
Finished Aug 28 09:52:47 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766458301 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.766458301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.58653385
Short name T398
Test name
Test status
Simulation time 264735777 ps
CPU time 20.24 seconds
Started Aug 28 09:52:30 PM UTC 24
Finished Aug 28 09:52:52 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58653385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.58653385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.3552443047
Short name T408
Test name
Test status
Simulation time 4925687805 ps
CPU time 45.21 seconds
Started Aug 28 09:52:34 PM UTC 24
Finished Aug 28 09:53:21 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552443047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3552443047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.217768020
Short name T502
Test name
Test status
Simulation time 23802115678 ps
CPU time 1237.54 seconds
Started Aug 28 09:52:34 PM UTC 24
Finished Aug 28 10:13:25 PM UTC 24
Peak memory 733384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217768020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.217768020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_error.3828286473
Short name T433
Test name
Test status
Simulation time 21828023304 ps
CPU time 188.19 seconds
Started Aug 28 09:52:37 PM UTC 24
Finished Aug 28 09:55:48 PM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828286473 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3828286473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1387103135
Short name T430
Test name
Test status
Simulation time 8984609196 ps
CPU time 185.03 seconds
Started Aug 28 09:52:28 PM UTC 24
Finished Aug 28 09:55:37 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387103135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1387103135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_smoke.2017650503
Short name T395
Test name
Test status
Simulation time 1358910965 ps
CPU time 15.39 seconds
Started Aug 28 09:52:28 PM UTC 24
Finished Aug 28 09:52:45 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017650503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2017650503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_stress_all.2364628491
Short name T522
Test name
Test status
Simulation time 137484527825 ps
CPU time 1859.75 seconds
Started Aug 28 09:52:43 PM UTC 24
Finished Aug 28 10:24:04 PM UTC 24
Peak memory 524492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364628491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2364628491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.469316149
Short name T89
Test name
Test status
Simulation time 207190879 ps
CPU time 12.8 seconds
Started Aug 28 09:52:41 PM UTC 24
Finished Aug 28 09:52:54 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469316149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.469316149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_alert_test.1856928912
Short name T404
Test name
Test status
Simulation time 15501650 ps
CPU time 0.85 seconds
Started Aug 28 09:53:05 PM UTC 24
Finished Aug 28 09:53:06 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856928912 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1856928912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.695029229
Short name T417
Test name
Test status
Simulation time 5857868790 ps
CPU time 74.38 seconds
Started Aug 28 09:52:50 PM UTC 24
Finished Aug 28 09:54:06 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695029229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.695029229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.1469329041
Short name T413
Test name
Test status
Simulation time 2788722551 ps
CPU time 47.89 seconds
Started Aug 28 09:52:56 PM UTC 24
Finished Aug 28 09:53:45 PM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469329041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1469329041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.2943778127
Short name T491
Test name
Test status
Simulation time 3947680577 ps
CPU time 674.2 seconds
Started Aug 28 09:52:53 PM UTC 24
Finished Aug 28 10:04:15 PM UTC 24
Peak memory 733668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943778127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2943778127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_error.3172792723
Short name T409
Test name
Test status
Simulation time 1429783698 ps
CPU time 28.67 seconds
Started Aug 28 09:52:56 PM UTC 24
Finished Aug 28 09:53:26 PM UTC 24
Peak memory 207172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172792723 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3172792723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_long_msg.622703477
Short name T426
Test name
Test status
Simulation time 2722515134 ps
CPU time 155.73 seconds
Started Aug 28 09:52:48 PM UTC 24
Finished Aug 28 09:55:27 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622703477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.622703477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_smoke.1697264954
Short name T401
Test name
Test status
Simulation time 2538088416 ps
CPU time 14.38 seconds
Started Aug 28 09:52:47 PM UTC 24
Finished Aug 28 09:53:02 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697264954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1697264954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_stress_all.3213419694
Short name T93
Test name
Test status
Simulation time 23651032397 ps
CPU time 388.42 seconds
Started Aug 28 09:53:03 PM UTC 24
Finished Aug 28 09:59:37 PM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213419694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3213419694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.467243584
Short name T90
Test name
Test status
Simulation time 37111709128 ps
CPU time 134.47 seconds
Started Aug 28 09:52:59 PM UTC 24
Finished Aug 28 09:55:16 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467243584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.467243584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_alert_test.1205033987
Short name T412
Test name
Test status
Simulation time 14037864 ps
CPU time 0.87 seconds
Started Aug 28 09:53:42 PM UTC 24
Finished Aug 28 09:53:44 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205033987 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1205033987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.2400670892
Short name T414
Test name
Test status
Simulation time 3163177157 ps
CPU time 43.95 seconds
Started Aug 28 09:53:08 PM UTC 24
Finished Aug 28 09:53:54 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400670892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2400670892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.1256371063
Short name T421
Test name
Test status
Simulation time 4996199132 ps
CPU time 112.23 seconds
Started Aug 28 09:53:15 PM UTC 24
Finished Aug 28 09:55:09 PM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256371063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1256371063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.2561556218
Short name T482
Test name
Test status
Simulation time 2690207674 ps
CPU time 479.07 seconds
Started Aug 28 09:53:12 PM UTC 24
Finished Aug 28 10:01:17 PM UTC 24
Peak memory 748004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561556218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2561556218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_error.1571788025
Short name T443
Test name
Test status
Simulation time 37481522176 ps
CPU time 205.36 seconds
Started Aug 28 09:53:22 PM UTC 24
Finished Aug 28 09:56:51 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571788025 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1571788025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_long_msg.1744270238
Short name T410
Test name
Test status
Simulation time 1517196768 ps
CPU time 25.56 seconds
Started Aug 28 09:53:08 PM UTC 24
Finished Aug 28 09:53:35 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744270238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1744270238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_smoke.147211974
Short name T406
Test name
Test status
Simulation time 350596834 ps
CPU time 3.48 seconds
Started Aug 28 09:53:07 PM UTC 24
Finished Aug 28 09:53:11 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147211974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.147211974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_stress_all.3754670369
Short name T525
Test name
Test status
Simulation time 88987834576 ps
CPU time 2053.52 seconds
Started Aug 28 09:53:36 PM UTC 24
Finished Aug 28 10:28:14 PM UTC 24
Peak memory 739852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754670369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3754670369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.595815277
Short name T92
Test name
Test status
Simulation time 49145018136 ps
CPU time 189.48 seconds
Started Aug 28 09:53:27 PM UTC 24
Finished Aug 28 09:56:40 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595815277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.595815277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_alert_test.1115356782
Short name T422
Test name
Test status
Simulation time 13874609 ps
CPU time 0.87 seconds
Started Aug 28 09:55:08 PM UTC 24
Finished Aug 28 09:55:10 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115356782 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1115356782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.1792050083
Short name T425
Test name
Test status
Simulation time 7178942627 ps
CPU time 85.67 seconds
Started Aug 28 09:53:55 PM UTC 24
Finished Aug 28 09:55:23 PM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792050083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1792050083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.1001211724
Short name T418
Test name
Test status
Simulation time 317049453 ps
CPU time 4.65 seconds
Started Aug 28 09:54:02 PM UTC 24
Finished Aug 28 09:54:07 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001211724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1001211724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.4215600635
Short name T492
Test name
Test status
Simulation time 4203727892 ps
CPU time 674.17 seconds
Started Aug 28 09:53:58 PM UTC 24
Finished Aug 28 10:05:20 PM UTC 24
Peak memory 710884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215600635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4215600635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_error.3009443260
Short name T428
Test name
Test status
Simulation time 4117388097 ps
CPU time 83.34 seconds
Started Aug 28 09:54:07 PM UTC 24
Finished Aug 28 09:55:33 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009443260 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3009443260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_long_msg.2699801174
Short name T441
Test name
Test status
Simulation time 5992834171 ps
CPU time 175.56 seconds
Started Aug 28 09:53:46 PM UTC 24
Finished Aug 28 09:56:44 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699801174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2699801174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_smoke.2214364741
Short name T416
Test name
Test status
Simulation time 1200355178 ps
CPU time 14.6 seconds
Started Aug 28 09:53:46 PM UTC 24
Finished Aug 28 09:54:01 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214364741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2214364741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_stress_all.103708820
Short name T485
Test name
Test status
Simulation time 90522193753 ps
CPU time 503.52 seconds
Started Aug 28 09:54:22 PM UTC 24
Finished Aug 28 10:02:53 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103708820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.103708820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.3704259536
Short name T424
Test name
Test status
Simulation time 28327050300 ps
CPU time 68.1 seconds
Started Aug 28 09:54:08 PM UTC 24
Finished Aug 28 09:55:19 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704259536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3704259536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2209398103
Short name T429
Test name
Test status
Simulation time 15551763 ps
CPU time 0.79 seconds
Started Aug 28 09:55:34 PM UTC 24
Finished Aug 28 09:55:36 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209398103 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2209398103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.805365536
Short name T445
Test name
Test status
Simulation time 1759981375 ps
CPU time 97.18 seconds
Started Aug 28 09:55:17 PM UTC 24
Finished Aug 28 09:56:57 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805365536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.805365536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.198569991
Short name T431
Test name
Test status
Simulation time 1221064941 ps
CPU time 16.61 seconds
Started Aug 28 09:55:20 PM UTC 24
Finished Aug 28 09:55:37 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198569991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.198569991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.795441144
Short name T493
Test name
Test status
Simulation time 8128863377 ps
CPU time 686.3 seconds
Started Aug 28 09:55:20 PM UTC 24
Finished Aug 28 10:06:54 PM UTC 24
Peak memory 729388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795441144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.795441144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_error.2543929567
Short name T437
Test name
Test status
Simulation time 8727011777 ps
CPU time 50.28 seconds
Started Aug 28 09:55:24 PM UTC 24
Finished Aug 28 09:56:16 PM UTC 24
Peak memory 207372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543929567 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2543929567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_long_msg.1442925436
Short name T435
Test name
Test status
Simulation time 8308954777 ps
CPU time 48.46 seconds
Started Aug 28 09:55:11 PM UTC 24
Finished Aug 28 09:56:02 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442925436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1442925436
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_smoke.1041653954
Short name T427
Test name
Test status
Simulation time 1894345561 ps
CPU time 19.35 seconds
Started Aug 28 09:55:10 PM UTC 24
Finished Aug 28 09:55:31 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041653954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1041653954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_stress_all.1398433765
Short name T70
Test name
Test status
Simulation time 87051485232 ps
CPU time 797.69 seconds
Started Aug 28 09:55:32 PM UTC 24
Finished Aug 28 10:08:59 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398433765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1398433765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.2114714912
Short name T464
Test name
Test status
Simulation time 7954233972 ps
CPU time 177.27 seconds
Started Aug 28 09:55:30 PM UTC 24
Finished Aug 28 09:58:30 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114714912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2114714912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_alert_test.4163471717
Short name T436
Test name
Test status
Simulation time 16068955 ps
CPU time 0.83 seconds
Started Aug 28 09:56:03 PM UTC 24
Finished Aug 28 09:56:04 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163471717 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4163471717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.2391808814
Short name T432
Test name
Test status
Simulation time 51136320 ps
CPU time 4.04 seconds
Started Aug 28 09:55:39 PM UTC 24
Finished Aug 28 09:55:44 PM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391808814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2391808814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.2991484728
Short name T446
Test name
Test status
Simulation time 2182736518 ps
CPU time 67.88 seconds
Started Aug 28 09:55:48 PM UTC 24
Finished Aug 28 09:56:58 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991484728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2991484728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.2589500760
Short name T488
Test name
Test status
Simulation time 7513903481 ps
CPU time 451.41 seconds
Started Aug 28 09:55:48 PM UTC 24
Finished Aug 28 10:03:26 PM UTC 24
Peak memory 678172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589500760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2589500760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_error.2821048993
Short name T474
Test name
Test status
Simulation time 40811349874 ps
CPU time 213.84 seconds
Started Aug 28 09:55:50 PM UTC 24
Finished Aug 28 09:59:27 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821048993 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2821048993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_long_msg.3086439790
Short name T440
Test name
Test status
Simulation time 1714562622 ps
CPU time 52.64 seconds
Started Aug 28 09:55:39 PM UTC 24
Finished Aug 28 09:56:33 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086439790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3086439790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_smoke.3417625688
Short name T434
Test name
Test status
Simulation time 1665402296 ps
CPU time 17.9 seconds
Started Aug 28 09:55:37 PM UTC 24
Finished Aug 28 09:55:56 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417625688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3417625688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_stress_all.1950950486
Short name T526
Test name
Test status
Simulation time 91386765428 ps
CPU time 2213.48 seconds
Started Aug 28 09:55:57 PM UTC 24
Finished Aug 28 10:33:15 PM UTC 24
Peak memory 780588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950950486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1950950486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.1899876599
Short name T469
Test name
Test status
Simulation time 11669356436 ps
CPU time 175.8 seconds
Started Aug 28 09:55:50 PM UTC 24
Finished Aug 28 09:58:49 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899876599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1899876599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_alert_test.237989297
Short name T444
Test name
Test status
Simulation time 25913215 ps
CPU time 0.85 seconds
Started Aug 28 09:56:52 PM UTC 24
Finished Aug 28 09:56:54 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237989297 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.237989297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.767443769
Short name T455
Test name
Test status
Simulation time 5227693994 ps
CPU time 81.96 seconds
Started Aug 28 09:56:24 PM UTC 24
Finished Aug 28 09:57:48 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767443769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.767443769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.4196119729
Short name T451
Test name
Test status
Simulation time 5922757439 ps
CPU time 47.8 seconds
Started Aug 28 09:56:34 PM UTC 24
Finished Aug 28 09:57:24 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196119729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4196119729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.3460914226
Short name T479
Test name
Test status
Simulation time 5522611932 ps
CPU time 241.09 seconds
Started Aug 28 09:56:24 PM UTC 24
Finished Aug 28 10:00:29 PM UTC 24
Peak memory 456928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460914226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3460914226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_error.432837827
Short name T461
Test name
Test status
Simulation time 22270892567 ps
CPU time 103.19 seconds
Started Aug 28 09:56:41 PM UTC 24
Finished Aug 28 09:58:27 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432837827 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.432837827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_long_msg.427727981
Short name T459
Test name
Test status
Simulation time 3390732340 ps
CPU time 124.7 seconds
Started Aug 28 09:56:17 PM UTC 24
Finished Aug 28 09:58:24 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427727981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.427727981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_smoke.1923010206
Short name T439
Test name
Test status
Simulation time 1181640062 ps
CPU time 14.17 seconds
Started Aug 28 09:56:06 PM UTC 24
Finished Aug 28 09:56:21 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923010206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1923010206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_stress_all.384814023
Short name T529
Test name
Test status
Simulation time 70852709690 ps
CPU time 4484.58 seconds
Started Aug 28 09:56:52 PM UTC 24
Finished Aug 28 11:12:23 PM UTC 24
Peak memory 882936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384814023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.384814023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.1293072066
Short name T447
Test name
Test status
Simulation time 1752478910 ps
CPU time 18.14 seconds
Started Aug 28 09:56:46 PM UTC 24
Finished Aug 28 09:57:05 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293072066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1293072066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1760108124
Short name T454
Test name
Test status
Simulation time 15844040 ps
CPU time 0.91 seconds
Started Aug 28 09:57:37 PM UTC 24
Finished Aug 28 09:57:39 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760108124 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1760108124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.757666923
Short name T453
Test name
Test status
Simulation time 6430710839 ps
CPU time 38.21 seconds
Started Aug 28 09:56:58 PM UTC 24
Finished Aug 28 09:57:38 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757666923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.757666923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.666181674
Short name T452
Test name
Test status
Simulation time 4272134105 ps
CPU time 26.39 seconds
Started Aug 28 09:57:09 PM UTC 24
Finished Aug 28 09:57:36 PM UTC 24
Peak memory 215756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666181674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.666181674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.881475273
Short name T508
Test name
Test status
Simulation time 11780355372 ps
CPU time 1113.3 seconds
Started Aug 28 09:57:06 PM UTC 24
Finished Aug 28 10:15:52 PM UTC 24
Peak memory 725192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881475273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.881475273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_error.3814418717
Short name T466
Test name
Test status
Simulation time 2545562974 ps
CPU time 75.57 seconds
Started Aug 28 09:57:15 PM UTC 24
Finished Aug 28 09:58:32 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814418717 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3814418717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_long_msg.208493187
Short name T450
Test name
Test status
Simulation time 1233530401 ps
CPU time 19.88 seconds
Started Aug 28 09:56:58 PM UTC 24
Finished Aug 28 09:57:20 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208493187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.208493187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_smoke.3940956895
Short name T448
Test name
Test status
Simulation time 809316031 ps
CPU time 10.91 seconds
Started Aug 28 09:56:55 PM UTC 24
Finished Aug 28 09:57:08 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940956895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3940956895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_stress_all.3982260855
Short name T506
Test name
Test status
Simulation time 39821538564 ps
CPU time 1063.84 seconds
Started Aug 28 09:57:25 PM UTC 24
Finished Aug 28 10:15:20 PM UTC 24
Peak memory 540956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982260855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3982260855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.24996857
Short name T460
Test name
Test status
Simulation time 5871228763 ps
CPU time 64.42 seconds
Started Aug 28 09:57:21 PM UTC 24
Finished Aug 28 09:58:27 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24996857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.24996857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_alert_test.4157473838
Short name T465
Test name
Test status
Simulation time 15573401 ps
CPU time 0.82 seconds
Started Aug 28 09:58:29 PM UTC 24
Finished Aug 28 09:58:31 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157473838 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4157473838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.128325020
Short name T457
Test name
Test status
Simulation time 307352120 ps
CPU time 24.22 seconds
Started Aug 28 09:57:49 PM UTC 24
Finished Aug 28 09:58:15 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128325020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.128325020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.4168886990
Short name T458
Test name
Test status
Simulation time 1102032353 ps
CPU time 6.18 seconds
Started Aug 28 09:58:16 PM UTC 24
Finished Aug 28 09:58:23 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168886990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4168886990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.3415333341
Short name T505
Test name
Test status
Simulation time 17681932780 ps
CPU time 1020.09 seconds
Started Aug 28 09:58:00 PM UTC 24
Finished Aug 28 10:15:11 PM UTC 24
Peak memory 774444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415333341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3415333341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_error.3642407543
Short name T475
Test name
Test status
Simulation time 5026634166 ps
CPU time 66.14 seconds
Started Aug 28 09:58:24 PM UTC 24
Finished Aug 28 09:59:32 PM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642407543 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3642407543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_long_msg.1125593085
Short name T462
Test name
Test status
Simulation time 709721020 ps
CPU time 47.56 seconds
Started Aug 28 09:57:40 PM UTC 24
Finished Aug 28 09:58:29 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125593085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1125593085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_smoke.2246025131
Short name T456
Test name
Test status
Simulation time 587236464 ps
CPU time 18.02 seconds
Started Aug 28 09:57:39 PM UTC 24
Finished Aug 28 09:57:59 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246025131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2246025131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_stress_all.3163044251
Short name T503
Test name
Test status
Simulation time 182057170308 ps
CPU time 959.68 seconds
Started Aug 28 09:58:28 PM UTC 24
Finished Aug 28 10:14:41 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163044251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3163044251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.1581899977
Short name T470
Test name
Test status
Simulation time 5933232121 ps
CPU time 27.5 seconds
Started Aug 28 09:58:26 PM UTC 24
Finished Aug 28 09:58:55 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581899977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1581899977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_alert_test.183268959
Short name T471
Test name
Test status
Simulation time 19841400 ps
CPU time 0.94 seconds
Started Aug 28 09:58:56 PM UTC 24
Finished Aug 28 09:58:58 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183268959 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.183268959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.2689949944
Short name T481
Test name
Test status
Simulation time 3797234646 ps
CPU time 123.74 seconds
Started Aug 28 09:58:32 PM UTC 24
Finished Aug 28 10:00:38 PM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689949944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2689949944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.3791573956
Short name T468
Test name
Test status
Simulation time 229006944 ps
CPU time 7.63 seconds
Started Aug 28 09:58:34 PM UTC 24
Finished Aug 28 09:58:42 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791573956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3791573956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.2606297912
Short name T472
Test name
Test status
Simulation time 288117397 ps
CPU time 28.38 seconds
Started Aug 28 09:58:32 PM UTC 24
Finished Aug 28 09:59:02 PM UTC 24
Peak memory 241892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606297912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2606297912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_error.3795437243
Short name T484
Test name
Test status
Simulation time 63097850008 ps
CPU time 231.47 seconds
Started Aug 28 09:58:39 PM UTC 24
Finished Aug 28 10:02:34 PM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795437243 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3795437243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2066124915
Short name T473
Test name
Test status
Simulation time 9998067764 ps
CPU time 47.59 seconds
Started Aug 28 09:58:32 PM UTC 24
Finished Aug 28 09:59:21 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066124915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2066124915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_smoke.1330950249
Short name T467
Test name
Test status
Simulation time 281967448 ps
CPU time 5.05 seconds
Started Aug 28 09:58:32 PM UTC 24
Finished Aug 28 09:58:38 PM UTC 24
Peak memory 207000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330950249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1330950249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2038247649
Short name T524
Test name
Test status
Simulation time 271817630888 ps
CPU time 1722.95 seconds
Started Aug 28 09:58:51 PM UTC 24
Finished Aug 28 10:27:54 PM UTC 24
Peak memory 737640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038247649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2038247649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.6730984
Short name T476
Test name
Test status
Simulation time 1159626273 ps
CPU time 61.13 seconds
Started Aug 28 09:58:43 PM UTC 24
Finished Aug 28 09:59:46 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6730984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.6730984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_alert_test.1624881603
Short name T68
Test name
Test status
Simulation time 39046009 ps
CPU time 0.81 seconds
Started Aug 28 09:34:48 PM UTC 24
Finished Aug 28 09:34:50 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624881603 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1624881603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.3482499643
Short name T181
Test name
Test status
Simulation time 5204224574 ps
CPU time 73.03 seconds
Started Aug 28 09:34:39 PM UTC 24
Finished Aug 28 09:35:54 PM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482499643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3482499643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.115363485
Short name T156
Test name
Test status
Simulation time 2960112416 ps
CPU time 64.1 seconds
Started Aug 28 09:34:44 PM UTC 24
Finished Aug 28 09:35:51 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115363485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.115363485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.3595225613
Short name T288
Test name
Test status
Simulation time 2936263644 ps
CPU time 569.08 seconds
Started Aug 28 09:34:39 PM UTC 24
Finished Aug 28 09:44:15 PM UTC 24
Peak memory 712928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595225613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3595225613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_error.1529753050
Short name T143
Test name
Test status
Simulation time 50479628709 ps
CPU time 177.77 seconds
Started Aug 28 09:34:44 PM UTC 24
Finished Aug 28 09:37:45 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529753050 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1529753050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_long_msg.3034928317
Short name T66
Test name
Test status
Simulation time 109361707 ps
CPU time 6.59 seconds
Started Aug 28 09:34:38 PM UTC 24
Finished Aug 28 09:34:46 PM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034928317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3034928317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_smoke.1652145713
Short name T146
Test name
Test status
Simulation time 1027170202 ps
CPU time 13.67 seconds
Started Aug 28 09:34:38 PM UTC 24
Finished Aug 28 09:34:53 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652145713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1652145713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3926756819
Short name T91
Test name
Test status
Simulation time 66959352497 ps
CPU time 1240.86 seconds
Started Aug 28 09:34:47 PM UTC 24
Finished Aug 28 09:55:43 PM UTC 24
Peak memory 678180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926756819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3926756819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.1351886508
Short name T122
Test name
Test status
Simulation time 43869925119 ps
CPU time 120.12 seconds
Started Aug 28 09:34:45 PM UTC 24
Finished Aug 28 09:36:48 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351886508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1351886508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_alert_test.532488974
Short name T176
Test name
Test status
Simulation time 14356126 ps
CPU time 0.85 seconds
Started Aug 28 09:35:08 PM UTC 24
Finished Aug 28 09:35:10 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532488974 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.532488974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.2413320559
Short name T45
Test name
Test status
Simulation time 1191248158 ps
CPU time 39.98 seconds
Started Aug 28 09:34:51 PM UTC 24
Finished Aug 28 09:35:32 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413320559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2413320559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.3094433402
Short name T167
Test name
Test status
Simulation time 22910388495 ps
CPU time 68.89 seconds
Started Aug 28 09:34:53 PM UTC 24
Finished Aug 28 09:36:04 PM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094433402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3094433402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.3562608926
Short name T147
Test name
Test status
Simulation time 805337672 ps
CPU time 63.98 seconds
Started Aug 28 09:34:52 PM UTC 24
Finished Aug 28 09:35:58 PM UTC 24
Peak memory 417944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562608926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3562608926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_error.3538630015
Short name T203
Test name
Test status
Simulation time 10197908593 ps
CPU time 157.31 seconds
Started Aug 28 09:34:57 PM UTC 24
Finished Aug 28 09:37:37 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538630015 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3538630015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_long_msg.3957630135
Short name T128
Test name
Test status
Simulation time 71094330191 ps
CPU time 75.93 seconds
Started Aug 28 09:34:51 PM UTC 24
Finished Aug 28 09:36:09 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957630135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3957630135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_smoke.1120693851
Short name T129
Test name
Test status
Simulation time 269861933 ps
CPU time 16.76 seconds
Started Aug 28 09:34:51 PM UTC 24
Finished Aug 28 09:35:09 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120693851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1120693851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_stress_all.4255894626
Short name T480
Test name
Test status
Simulation time 46078630524 ps
CPU time 1517.66 seconds
Started Aug 28 09:35:03 PM UTC 24
Finished Aug 28 10:00:37 PM UTC 24
Peak memory 772476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255894626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4255894626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_stress_all_with_rand_reset.2212048309
Short name T22
Test name
Test status
Simulation time 14629750789 ps
CPU time 176.19 seconds
Started Aug 28 09:35:08 PM UTC 24
Finished Aug 28 09:38:07 PM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22120483
09 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2212048309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.402140088
Short name T125
Test name
Test status
Simulation time 8416713170 ps
CPU time 144.98 seconds
Started Aug 28 09:35:01 PM UTC 24
Finished Aug 28 09:37:29 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402140088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.402140088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_alert_test.3688216761
Short name T179
Test name
Test status
Simulation time 75373136 ps
CPU time 0.87 seconds
Started Aug 28 09:35:47 PM UTC 24
Finished Aug 28 09:35:49 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688216761 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3688216761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.3488313882
Short name T189
Test name
Test status
Simulation time 18511505020 ps
CPU time 79.8 seconds
Started Aug 28 09:35:11 PM UTC 24
Finished Aug 28 09:36:33 PM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488313882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3488313882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.1173957949
Short name T168
Test name
Test status
Simulation time 19233296805 ps
CPU time 42.86 seconds
Started Aug 28 09:35:18 PM UTC 24
Finished Aug 28 09:36:03 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173957949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1173957949
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.819115159
Short name T245
Test name
Test status
Simulation time 14042195516 ps
CPU time 363.2 seconds
Started Aug 28 09:35:16 PM UTC 24
Finished Aug 28 09:41:24 PM UTC 24
Peak memory 717020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819115159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.819115159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_error.2183778703
Short name T36
Test name
Test status
Simulation time 30383955037 ps
CPU time 158.56 seconds
Started Aug 28 09:35:34 PM UTC 24
Finished Aug 28 09:38:16 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183778703 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2183778703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_long_msg.1688598448
Short name T213
Test name
Test status
Simulation time 22758767538 ps
CPU time 217.11 seconds
Started Aug 28 09:35:10 PM UTC 24
Finished Aug 28 09:38:51 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688598448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1688598448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_smoke.2587882838
Short name T153
Test name
Test status
Simulation time 193304258 ps
CPU time 6.04 seconds
Started Aug 28 09:35:10 PM UTC 24
Finished Aug 28 09:35:17 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587882838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2587882838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_stress_all.1774888289
Short name T126
Test name
Test status
Simulation time 22129373007 ps
CPU time 118.17 seconds
Started Aug 28 09:35:38 PM UTC 24
Finished Aug 28 09:37:39 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774888289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1774888289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1065105490
Short name T123
Test name
Test status
Simulation time 5842218949 ps
CPU time 73.27 seconds
Started Aug 28 09:35:36 PM UTC 24
Finished Aug 28 09:36:51 PM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065105490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1065105490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1050876361
Short name T183
Test name
Test status
Simulation time 34254495 ps
CPU time 0.84 seconds
Started Aug 28 09:36:05 PM UTC 24
Finished Aug 28 09:36:07 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050876361 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1050876361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.1496919150
Short name T196
Test name
Test status
Simulation time 1115827480 ps
CPU time 63.19 seconds
Started Aug 28 09:35:54 PM UTC 24
Finished Aug 28 09:36:59 PM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496919150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1496919150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.200386223
Short name T160
Test name
Test status
Simulation time 4239974636 ps
CPU time 72.5 seconds
Started Aug 28 09:35:56 PM UTC 24
Finished Aug 28 09:37:11 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200386223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.200386223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.3087660342
Short name T244
Test name
Test status
Simulation time 1359717460 ps
CPU time 315.68 seconds
Started Aug 28 09:35:56 PM UTC 24
Finished Aug 28 09:41:16 PM UTC 24
Peak memory 702752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087660342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3087660342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_error.2919203059
Short name T190
Test name
Test status
Simulation time 1949581670 ps
CPU time 40.7 seconds
Started Aug 28 09:35:58 PM UTC 24
Finished Aug 28 09:36:41 PM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919203059 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2919203059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_long_msg.2002242783
Short name T185
Test name
Test status
Simulation time 933158519 ps
CPU time 18.81 seconds
Started Aug 28 09:35:52 PM UTC 24
Finished Aug 28 09:36:12 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002242783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2002242783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_smoke.4144596513
Short name T180
Test name
Test status
Simulation time 62574678 ps
CPU time 1.72 seconds
Started Aug 28 09:35:50 PM UTC 24
Finished Aug 28 09:35:53 PM UTC 24
Peak memory 206344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144596513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4144596513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_stress_all.4075847827
Short name T186
Test name
Test status
Simulation time 7928854386 ps
CPU time 25.37 seconds
Started Aug 28 09:36:02 PM UTC 24
Finished Aug 28 09:36:28 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075847827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.4075847827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.2423339769
Short name T124
Test name
Test status
Simulation time 13946207693 ps
CPU time 63.18 seconds
Started Aug 28 09:36:01 PM UTC 24
Finished Aug 28 09:37:06 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423339769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2423339769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2964349364
Short name T188
Test name
Test status
Simulation time 19358725 ps
CPU time 0.87 seconds
Started Aug 28 09:36:29 PM UTC 24
Finished Aug 28 09:36:31 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964349364 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2964349364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.3997268504
Short name T194
Test name
Test status
Simulation time 2870833937 ps
CPU time 37.91 seconds
Started Aug 28 09:36:10 PM UTC 24
Finished Aug 28 09:36:49 PM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997268504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3997268504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.2343968233
Short name T198
Test name
Test status
Simulation time 46873099404 ps
CPU time 51.79 seconds
Started Aug 28 09:36:13 PM UTC 24
Finished Aug 28 09:37:06 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343968233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2343968233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.613900841
Short name T399
Test name
Test status
Simulation time 4837349147 ps
CPU time 990.2 seconds
Started Aug 28 09:36:12 PM UTC 24
Finished Aug 28 09:52:52 PM UTC 24
Peak memory 745756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613900841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.613900841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_error.1518171654
Short name T232
Test name
Test status
Simulation time 116462771032 ps
CPU time 224.51 seconds
Started Aug 28 09:36:13 PM UTC 24
Finished Aug 28 09:40:01 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518171654 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1518171654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_long_msg.2872377341
Short name T184
Test name
Test status
Simulation time 245001588 ps
CPU time 3.86 seconds
Started Aug 28 09:36:07 PM UTC 24
Finished Aug 28 09:36:12 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872377341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2872377341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_smoke.3373520993
Short name T149
Test name
Test status
Simulation time 2152762974 ps
CPU time 9.06 seconds
Started Aug 28 09:36:07 PM UTC 24
Finished Aug 28 09:36:18 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373520993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3373520993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_stress_all.2279488628
Short name T500
Test name
Test status
Simulation time 310763831415 ps
CPU time 2570.49 seconds
Started Aug 28 09:36:19 PM UTC 24
Finished Aug 28 10:19:38 PM UTC 24
Peak memory 784576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_28/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279488628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2279488628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1109961286
Short name T169
Test name
Test status
Simulation time 1126815216 ps
CPU time 59.2 seconds
Started Aug 28 09:36:16 PM UTC 24
Finished Aug 28 09:37:17 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109961286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1109961286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/hmac-sim-vcs/9.hmac_wipe_secret/latest
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