Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17332907	1			T3	657		T4	115		T5	2362
all_values[1]	17332907	1			T3	657		T4	115		T5	2362
all_values[2]	17332907	1			T3	657		T4	115		T5	2362

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

278790

1

T4

45

T6

277

T8

18

auto[1]

51719931

1

T3

1971

T4

300

T5

7086

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44212145

1

T3

1836

T4

239

T5

6290

auto[1]

7786576

1

T3

135

T4

106

T5

796

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101362	1			T13	833		T18	119		T122	23
all_values[0]	auto[0]	auto[1]	325	1			T18	2		T121	2		T21	3
all_values[0]	auto[1]	auto[0]	17212800	1			T3	644		T4	113		T5	2328
all_values[0]	auto[1]	auto[1]	18420	1			T3	13		T4	2		T5	34
all_values[1]	auto[0]	auto[0]	73361	1			T6	277		T17	1161		T10	97
all_values[1]	auto[0]	auto[1]	183	1			T59	3		T60	1		T61	3
all_values[1]	auto[1]	auto[0]	17259102	1			T3	657		T4	115		T5	2362
all_values[1]	auto[1]	auto[1]	261	1			T9	1		T44	4		T123	11
all_values[2]	auto[0]	auto[0]	39061	1			T4	5		T8	18		T16	2
all_values[2]	auto[0]	auto[1]	64498	1			T4	40		T82	415		T13	832
all_values[2]	auto[1]	auto[0]	9526459	1			T3	535		T4	6		T5	1600
all_values[2]	auto[1]	auto[1]	7702889	1			T3	122		T4	64		T5	762