Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116666

1

T3

14

T4

34

T5

38

auto[1]

114390

1

T3

24

T4

62

T5

26

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	87561	1			T3	1		T6	8		T7	1
len_1026_2046	6445	1			T8	1		T9	24		T14	42
len_514_1022	4258	1			T5	4		T9	11		T14	17
len_2_510	3522	1			T3	2		T5	1		T9	62
len_2056	163	1			T5	3		T8	6		T22	5
len_2048	323	1			T5	6		T6	1		T14	1
len_2040	141	1			T3	1		T10	1		T138	2
len_1032	121	1			T5	2		T8	1		T10	1
len_1024	1783	1			T3	6		T5	3		T7	1
len_1016	151	1			T5	1		T10	4		T139	1
len_520	196	1			T5	1		T8	2		T22	5
len_512	360	1			T3	2		T5	1		T9	1
len_504	170	1			T3	4		T5	2		T22	4
len_8	1102	1			T121	1		T140	1		T141	10
len_0	9232	1			T3	3		T4	48		T5	8

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

116

1

T3

1

T6

2

T9

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	44897	1			T6	5		T7	1		T9	605
auto[0]	len_1026_2046	3131	1			T8	1		T9	21		T14	22
auto[0]	len_514_1022	3095	1			T5	2		T9	10		T14	10
auto[0]	len_2_510	1843	1			T3	1		T5	1		T9	9
auto[0]	len_2056	71	1			T5	3		T8	1		T22	2
auto[0]	len_2048	191	1			T5	4		T6	1		T14	1
auto[0]	len_2040	72	1			T138	2		T23	2		T53	2
auto[0]	len_1032	62	1			T5	2		T8	1		T10	1
auto[0]	len_1024	245	1			T3	2		T5	2		T7	1
auto[0]	len_1016	99	1			T10	3		T139	1		T138	3
auto[0]	len_520	110	1			T5	1		T8	2		T22	2
auto[0]	len_512	206	1			T5	1		T9	1		T10	2
auto[0]	len_504	91	1			T3	2		T22	2		T23	2
auto[0]	len_8	87	1			T142	1		T143	1		T144	1
auto[0]	len_0	4133	1			T3	2		T4	17		T5	3
auto[1]	len_2050_plus	42664	1			T3	1		T6	3		T9	104
auto[1]	len_1026_2046	3314	1			T9	3		T14	20		T12	2
auto[1]	len_514_1022	1163	1			T5	2		T9	1		T14	7
auto[1]	len_2_510	1679	1			T3	1		T9	53		T14	102
auto[1]	len_2056	92	1			T8	5		T22	3		T138	3
auto[1]	len_2048	132	1			T5	2		T18	1		T22	3
auto[1]	len_2040	69	1			T3	1		T10	1		T23	1
auto[1]	len_1032	59	1			T138	2		T23	1		T145	5
auto[1]	len_1024	1538	1			T3	4		T5	1		T19	64
auto[1]	len_1016	52	1			T5	1		T10	1		T23	1
auto[1]	len_520	86	1			T22	3		T138	1		T53	4
auto[1]	len_512	154	1			T3	2		T14	1		T12	1
auto[1]	len_504	79	1			T3	2		T5	2		T22	2
auto[1]	len_8	1015	1			T121	1		T140	1		T141	10
auto[1]	len_0	5099	1			T3	1		T4	31		T5	5

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

65

1

T6

2

T9

2

T14

1

auto[1]

len_upper

51

1

T3

1

T20

1

T146

2