Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4385163

1

T3

115

T4

124

T5

564

auto[1]

2610578

1

T3

168

T4

65

T5

532

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2626355

1

T3

175

T5

530

T6

2

auto[1]

4369386

1

T3

108

T4

189

T5

566

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3244843

1

T3

67

T4

65

T5

525

auto[1]

3750898

1

T3

216

T4

124

T5

571

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4380485

1

T3

100

T4

65

T5

429

auto[1]

2615256

1

T3

183

T4

124

T5

667

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6348026	1			T3	272		T4	189		T5	1070
fifo_depth[1]	113127	1			T3	7		T5	14		T7	13
fifo_depth[2]	83459	1			T3	4		T5	10		T7	6
fifo_depth[3]	64971	1			T5	1		T7	1		T9	133
fifo_depth[4]	59037	1			T5	1		T6	1		T9	167
fifo_depth[5]	46751	1			T9	139		T14	7		T12	9
fifo_depth[6]	37802	1			T9	129		T14	5		T11	1
fifo_depth[7]	24999	1			T9	152		T14	2		T12	18

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647715

1

T3

11

T5

26

T6

1

auto[1]

6348026

1

T3

272

T4

189

T5

1070

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6986524

1

T3

283

T4

189

T5

1096

auto[1]

9217

1

T9

67

T12

85

T44

202

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

25561

1

T5

2

T16

8

T13

298

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30513

1

T9

463

T82

7

T12

965

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

33414

1

T9

2276

T10

3

T12

1492

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29754

1

T9

108

T82

5

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

136104

1

T5

1

T6

1

T7

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30043

1

T5

1

T8

1

T18

73

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29236

1

T8

1

T9

6

T17

37

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29908

1

T5

3

T9

418

T14

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38164

1

T5

1

T82

3

T12

765

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

35441

1

T3

1

T5

8

T16

18

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

46467

1

T3

4

T5

5

T14

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34334

1

T3

4

T5

2

T16

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51702

1

T9

1745

T19

264

T14

41

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

33264

1

T5

1

T8

4

T17

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26129

1

T5

2

T8

1

T17

76

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37681

1

T3

2

T16

14

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

168830

1

T3

20

T5

105

T7

408

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

177541

1

T5

56

T9

401

T14

175

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

160462

1

T3

1

T5

10

T8

23

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

165166

1

T8

14

T9

127

T16

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1723149

1

T3

22

T5

53

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

144255

1

T3

13

T5

80

T8

58

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

164998

1

T4

65

T5

34

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

195909

1

T3

11

T5

180

T7

317

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

409436

1

T3

9

T5

22

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

425323

1

T3

40

T5

141

T9

89

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

458543

1

T3

44

T5

120

T9

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

387406

1

T3

52

T5

58

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

528257

1

T5

2

T6

1

T9

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

427580

1

T3

10

T4

124

T5

91

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

380033

1

T5

72

T8

6

T9

41

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

431138

1

T3

50

T5

46

T7

495

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

193942

1

T3

20

T5

107

T7

408

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

207694

1

T5

56

T9

841

T14

175

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

193000

1

T3

1

T5

10

T8

23

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

194237

1

T8

14

T9

235

T16

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1858479

1

T3

22

T5

54

T6

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

172986

1

T3

13

T5

81

T8

59

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

193775

1

T4

65

T5

34

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

225403

1

T3

11

T5

183

T7

317

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

446102

1

T3

9

T5

23

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

460455

1

T3

41

T5

149

T9

89

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

504893

1

T3

48

T5

125

T9

42

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

420940

1

T3

56

T5

60

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

579760

1

T5

2

T6

1

T9

1735

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

460631

1

T3

10

T4

124

T5

92

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

405787

1

T5

74

T8

7

T9

41

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

468440

1

T3

52

T5

46

T7

495

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

449

1

T60

5

T148

42

T149

55

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

360

1

T9

23

T12

3

T150

54

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

876

1

T9

24

T12

53

T123

79

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

683

1

T123

33

T148

91

T150

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

774

1

T44

115

T123

136

T60

28

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1312

1

T44

74

T148

3

T151

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

459

1

T123

1

T148

8

T149

61

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

414

1

T9

8

T123

5

T148

49

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1498

1

T12

27

T152

1317

T60

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

309

1

T123

82

T148

140

T153

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

117

1

T60

1

T149

1

T154

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

800

1

T12

2

T44

9

T123

47

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

199

1

T9

12

T154

14

T153

18

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

213

1

T44

4

T148

12

T150

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

375

1

T155

1

T156

1

T157

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

379

1

T150

4

T158

46

T159

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

168830

1

T3

20

T5

105

T7

408

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

177541

1

T5

56

T9

401

T14

175

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

160462

1

T3

1

T5

10

T8

23

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

165166

1

T8

14

T9

127

T16

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1723149

1

T3

22

T5

53

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

144255

1

T3

13

T5

80

T8

58

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

164998

1

T4

65

T5

34

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

195909

1

T3

11

T5

180

T7

317

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

409436

1

T3

9

T5

22

T6

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

425323

1

T3

40

T5

141

T9

89

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

458543

1

T3

44

T5

120

T9

42

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

387406

1

T3

52

T5

58

T6

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

528257

1

T5

2

T6

1

T9

2

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

427580

1

T3

10

T4

124

T5

91

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

380033

1

T5

72

T8

6

T9

41

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

431138

1

T3

50

T5

46

T7

495

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3355

1

T16

7

T13

92

T22

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3655

1

T9

4

T82

6

T12

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3292

1

T9

119

T10

2

T12

2

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3360

1

T9

3

T82

3

T18

4

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

42596

1

T5

1

T7

13

T9

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

2597

1

T8

1

T18

4

T15

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3262

1

T17

20

T14

1

T16

11

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4138

1

T5

2

T9

2

T14

12

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

4827

1

T82

3

T12

2

T31

5

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5151

1

T3

1

T5

5

T16

13

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7497

1

T3

1

T5

3

T14

10

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5773

1

T3

3

T5

2

T16

3

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7898

1

T9

10

T19

164

T14

15

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5185

1

T8

3

T17

3

T14

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

4913

1

T5

1

T17

52

T39

6

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5628

1

T3

2

T16

11

T10

1

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2359

1

T5

2

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1

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8

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34

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6

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16

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11

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34

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3

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3

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5

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28

fifo_depth[4]

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111

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4

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14

fifo_depth[4]

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22

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4

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5

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4

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13

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1

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5

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3

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7

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13

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1

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9

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3

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1

fifo_depth[4]

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1

T12

5

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24

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5

fifo_depth[4]

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1

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4

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3

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1

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1

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8

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1

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2

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6

fifo_depth[4]

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1

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1

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31

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2

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1

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23

T41

1

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30

fifo_depth[5]

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1

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1

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1

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118

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5

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7

fifo_depth[5]

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1

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3

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1

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fifo_depth[5]

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1

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1

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1

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14

fifo_depth[5]

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5

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1

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1

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12

fifo_depth[5]

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1

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1

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12

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4

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16

fifo_depth[5]

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1

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6

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1

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1

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5

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119

fifo_depth[5]

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1

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1

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18

fifo_depth[5]

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1

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1

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10

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103

fifo_depth[5]

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1

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22

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2

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3

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1

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12

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1

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1

fifo_depth[6]

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1

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2

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14

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1

fifo_depth[6]

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1

T9

111

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4

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5

fifo_depth[6]

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1

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10

T123

7

fifo_depth[6]

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1

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3

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1

fifo_depth[6]

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1

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13

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3

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15

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1

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1

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1

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1

fifo_depth[6]

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4

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1

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22

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1

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1

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8

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7

fifo_depth[6]

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1

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2

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3

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1

fifo_depth[6]

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1

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1

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23

T60

9

fifo_depth[6]

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1

T12

3

T13

7

T41

5

fifo_depth[6]

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1

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11

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1

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1

fifo_depth[6]

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1

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2

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15

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12

fifo_depth[6]

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1

T138

6

T121

84

T165

2

fifo_depth[6]

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1

T122

16

T138

1

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1

fifo_depth[7]

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1

T13

10

T41

1

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7

fifo_depth[7]

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1

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3

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13

T138

2

fifo_depth[7]

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1

T9

131

T12

3

T18

2

fifo_depth[7]

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1

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3

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1

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9

fifo_depth[7]

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1

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1

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6

T44

3

fifo_depth[7]

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3

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1

T50

8

fifo_depth[7]

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1

T35

1

T139

1

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1

fifo_depth[7]

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3

T50

15

T123

81

fifo_depth[7]

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1

T35

1

T44

1

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9

fifo_depth[7]

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1

T41

3

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1

T123

2

fifo_depth[7]

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1

T163

2

T123

18

T60

1

fifo_depth[7]

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auto[1]

1632

1

T12

2

T13

2

T41

1

fifo_depth[7]

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2251

1

T9

12

T14

1

T51

25

fifo_depth[7]

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auto[0]

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1480

1

T44

21

T162

9

T148

8

fifo_depth[7]

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auto[0]

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1

T138

4

T121

46

T20

1

fifo_depth[7]

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auto[1]

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1969

1

T122

6

T138

2

T50

1