Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17332907	1			T3	657		T4	115		T5	2362
all_pins[1]	17332907	1			T3	657		T4	115		T5	2362
all_pins[2]	17332907	1			T3	657		T4	115		T5	2362

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44276381	1			T3	1833		T4	279		T5	6290
values[0x1]	7722340	1			T3	138		T4	66		T5	796
transitions[0x0=>0x1]	7722219	1			T3	138		T4	66		T5	796
transitions[0x1=>0x0]	7722231	1			T3	138		T4	66		T5	796

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17313739	1			T3	641		T4	113		T5	2328
all_pins[0]	values[0x1]	19168	1			T3	16		T4	2		T5	34
all_pins[0]	transitions[0x0=>0x1]	19118	1			T3	16		T4	2		T5	34
all_pins[0]	transitions[0x1=>0x0]	7702851	1			T3	122		T4	64		T5	762
all_pins[1]	values[0x0]	17332624	1			T3	657		T4	115		T5	2362
all_pins[1]	values[0x1]	283	1			T9	1		T44	4		T123	13
all_pins[1]	transitions[0x0=>0x1]	248	1			T9	1		T44	4		T123	13
all_pins[1]	transitions[0x1=>0x0]	19133	1			T3	16		T4	2		T5	34
all_pins[2]	values[0x0]	9630018	1			T3	535		T4	51		T5	1600
all_pins[2]	values[0x1]	7702889	1			T3	122		T4	64		T5	762
all_pins[2]	transitions[0x0=>0x1]	7702853	1			T3	122		T4	64		T5	762
all_pins[2]	transitions[0x1=>0x0]	247	1			T9	1		T44	4		T123	13