Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 830 1 T59 17 T60 11 T61 10
all_values[1] 830 1 T59 17 T60 11 T61 10
all_values[2] 830 1 T59 17 T60 11 T61 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1367 1 T59 27 T60 22 T61 14
auto[1] 1123 1 T59 24 T60 11 T61 16


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 937 1 T59 15 T60 11 T61 8
auto[1] 1553 1 T59 36 T60 22 T61 22


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1435 1 T59 21 T60 16 T61 13
auto[1] 1055 1 T59 30 T60 17 T61 17


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 180 1 T59 4 T60 4 T61 3
all_values[0] auto[0] auto[0] auto[1] 82 1 T61 1 T24 1 T25 1
all_values[0] auto[0] auto[1] auto[0] 139 1 T59 1 T60 3 T25 2
all_values[0] auto[0] auto[1] auto[1] 75 1 T25 1 T75 3 T124 1
all_values[0] auto[1] auto[0] auto[1] 203 1 T59 7 T60 3 T61 2
all_values[0] auto[1] auto[1] auto[1] 151 1 T59 5 T60 1 T61 4
all_values[1] auto[0] auto[0] auto[0] 151 1 T59 2 T60 2 T25 2
all_values[1] auto[0] auto[0] auto[1] 102 1 T59 2 T61 1 T25 2
all_values[1] auto[0] auto[1] auto[0] 130 1 T59 3 T60 1 T61 1
all_values[1] auto[0] auto[1] auto[1] 89 1 T59 3 T60 2 T61 2
all_values[1] auto[1] auto[0] auto[1] 193 1 T59 4 T60 3 T61 2
all_values[1] auto[1] auto[1] auto[1] 165 1 T59 3 T60 3 T61 4
all_values[2] auto[0] auto[0] auto[0] 183 1 T59 4 T60 1 T61 2
all_values[2] auto[0] auto[0] auto[1] 77 1 T60 2 T61 1 T24 1
all_values[2] auto[0] auto[1] auto[0] 154 1 T59 1 T61 2 T25 2
all_values[2] auto[0] auto[1] auto[1] 73 1 T59 1 T60 1 T24 1
all_values[2] auto[1] auto[0] auto[1] 196 1 T59 4 T60 7 T61 2
all_values[2] auto[1] auto[1] auto[1] 147 1 T59 7 T61 3 T24 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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