Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3919	1			T3	4		T4	1		T5	11
sha2_none	3840	1			T3	1		T4	1		T5	10
sha2_512	7093	1			T3	5		T5	11		T6	6
sha2_384	6977	1			T3	2		T4	1		T5	7
sha2_256	5883	1			T3	5		T5	12		T6	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17804

1

T3

8

T4

1

T5

26

auto[1]

10272

1

T3

10

T4

2

T5

25

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10080

1

T3

10

T5

22

T6

2

auto[1]

17996

1

T3

8

T4

3

T5

29

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14327

1

T3

11

T4

1

T5

22

disabled

13749

1

T3

7

T4

2

T5

29

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4240	1			T3	2		T4	1		T5	8
key_none	7523	1			T3	3		T5	5		T6	1
key_1024	4005	1			T3	1		T4	1		T5	9
key_512	3534	1			T3	4		T4	1		T5	8
key_384	3128	1			T3	7		T5	2		T6	2
key_256	2817	1			T3	1		T5	11		T8	1
key_128	2752	1			T5	8		T6	1		T7	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17809

1

T3

8

T4

2

T5

25

auto[1]

10267

1

T3

10

T4

1

T5

26

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27865

1

T3

18

T4

3

T5

51

disabled

211

1

T13

1

T47

2

T48

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1405

1

T3

1

T5

1

T6

1

enabled

auto[0]

auto[0]

auto[1]

1483

1

T3

2

T5

3

T9

3

enabled

auto[0]

auto[1]

auto[0]

1410

1

T3

3

T5

5

T9

1

enabled

auto[0]

auto[1]

auto[1]

1381

1

T3

2

T5

2

T6

1

enabled

auto[1]

auto[0]

auto[0]

4171

1

T5

2

T6

1

T9

3

enabled

auto[1]

auto[0]

auto[1]

1506

1

T3

1

T4

1

T5

3

enabled

auto[1]

auto[1]

auto[0]

1570

1

T5

3

T8

1

T9

2

enabled

auto[1]

auto[1]

auto[1]

1401

1

T3

2

T5

3

T7

1

disabled

auto[0]

auto[0]

auto[0]

1077

1

T3

1

T5

6

T7

1

disabled

auto[0]

auto[0]

auto[1]

1103

1

T5

3

T9

3

T14

3

disabled

auto[0]

auto[1]

auto[0]

1098

1

T3

1

T5

2

T8

1

disabled

auto[0]

auto[1]

auto[1]

1123

1

T8

1

T9

3

T16

1

disabled

auto[1]

auto[0]

auto[0]

5971

1

T3

2

T5

4

T6

2

disabled

auto[1]

auto[0]

auto[1]

1088

1

T3

1

T5

4

T8

2

disabled

auto[1]

auto[1]

auto[0]

1107

1

T4

2

T5

2

T6

2

disabled

auto[1]

auto[1]

auto[1]

1182

1

T3

2

T5

8

T7

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14248

1

T3

11

T4

1

T5

22

enabled

disabled

79

1

T13

1

T47

2

T136

1

disabled

disabled

132

1

T48

1

T136

1

T137

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13617

1

T3

7

T4

2

T5

29

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1068	1			T3	2		T5	4		T9	1
key_invalid	sha2_none	801	1			T4	1		T5	1		T14	2
key_invalid	sha2_512	761	1			T5	1		T6	2		T9	2
key_invalid	sha2_384	731	1			T8	2		T9	2		T14	1
key_invalid	sha2_256	777	1			T5	2		T6	1		T17	1
key_none	sha2_invalid	444	1			T6	1		T7	2		T8	1
key_none	sha2_none	514	1			T3	1		T5	2		T7	1
key_none	sha2_512	2483	1			T3	1		T5	2		T9	4
key_none	sha2_384	2557	1			T3	1		T5	1		T9	1
key_none	sha2_256	1488	1			T9	3		T14	2		T12	1
key_1024	sha2_invalid	445	1			T4	1		T5	2		T8	2
key_1024	sha2_none	482	1			T5	2		T8	1		T9	1
key_1024	sha2_512	1654	1			T5	3		T6	1		T8	1
key_1024	sha2_384	868	1			T5	1		T8	2		T14	1
key_512	sha2_invalid	516	1			T10	1		T12	1		T13	1
key_512	sha2_none	465	1			T5	2		T9	2		T14	1
key_512	sha2_512	524	1			T3	2		T5	2		T8	1
key_512	sha2_384	1168	1			T3	1		T4	1		T5	1
key_512	sha2_256	811	1			T3	1		T5	3		T19	45
key_384	sha2_invalid	461	1			T3	2		T14	1		T16	1
key_384	sha2_none	520	1			T5	1		T9	1		T16	1
key_384	sha2_512	544	1			T3	2		T5	1		T6	2
key_384	sha2_384	537	1			T9	4		T10	2		T12	1
key_384	sha2_256	1022	1			T3	3		T19	90		T10	1
key_256	sha2_invalid	468	1			T5	4		T9	2		T18	1
key_256	sha2_none	479	1			T14	1		T10	1		T18	2
key_256	sha2_512	557	1			T5	2		T9	2		T16	3
key_256	sha2_384	566	1			T5	2		T16	1		T82	1
key_256	sha2_256	701	1			T3	1		T5	3		T8	1
key_128	sha2_invalid	494	1			T5	1		T9	1		T14	2
key_128	sha2_none	567	1			T5	2		T17	1		T10	1
key_128	sha2_512	561	1			T6	1		T9	1		T16	4
key_128	sha2_384	539	1			T5	2		T14	1		T16	1
key_128	sha2_256	555	1			T5	3		T7	2		T14	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

509

1

T5

1

T14

1

T22

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1068	1			T3	2		T5	4		T9	1
key_invalid	sha2_none	801	1			T4	1		T5	1		T14	2
key_invalid	sha2_512	761	1			T5	1		T6	2		T9	2
key_invalid	sha2_384	731	1			T8	2		T9	2		T14	1
key_invalid	sha2_256	777	1			T5	2		T6	1		T17	1
key_none	sha2_invalid	444	1			T6	1		T7	2		T8	1
key_none	sha2_none	514	1			T3	1		T5	2		T7	1
key_none	sha2_512	2483	1			T3	1		T5	2		T9	4
key_none	sha2_384	2557	1			T3	1		T5	1		T9	1
key_none	sha2_256	1488	1			T9	3		T14	2		T12	1
key_1024	sha2_invalid	445	1			T4	1		T5	2		T8	2
key_1024	sha2_none	482	1			T5	2		T8	1		T9	1
key_1024	sha2_512	1654	1			T5	3		T6	1		T8	1
key_1024	sha2_384	868	1			T5	1		T8	2		T14	1
key_1024	sha2_256	509	1			T5	1		T14	1		T22	1
key_512	sha2_invalid	516	1			T10	1		T12	1		T13	1
key_512	sha2_none	465	1			T5	2		T9	2		T14	1
key_512	sha2_512	524	1			T3	2		T5	2		T8	1
key_512	sha2_384	1168	1			T3	1		T4	1		T5	1
key_512	sha2_256	811	1			T3	1		T5	3		T19	45
key_384	sha2_invalid	461	1			T3	2		T14	1		T16	1
key_384	sha2_none	520	1			T5	1		T9	1		T16	1
key_384	sha2_512	544	1			T3	2		T5	1		T6	2
key_384	sha2_384	537	1			T9	4		T10	2		T12	1
key_384	sha2_256	1022	1			T3	3		T19	90		T10	1
key_256	sha2_invalid	468	1			T5	4		T9	2		T18	1
key_256	sha2_none	479	1			T14	1		T10	1		T18	2
key_256	sha2_512	557	1			T5	2		T9	2		T16	3
key_256	sha2_384	566	1			T5	2		T16	1		T82	1
key_256	sha2_256	701	1			T3	1		T5	3		T8	1
key_128	sha2_invalid	494	1			T5	1		T9	1		T14	2
key_128	sha2_none	567	1			T5	2		T17	1		T10	1
key_128	sha2_512	561	1			T6	1		T9	1		T16	4
key_128	sha2_384	539	1			T5	2		T14	1		T16	1
key_128	sha2_256	555	1			T5	3		T7	2		T14	1