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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85


Total test records in report: 655
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T68 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.4161030825 Sep 01 07:02:53 AM UTC 24 Sep 01 07:02:59 AM UTC 24 111874055 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.62363962 Sep 01 07:02:53 AM UTC 24 Sep 01 07:02:59 AM UTC 24 132924117 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2359297023 Sep 01 07:02:53 AM UTC 24 Sep 01 07:03:00 AM UTC 24 1138713127 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3521293808 Sep 01 07:02:53 AM UTC 24 Sep 01 07:03:00 AM UTC 24 400770008 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.2311739166 Sep 01 07:02:54 AM UTC 24 Sep 01 07:03:00 AM UTC 24 406743748 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.4113338190 Sep 01 07:02:57 AM UTC 24 Sep 01 07:03:00 AM UTC 24 77980322 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.3660335915 Sep 01 07:02:55 AM UTC 24 Sep 01 07:03:01 AM UTC 24 116244062 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2958691832 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:02 AM UTC 24 23833353 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1919193136 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:02 AM UTC 24 105222877 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3025448167 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:02 AM UTC 24 33555420 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.22695201 Sep 01 07:02:59 AM UTC 24 Sep 01 07:03:02 AM UTC 24 15550368 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.696361357 Sep 01 07:02:55 AM UTC 24 Sep 01 07:03:03 AM UTC 24 321492038 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.888144814 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:03 AM UTC 24 107380109 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.305845871 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:03 AM UTC 24 55719376 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.4168911537 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:04 AM UTC 24 204468894 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3058775796 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:04 AM UTC 24 297975010 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.997191072 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:04 AM UTC 24 94329995 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2820089822 Sep 01 07:02:53 AM UTC 24 Sep 01 07:03:05 AM UTC 24 301932991 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.2221121728 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:06 AM UTC 24 15800623 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.1325191309 Sep 01 07:03:02 AM UTC 24 Sep 01 07:03:07 AM UTC 24 31802604 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2488123124 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:07 AM UTC 24 22990036 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.949086470 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:07 AM UTC 24 412420053 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.3918926773 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:07 AM UTC 24 43074269 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.470251958 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:07 AM UTC 24 123045888 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1871128877 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:07 AM UTC 24 41399997 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2275925452 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:07 AM UTC 24 212401438 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2915759578 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:08 AM UTC 24 24423707 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.3016682446 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:08 AM UTC 24 138354772 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3193420178 Sep 01 07:02:58 AM UTC 24 Sep 01 07:03:08 AM UTC 24 748802248 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.549572918 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:08 AM UTC 24 105177375 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3962852823 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:08 AM UTC 24 66316252 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2632494122 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:08 AM UTC 24 45740446 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3756155013 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:09 AM UTC 24 413349812 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4163670827 Sep 01 07:03:02 AM UTC 24 Sep 01 07:03:10 AM UTC 24 111443438 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3845075060 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:10 AM UTC 24 290385669 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2356698828 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:11 AM UTC 24 8779165916 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2694872541 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:11 AM UTC 24 366994558 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2765449929 Sep 01 07:03:03 AM UTC 24 Sep 01 07:03:12 AM UTC 24 56539576 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.4172284947 Sep 01 07:03:09 AM UTC 24 Sep 01 07:03:12 AM UTC 24 15458604 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.41719961 Sep 01 07:03:09 AM UTC 24 Sep 01 07:03:12 AM UTC 24 39612787 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1553158419 Sep 01 07:03:09 AM UTC 24 Sep 01 07:03:12 AM UTC 24 81164143 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.347132557 Sep 01 07:02:53 AM UTC 24 Sep 01 07:03:12 AM UTC 24 3744691472 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2026059460 Sep 01 07:03:09 AM UTC 24 Sep 01 07:03:13 AM UTC 24 124233311 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1633138196 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:14 AM UTC 24 47708764 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.1815028253 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:14 AM UTC 24 97719089 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.855216765 Sep 01 07:03:09 AM UTC 24 Sep 01 07:03:14 AM UTC 24 187320867 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3877461033 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:14 AM UTC 24 90207787 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2890043560 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:14 AM UTC 24 132297880 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2402116445 Sep 01 07:03:09 AM UTC 24 Sep 01 07:03:15 AM UTC 24 179809129 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2092784454 Sep 01 07:03:11 AM UTC 24 Sep 01 07:03:16 AM UTC 24 42906934 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.722864248 Sep 01 07:03:11 AM UTC 24 Sep 01 07:03:16 AM UTC 24 30180473 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3372793921 Sep 01 07:03:15 AM UTC 24 Sep 01 07:03:17 AM UTC 24 19500386 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3324341662 Sep 01 07:03:05 AM UTC 24 Sep 01 07:03:17 AM UTC 24 19436869 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3315285536 Sep 01 07:03:13 AM UTC 24 Sep 01 07:03:17 AM UTC 24 16902662 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1718719223 Sep 01 07:03:15 AM UTC 24 Sep 01 07:03:18 AM UTC 24 45660063 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.467139120 Sep 01 07:03:03 AM UTC 24 Sep 01 07:03:18 AM UTC 24 29954260 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3468427091 Sep 01 07:03:00 AM UTC 24 Sep 01 07:03:18 AM UTC 24 1585098542 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2014863699 Sep 01 07:03:15 AM UTC 24 Sep 01 07:03:18 AM UTC 24 45101633 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1757688495 Sep 01 07:03:04 AM UTC 24 Sep 01 07:03:18 AM UTC 24 3227663528 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1663049920 Sep 01 07:03:12 AM UTC 24 Sep 01 07:03:18 AM UTC 24 84851067 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3510070926 Sep 01 07:03:03 AM UTC 24 Sep 01 07:03:19 AM UTC 24 158269782 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.3877375771 Sep 01 07:03:15 AM UTC 24 Sep 01 07:03:19 AM UTC 24 107474417 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1482055887 Sep 01 07:03:05 AM UTC 24 Sep 01 07:03:19 AM UTC 24 357914277 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.437277082 Sep 01 07:03:15 AM UTC 24 Sep 01 07:03:20 AM UTC 24 126964389 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1708320405 Sep 01 07:03:13 AM UTC 24 Sep 01 07:03:21 AM UTC 24 834368281 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1778277243 Sep 01 07:03:03 AM UTC 24 Sep 01 07:03:21 AM UTC 24 573887784 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2057634331 Sep 01 07:03:20 AM UTC 24 Sep 01 07:03:22 AM UTC 24 17653722 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.2606931189 Sep 01 07:03:17 AM UTC 24 Sep 01 07:03:22 AM UTC 24 19025196 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.319408788 Sep 01 07:03:17 AM UTC 24 Sep 01 07:03:22 AM UTC 24 104957040 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.410480191 Sep 01 07:03:20 AM UTC 24 Sep 01 07:03:22 AM UTC 24 118868608 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.263113726 Sep 01 07:03:20 AM UTC 24 Sep 01 07:03:23 AM UTC 24 31543435 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2518474443 Sep 01 07:03:14 AM UTC 24 Sep 01 07:03:23 AM UTC 24 53020358 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.3985601435 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:23 AM UTC 24 18626527 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3094647892 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:23 AM UTC 24 25856029 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1978855905 Sep 01 07:03:14 AM UTC 24 Sep 01 07:03:23 AM UTC 24 214346875 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2145621766 Sep 01 07:03:17 AM UTC 24 Sep 01 07:03:24 AM UTC 24 155162777 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2779979991 Sep 01 07:03:08 AM UTC 24 Sep 01 07:03:24 AM UTC 24 65825401 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1499408487 Sep 01 07:03:17 AM UTC 24 Sep 01 07:03:24 AM UTC 24 223385310 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2933251515 Sep 01 07:03:14 AM UTC 24 Sep 01 07:03:24 AM UTC 24 457954194 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.149890003 Sep 01 07:03:21 AM UTC 24 Sep 01 07:03:24 AM UTC 24 86028101 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.827840679 Sep 01 07:03:21 AM UTC 24 Sep 01 07:03:24 AM UTC 24 87795554 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.525902782 Sep 01 07:03:20 AM UTC 24 Sep 01 07:03:25 AM UTC 24 89903821 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.4043545129 Sep 01 07:03:17 AM UTC 24 Sep 01 07:03:25 AM UTC 24 740991603 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.686106423 Sep 01 07:03:21 AM UTC 24 Sep 01 07:03:25 AM UTC 24 282379493 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2645512858 Sep 01 07:03:20 AM UTC 24 Sep 01 07:03:26 AM UTC 24 1045229739 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4073567534 Sep 01 07:03:01 AM UTC 24 Sep 01 07:03:26 AM UTC 24 114625434 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.3006392962 Sep 01 07:03:22 AM UTC 24 Sep 01 07:03:27 AM UTC 24 52446183 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4125142551 Sep 01 07:03:22 AM UTC 24 Sep 01 07:03:27 AM UTC 24 14180514 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.1034092855 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:27 AM UTC 24 53096696 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1228512633 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:28 AM UTC 24 15438416 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3406528659 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:28 AM UTC 24 41566532 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.716487145 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:28 AM UTC 24 23352735 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2912149752 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:28 AM UTC 24 18771026 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.3669271393 Sep 01 07:03:26 AM UTC 24 Sep 01 07:03:28 AM UTC 24 21388272 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.250163750 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:28 AM UTC 24 21463977 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.3370373709 Sep 01 07:03:26 AM UTC 24 Sep 01 07:03:28 AM UTC 24 46268587 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3632866355 Sep 01 07:03:23 AM UTC 24 Sep 01 07:03:28 AM UTC 24 62512450 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.447091259 Sep 01 07:03:23 AM UTC 24 Sep 01 07:03:28 AM UTC 24 22792608 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1510357114 Sep 01 07:03:16 AM UTC 24 Sep 01 07:03:28 AM UTC 24 23885463 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3078781702 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:29 AM UTC 24 130220639 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3892996593 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:29 AM UTC 24 33913260 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1426368590 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:29 AM UTC 24 65374752 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2797464627 Sep 01 07:03:07 AM UTC 24 Sep 01 07:03:29 AM UTC 24 30474854 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.1585841730 Sep 01 07:03:27 AM UTC 24 Sep 01 07:03:29 AM UTC 24 13670975 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3388919915 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:29 AM UTC 24 112416714 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1056635762 Sep 01 07:03:26 AM UTC 24 Sep 01 07:03:29 AM UTC 24 53058994 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.4070861674 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:29 AM UTC 24 48647684 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3952762367 Sep 01 07:03:07 AM UTC 24 Sep 01 07:03:29 AM UTC 24 96736802 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.3988015058 Sep 01 07:03:23 AM UTC 24 Sep 01 07:03:30 AM UTC 24 97167387 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3787240757 Sep 01 07:03:23 AM UTC 24 Sep 01 07:03:30 AM UTC 24 45918468 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1939249369 Sep 01 07:03:27 AM UTC 24 Sep 01 07:03:30 AM UTC 24 257614712 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3010447064 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:30 AM UTC 24 223386379 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.699377756 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:30 AM UTC 24 176438327 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.4116240260 Sep 01 07:03:23 AM UTC 24 Sep 01 07:03:31 AM UTC 24 196760608 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.17085685 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:31 AM UTC 24 721557089 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.4283094887 Sep 01 07:03:25 AM UTC 24 Sep 01 07:03:31 AM UTC 24 189624717 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.3059933590 Sep 01 07:03:26 AM UTC 24 Sep 01 07:03:31 AM UTC 24 2252430312 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1663968086 Sep 01 07:03:19 AM UTC 24 Sep 01 07:03:31 AM UTC 24 3390744636 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3202142302 Sep 01 07:03:23 AM UTC 24 Sep 01 07:03:31 AM UTC 24 54369125 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3096370002 Sep 01 07:03:28 AM UTC 24 Sep 01 07:03:31 AM UTC 24 14381028 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2186186341 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 17463881 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2257978992 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 40006154 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.2803788291 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 15257582 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.583525823 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 30210426 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.2165650191 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 36844566 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.650504676 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 71900950 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2932724628 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 42526131 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1560819773 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 31191524 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3820638790 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 13476473 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.838230468 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 35286784 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1954930325 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 14491117 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.283835861 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 35715760 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.3616061072 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 17136225 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.3880229212 Sep 01 07:03:30 AM UTC 24 Sep 01 07:03:32 AM UTC 24 18384372 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2394794582 Sep 01 07:03:31 AM UTC 24 Sep 01 07:03:36 AM UTC 24 13870446 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.444956446 Sep 01 07:03:28 AM UTC 24 Sep 01 07:03:37 AM UTC 24 14683896 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.2495856190 Sep 01 07:03:28 AM UTC 24 Sep 01 07:03:37 AM UTC 24 37046073 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.262585713 Sep 01 07:03:28 AM UTC 24 Sep 01 07:03:37 AM UTC 24 11575137 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.2809510073 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:37 AM UTC 24 11643764 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2732905886 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:38 AM UTC 24 16088946 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.3513851977 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:38 AM UTC 24 12822054 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1654701221 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:38 AM UTC 24 15281263 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3189015687 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:38 AM UTC 24 15517140 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.92137471 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:48 AM UTC 24 14439255 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4071822170 Sep 01 07:03:02 AM UTC 24 Sep 01 07:03:48 AM UTC 24 262874186 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.830234876 Sep 01 07:03:29 AM UTC 24 Sep 01 07:03:48 AM UTC 24 17442985 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1879226116 Sep 01 07:03:02 AM UTC 24 Sep 01 07:03:48 AM UTC 24 222921279 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.375364877 Sep 01 07:03:32 AM UTC 24 Sep 01 07:04:23 AM UTC 24 49476738 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3348889230 Sep 01 07:03:31 AM UTC 24 Sep 01 07:04:23 AM UTC 24 20576343 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1263835797 Sep 01 07:03:31 AM UTC 24 Sep 01 07:04:24 AM UTC 24 58924957 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4253857884 Sep 01 07:03:02 AM UTC 24 Sep 01 07:04:44 AM UTC 24 291003383 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1893843875 Sep 01 07:03:12 AM UTC 24 Sep 01 07:05:22 AM UTC 24 16991493094 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2802479675 Sep 01 07:02:53 AM UTC 24 Sep 01 07:08:51 AM UTC 24 65300053550 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1899316839 Sep 01 07:03:00 AM UTC 24 Sep 01 07:22:52 AM UTC 24 406737178949 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1038693495 Sep 01 07:03:09 AM UTC 24 Sep 01 07:24:10 AM UTC 24 104455502963 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_smoke.468178759
Short name T3
Test name
Test status
Simulation time 2438445124 ps
CPU time 7.32 seconds
Started Sep 01 09:13:49 AM UTC 24
Finished Sep 01 09:13:57 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468178759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.468178759
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.3912568429
Short name T23
Test name
Test status
Simulation time 7874384212 ps
CPU time 59.55 seconds
Started Sep 01 09:15:45 AM UTC 24
Finished Sep 01 09:16:46 AM UTC 24
Peak memory 223832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39125684
29 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3912568429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_stress_all.2897467133
Short name T9
Test name
Test status
Simulation time 658120587 ps
CPU time 37.68 seconds
Started Sep 01 09:13:46 AM UTC 24
Finished Sep 01 09:14:26 AM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897467133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2897467133
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_stress_all.4003233040
Short name T60
Test name
Test status
Simulation time 1697828712 ps
CPU time 51.5 seconds
Started Sep 01 09:18:12 AM UTC 24
Finished Sep 01 09:19:05 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003233040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4003233040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.878883122
Short name T15
Test name
Test status
Simulation time 6033236034 ps
CPU time 96.45 seconds
Started Sep 01 09:13:50 AM UTC 24
Finished Sep 01 09:15:29 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878883122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.878883122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_error.1756009658
Short name T50
Test name
Test status
Simulation time 4084361872 ps
CPU time 137.58 seconds
Started Sep 01 09:14:24 AM UTC 24
Finished Sep 01 09:16:44 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756009658 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1756009658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3193420178
Short name T128
Test name
Test status
Simulation time 748802248 ps
CPU time 1.92 seconds
Started Sep 01 07:02:58 AM UTC 24
Finished Sep 01 07:03:08 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193420178 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3193420178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_long_msg.3629069857
Short name T164
Test name
Test status
Simulation time 2146365770 ps
CPU time 131.34 seconds
Started Sep 01 09:18:01 AM UTC 24
Finished Sep 01 09:20:15 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629069857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3629069857
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1472130688
Short name T1
Test name
Test status
Simulation time 180682321 ps
CPU time 1.49 seconds
Started Sep 01 09:13:47 AM UTC 24
Finished Sep 01 09:13:49 AM UTC 24
Peak memory 236004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472130688 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1472130688
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_smoke.2965256576
Short name T5
Test name
Test status
Simulation time 986609095 ps
CPU time 16.62 seconds
Started Sep 01 09:13:42 AM UTC 24
Finished Sep 01 09:14:00 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965256576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2965256576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2820089822
Short name T96
Test name
Test status
Simulation time 301932991 ps
CPU time 7.41 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:03:05 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820089822 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2820089822
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_error.4246092309
Short name T13
Test name
Test status
Simulation time 1393818448 ps
CPU time 85.28 seconds
Started Sep 01 09:13:51 AM UTC 24
Finished Sep 01 09:15:18 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246092309 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4246092309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.2083103615
Short name T123
Test name
Test status
Simulation time 921781423 ps
CPU time 51.99 seconds
Started Sep 01 09:17:13 AM UTC 24
Finished Sep 01 09:18:07 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083103615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2083103615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3778623192
Short name T25
Test name
Test status
Simulation time 65678930677 ps
CPU time 415.69 seconds
Started Sep 01 09:16:03 AM UTC 24
Finished Sep 01 09:23:04 AM UTC 24
Peak memory 622948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37786231
92 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3778623192
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.2218063377
Short name T16
Test name
Test status
Simulation time 5065506496 ps
CPU time 60.56 seconds
Started Sep 01 09:13:44 AM UTC 24
Finished Sep 01 09:14:46 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218063377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2218063377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.3059933590
Short name T62
Test name
Test status
Simulation time 2252430312 ps
CPU time 3.62 seconds
Started Sep 01 07:03:26 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059933590 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3059933590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.988108430
Short name T155
Test name
Test status
Simulation time 6623844051 ps
CPU time 40.77 seconds
Started Sep 01 09:29:37 AM UTC 24
Finished Sep 01 09:30:20 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988108430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.988108430
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.855216765
Short name T129
Test name
Test status
Simulation time 187320867 ps
CPU time 2.63 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:03:14 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855216765 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.855216765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_alert_test.1174495035
Short name T2
Test name
Test status
Simulation time 44982201 ps
CPU time 0.79 seconds
Started Sep 01 09:13:48 AM UTC 24
Finished Sep 01 09:13:49 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174495035 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1174495035
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_smoke.2769461849
Short name T146
Test name
Test status
Simulation time 6132634878 ps
CPU time 22.98 seconds
Started Sep 01 09:17:38 AM UTC 24
Finished Sep 01 09:18:03 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769461849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2769461849
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_stress_all.1637095323
Short name T482
Test name
Test status
Simulation time 55822886069 ps
CPU time 1021.46 seconds
Started Sep 01 09:24:06 AM UTC 24
Finished Sep 01 09:41:19 AM UTC 24
Peak memory 678092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637095323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1637095323
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.583571160
Short name T105
Test name
Test status
Simulation time 55171804 ps
CPU time 1 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:02:59 AM UTC 24
Peak memory 206208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583571160 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.583571160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_error.2808487188
Short name T219
Test name
Test status
Simulation time 12194500103 ps
CPU time 179.54 seconds
Started Sep 01 09:17:50 AM UTC 24
Finished Sep 01 09:20:53 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808487188 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2808487188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.347132557
Short name T553
Test name
Test status
Simulation time 3744691472 ps
CPU time 14.62 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:03:12 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347132557 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.347132557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3143196151
Short name T92
Test name
Test status
Simulation time 16916043 ps
CPU time 0.86 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:02:58 AM UTC 24
Peak memory 207012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143196151 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3143196151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2802479675
Short name T653
Test name
Test status
Simulation time 65300053550 ps
CPU time 348.95 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:08:51 AM UTC 24
Peak memory 223888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2802479675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.2802479675
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.888425811
Short name T535
Test name
Test status
Simulation time 15540305 ps
CPU time 0.65 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:02:58 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888425811 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.888425811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2359297023
Short name T106
Test name
Test status
Simulation time 1138713127 ps
CPU time 1.8 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:03:00 AM UTC 24
Peak memory 206852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359297023 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.2359297023
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.62363962
Short name T69
Test name
Test status
Simulation time 132924117 ps
CPU time 1.82 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:02:59 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62363962 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.62363962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3521293808
Short name T56
Test name
Test status
Simulation time 400770008 ps
CPU time 2.26 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:03:00 AM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521293808 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3521293808
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.696361357
Short name T95
Test name
Test status
Simulation time 321492038 ps
CPU time 6.09 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:03:03 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696361357 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.696361357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.3660335915
Short name T537
Test name
Test status
Simulation time 116244062 ps
CPU time 4.66 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:03:01 AM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660335915 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3660335915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2050616445
Short name T91
Test name
Test status
Simulation time 115975322 ps
CPU time 0.89 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:02:58 AM UTC 24
Peak memory 206896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050616445 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2050616445
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.592680917
Short name T67
Test name
Test status
Simulation time 117739496 ps
CPU time 1.62 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:02:58 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=592680917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_re
set.592680917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.441935189
Short name T90
Test name
Test status
Simulation time 30998932 ps
CPU time 0.86 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:02:57 AM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441935189 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.441935189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.792592795
Short name T534
Test name
Test status
Simulation time 15505225 ps
CPU time 0.54 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:02:57 AM UTC 24
Peak memory 204720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792592795 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.792592795
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3468921973
Short name T104
Test name
Test status
Simulation time 87249021 ps
CPU time 1.9 seconds
Started Sep 01 07:02:55 AM UTC 24
Finished Sep 01 07:02:58 AM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468921973 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.3468921973
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.4161030825
Short name T68
Test name
Test status
Simulation time 111874055 ps
CPU time 1.41 seconds
Started Sep 01 07:02:53 AM UTC 24
Finished Sep 01 07:02:59 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161030825 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4161030825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.2311739166
Short name T57
Test name
Test status
Simulation time 406743748 ps
CPU time 1.84 seconds
Started Sep 01 07:02:54 AM UTC 24
Finished Sep 01 07:03:00 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311739166 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2311739166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1893843875
Short name T652
Test name
Test status
Simulation time 16991493094 ps
CPU time 124.42 seconds
Started Sep 01 07:03:12 AM UTC 24
Finished Sep 01 07:05:22 AM UTC 24
Peak memory 223696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1893843875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.1893843875
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.722864248
Short name T560
Test name
Test status
Simulation time 30180473 ps
CPU time 0.73 seconds
Started Sep 01 07:03:11 AM UTC 24
Finished Sep 01 07:03:16 AM UTC 24
Peak memory 206340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722864248 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.722864248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2092784454
Short name T559
Test name
Test status
Simulation time 42906934 ps
CPU time 0.59 seconds
Started Sep 01 07:03:11 AM UTC 24
Finished Sep 01 07:03:16 AM UTC 24
Peak memory 203064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092784454 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2092784454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1663049920
Short name T567
Test name
Test status
Simulation time 84851067 ps
CPU time 1.89 seconds
Started Sep 01 07:03:12 AM UTC 24
Finished Sep 01 07:03:18 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663049920 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.1663049920
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2402116445
Short name T558
Test name
Test status
Simulation time 179809129 ps
CPU time 3.52 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:03:15 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402116445 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2402116445
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1978855905
Short name T578
Test name
Test status
Simulation time 214346875 ps
CPU time 1.26 seconds
Started Sep 01 07:03:14 AM UTC 24
Finished Sep 01 07:03:23 AM UTC 24
Peak memory 206520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1978855905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.1978855905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2518474443
Short name T575
Test name
Test status
Simulation time 53020358 ps
CPU time 0.97 seconds
Started Sep 01 07:03:14 AM UTC 24
Finished Sep 01 07:03:23 AM UTC 24
Peak memory 206660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518474443 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2518474443
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3315285536
Short name T562
Test name
Test status
Simulation time 16902662 ps
CPU time 0.55 seconds
Started Sep 01 07:03:13 AM UTC 24
Finished Sep 01 07:03:17 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315285536 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3315285536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2933251515
Short name T582
Test name
Test status
Simulation time 457954194 ps
CPU time 2.06 seconds
Started Sep 01 07:03:14 AM UTC 24
Finished Sep 01 07:03:24 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933251515 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.2933251515
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3929350331
Short name T66
Test name
Test status
Simulation time 461512095 ps
CPU time 3.94 seconds
Started Sep 01 07:03:13 AM UTC 24
Finished Sep 01 07:03:21 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929350331 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3929350331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1708320405
Short name T131
Test name
Test status
Simulation time 834368281 ps
CPU time 3.89 seconds
Started Sep 01 07:03:13 AM UTC 24
Finished Sep 01 07:03:21 AM UTC 24
Peak memory 207692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708320405 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1708320405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1510357114
Short name T602
Test name
Test status
Simulation time 23885463 ps
CPU time 1.15 seconds
Started Sep 01 07:03:16 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 206660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1510357114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.1510357114
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3372793921
Short name T102
Test name
Test status
Simulation time 19500386 ps
CPU time 0.85 seconds
Started Sep 01 07:03:15 AM UTC 24
Finished Sep 01 07:03:17 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372793921 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3372793921
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1718719223
Short name T563
Test name
Test status
Simulation time 45660063 ps
CPU time 0.75 seconds
Started Sep 01 07:03:15 AM UTC 24
Finished Sep 01 07:03:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718719223 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1718719223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2014863699
Short name T565
Test name
Test status
Simulation time 45101633 ps
CPU time 1.89 seconds
Started Sep 01 07:03:15 AM UTC 24
Finished Sep 01 07:03:18 AM UTC 24
Peak memory 206740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014863699 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.2014863699
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.437277082
Short name T569
Test name
Test status
Simulation time 126964389 ps
CPU time 2.72 seconds
Started Sep 01 07:03:15 AM UTC 24
Finished Sep 01 07:03:20 AM UTC 24
Peak memory 207872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437277082 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.437277082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.3877375771
Short name T133
Test name
Test status
Simulation time 107474417 ps
CPU time 1.83 seconds
Started Sep 01 07:03:15 AM UTC 24
Finished Sep 01 07:03:19 AM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877375771 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3877375771
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3892996593
Short name T604
Test name
Test status
Simulation time 33913260 ps
CPU time 1.74 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 206264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3892996593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.3892996593
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.319408788
Short name T572
Test name
Test status
Simulation time 104957040 ps
CPU time 0.65 seconds
Started Sep 01 07:03:17 AM UTC 24
Finished Sep 01 07:03:22 AM UTC 24
Peak memory 206520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319408788 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.319408788
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.2606931189
Short name T571
Test name
Test status
Simulation time 19025196 ps
CPU time 0.56 seconds
Started Sep 01 07:03:17 AM UTC 24
Finished Sep 01 07:03:22 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606931189 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2606931189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2145621766
Short name T579
Test name
Test status
Simulation time 155162777 ps
CPU time 1.92 seconds
Started Sep 01 07:03:17 AM UTC 24
Finished Sep 01 07:03:24 AM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145621766 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.2145621766
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1499408487
Short name T581
Test name
Test status
Simulation time 223385310 ps
CPU time 2.45 seconds
Started Sep 01 07:03:17 AM UTC 24
Finished Sep 01 07:03:24 AM UTC 24
Peak memory 207980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499408487 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1499408487
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.4043545129
Short name T586
Test name
Test status
Simulation time 740991603 ps
CPU time 3.25 seconds
Started Sep 01 07:03:17 AM UTC 24
Finished Sep 01 07:03:25 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043545129 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4043545129
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.699377756
Short name T616
Test name
Test status
Simulation time 176438327 ps
CPU time 3.14 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:30 AM UTC 24
Peak memory 218112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=699377756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_r
eset.699377756
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1228512633
Short name T593
Test name
Test status
Simulation time 15438416 ps
CPU time 0.67 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 206516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228512633 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1228512633
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.1034092855
Short name T592
Test name
Test status
Simulation time 53096696 ps
CPU time 0.55 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:27 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034092855 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1034092855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3388919915
Short name T608
Test name
Test status
Simulation time 112416714 ps
CPU time 2.13 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388919915 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.3388919915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.4070861674
Short name T610
Test name
Test status
Simulation time 48647684 ps
CPU time 2.45 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 208000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070861674 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4070861674
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1663968086
Short name T618
Test name
Test status
Simulation time 3390744636 ps
CPU time 4.12 seconds
Started Sep 01 07:03:19 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 207896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663968086 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1663968086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.827840679
Short name T584
Test name
Test status
Simulation time 87795554 ps
CPU time 2.13 seconds
Started Sep 01 07:03:21 AM UTC 24
Finished Sep 01 07:03:24 AM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=827840679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_r
eset.827840679
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2057634331
Short name T570
Test name
Test status
Simulation time 17653722 ps
CPU time 0.65 seconds
Started Sep 01 07:03:20 AM UTC 24
Finished Sep 01 07:03:22 AM UTC 24
Peak memory 206456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057634331 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2057634331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.263113726
Short name T574
Test name
Test status
Simulation time 31543435 ps
CPU time 0.55 seconds
Started Sep 01 07:03:20 AM UTC 24
Finished Sep 01 07:03:23 AM UTC 24
Peak memory 203420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263113726 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.263113726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.410480191
Short name T573
Test name
Test status
Simulation time 118868608 ps
CPU time 1.41 seconds
Started Sep 01 07:03:20 AM UTC 24
Finished Sep 01 07:03:22 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410480191 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.410480191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2645512858
Short name T588
Test name
Test status
Simulation time 1045229739 ps
CPU time 4.23 seconds
Started Sep 01 07:03:20 AM UTC 24
Finished Sep 01 07:03:26 AM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645512858 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2645512858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.525902782
Short name T585
Test name
Test status
Simulation time 89903821 ps
CPU time 2.68 seconds
Started Sep 01 07:03:20 AM UTC 24
Finished Sep 01 07:03:25 AM UTC 24
Peak memory 207888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525902782 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.525902782
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3202142302
Short name T619
Test name
Test status
Simulation time 54369125 ps
CPU time 3.47 seconds
Started Sep 01 07:03:23 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 217972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3202142302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.3202142302
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4125142551
Short name T591
Test name
Test status
Simulation time 14180514 ps
CPU time 0.81 seconds
Started Sep 01 07:03:22 AM UTC 24
Finished Sep 01 07:03:27 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125142551 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4125142551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.3006392962
Short name T590
Test name
Test status
Simulation time 52446183 ps
CPU time 0.68 seconds
Started Sep 01 07:03:22 AM UTC 24
Finished Sep 01 07:03:27 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006392962 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3006392962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3787240757
Short name T613
Test name
Test status
Simulation time 45918468 ps
CPU time 2.45 seconds
Started Sep 01 07:03:23 AM UTC 24
Finished Sep 01 07:03:30 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787240757 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.3787240757
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.686106423
Short name T587
Test name
Test status
Simulation time 282379493 ps
CPU time 3.34 seconds
Started Sep 01 07:03:21 AM UTC 24
Finished Sep 01 07:03:25 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686106423 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.686106423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.149890003
Short name T583
Test name
Test status
Simulation time 86028101 ps
CPU time 1.75 seconds
Started Sep 01 07:03:21 AM UTC 24
Finished Sep 01 07:03:24 AM UTC 24
Peak memory 206672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149890003 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.149890003
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.250163750
Short name T598
Test name
Test status
Simulation time 21463977 ps
CPU time 1.17 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=250163750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_r
eset.250163750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3632866355
Short name T600
Test name
Test status
Simulation time 62512450 ps
CPU time 0.66 seconds
Started Sep 01 07:03:23 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 206892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632866355 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3632866355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.447091259
Short name T601
Test name
Test status
Simulation time 22792608 ps
CPU time 0.72 seconds
Started Sep 01 07:03:23 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447091259 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.447091259
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.716487145
Short name T595
Test name
Test status
Simulation time 23352735 ps
CPU time 1.01 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 206796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716487145 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.716487145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.3988015058
Short name T612
Test name
Test status
Simulation time 97167387 ps
CPU time 2.18 seconds
Started Sep 01 07:03:23 AM UTC 24
Finished Sep 01 07:03:30 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988015058 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3988015058
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.4116240260
Short name T130
Test name
Test status
Simulation time 196760608 ps
CPU time 3.02 seconds
Started Sep 01 07:03:23 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116240260 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4116240260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3010447064
Short name T615
Test name
Test status
Simulation time 223386379 ps
CPU time 3.1 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:30 AM UTC 24
Peak memory 207988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3010447064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.3010447064
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2912149752
Short name T596
Test name
Test status
Simulation time 18771026 ps
CPU time 0.78 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 205820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912149752 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2912149752
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3406528659
Short name T594
Test name
Test status
Simulation time 41566532 ps
CPU time 0.73 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 203484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406528659 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3406528659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1426368590
Short name T605
Test name
Test status
Simulation time 65374752 ps
CPU time 1.7 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 206692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426368590 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.1426368590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.17085685
Short name T617
Test name
Test status
Simulation time 721557089 ps
CPU time 3.82 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17085685 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.17085685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.4283094887
Short name T135
Test name
Test status
Simulation time 189624717 ps
CPU time 4.06 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283094887 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4283094887
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1939249369
Short name T614
Test name
Test status
Simulation time 257614712 ps
CPU time 1.99 seconds
Started Sep 01 07:03:27 AM UTC 24
Finished Sep 01 07:03:30 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1939249369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.1939249369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.3370373709
Short name T599
Test name
Test status
Simulation time 46268587 ps
CPU time 1.03 seconds
Started Sep 01 07:03:26 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370373709 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3370373709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.3669271393
Short name T597
Test name
Test status
Simulation time 21388272 ps
CPU time 0.7 seconds
Started Sep 01 07:03:26 AM UTC 24
Finished Sep 01 07:03:28 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669271393 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3669271393
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1056635762
Short name T609
Test name
Test status
Simulation time 53058994 ps
CPU time 1.88 seconds
Started Sep 01 07:03:26 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056635762 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.1056635762
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3078781702
Short name T603
Test name
Test status
Simulation time 130220639 ps
CPU time 1.47 seconds
Started Sep 01 07:03:25 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 206608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078781702 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3078781702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.949086470
Short name T542
Test name
Test status
Simulation time 412420053 ps
CPU time 4.88 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 207872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949086470 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.949086470
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3468427091
Short name T103
Test name
Test status
Simulation time 1585098542 ps
CPU time 16.06 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:18 AM UTC 24
Peak memory 207864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468427091 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3468427091
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2958691832
Short name T93
Test name
Test status
Simulation time 23833353 ps
CPU time 1.02 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:02 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958691832 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2958691832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1899316839
Short name T654
Test name
Test status
Simulation time 406737178949 ps
CPU time 1175.33 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:22:52 AM UTC 24
Peak memory 227972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1899316839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.1899316839
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.888144814
Short name T108
Test name
Test status
Simulation time 107380109 ps
CPU time 0.98 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:03 AM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888144814 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.888144814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.22695201
Short name T538
Test name
Test status
Simulation time 15550368 ps
CPU time 0.72 seconds
Started Sep 01 07:02:59 AM UTC 24
Finished Sep 01 07:03:02 AM UTC 24
Peak memory 203592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22695201 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.22695201
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3058775796
Short name T109
Test name
Test status
Simulation time 297975010 ps
CPU time 1.92 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:04 AM UTC 24
Peak memory 206720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058775796 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.3058775796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.4113338190
Short name T536
Test name
Test status
Simulation time 77980322 ps
CPU time 1.77 seconds
Started Sep 01 07:02:57 AM UTC 24
Finished Sep 01 07:03:00 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113338190 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.4113338190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.1585841730
Short name T607
Test name
Test status
Simulation time 13670975 ps
CPU time 0.78 seconds
Started Sep 01 07:03:27 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585841730 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1585841730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.444956446
Short name T636
Test name
Test status
Simulation time 14683896 ps
CPU time 0.69 seconds
Started Sep 01 07:03:28 AM UTC 24
Finished Sep 01 07:03:37 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444956446 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.444956446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.2495856190
Short name T637
Test name
Test status
Simulation time 37046073 ps
CPU time 0.71 seconds
Started Sep 01 07:03:28 AM UTC 24
Finished Sep 01 07:03:37 AM UTC 24
Peak memory 203516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495856190 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2495856190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.262585713
Short name T638
Test name
Test status
Simulation time 11575137 ps
CPU time 0.76 seconds
Started Sep 01 07:03:28 AM UTC 24
Finished Sep 01 07:03:37 AM UTC 24
Peak memory 203556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262585713 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.262585713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3096370002
Short name T620
Test name
Test status
Simulation time 14381028 ps
CPU time 0.61 seconds
Started Sep 01 07:03:28 AM UTC 24
Finished Sep 01 07:03:31 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096370002 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3096370002
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2732905886
Short name T640
Test name
Test status
Simulation time 16088946 ps
CPU time 0.67 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:38 AM UTC 24
Peak memory 203548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732905886 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2732905886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.3513851977
Short name T641
Test name
Test status
Simulation time 12822054 ps
CPU time 0.67 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:38 AM UTC 24
Peak memory 203548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513851977 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3513851977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3189015687
Short name T643
Test name
Test status
Simulation time 15517140 ps
CPU time 0.65 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:38 AM UTC 24
Peak memory 203384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189015687 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3189015687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.2809510073
Short name T639
Test name
Test status
Simulation time 11643764 ps
CPU time 0.55 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:37 AM UTC 24
Peak memory 203544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809510073 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2809510073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1654701221
Short name T642
Test name
Test status
Simulation time 15281263 ps
CPU time 0.67 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:38 AM UTC 24
Peak memory 203580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654701221 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1654701221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.2694872541
Short name T99
Test name
Test status
Simulation time 366994558 ps
CPU time 5.72 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:11 AM UTC 24
Peak memory 207368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694872541 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2694872541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2356698828
Short name T550
Test name
Test status
Simulation time 8779165916 ps
CPU time 10.12 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:11 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356698828 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2356698828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1919193136
Short name T94
Test name
Test status
Simulation time 105222877 ps
CPU time 0.81 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:02 AM UTC 24
Peak memory 206248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919193136 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1919193136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4073567534
Short name T589
Test name
Test status
Simulation time 114625434 ps
CPU time 1.09 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:26 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4073567534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.4073567534
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3025448167
Short name T107
Test name
Test status
Simulation time 33555420 ps
CPU time 0.69 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:02 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025448167 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3025448167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.305845871
Short name T539
Test name
Test status
Simulation time 55719376 ps
CPU time 0.76 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:03 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305845871 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.305845871
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.470251958
Short name T111
Test name
Test status
Simulation time 123045888 ps
CPU time 1.65 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470251958 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.470251958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.4168911537
Short name T540
Test name
Test status
Simulation time 204468894 ps
CPU time 2.74 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:04 AM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168911537 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4168911537
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.997191072
Short name T58
Test name
Test status
Simulation time 94329995 ps
CPU time 1.96 seconds
Started Sep 01 07:03:00 AM UTC 24
Finished Sep 01 07:03:04 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997191072 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.997191072
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.92137471
Short name T644
Test name
Test status
Simulation time 14439255 ps
CPU time 0.61 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:48 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92137471 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.92137471
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.830234876
Short name T646
Test name
Test status
Simulation time 17442985 ps
CPU time 0.65 seconds
Started Sep 01 07:03:29 AM UTC 24
Finished Sep 01 07:03:48 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830234876 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.830234876
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.2803788291
Short name T623
Test name
Test status
Simulation time 15257582 ps
CPU time 0.59 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803788291 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2803788291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.583525823
Short name T624
Test name
Test status
Simulation time 30210426 ps
CPU time 0.56 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583525823 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.583525823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2257978992
Short name T622
Test name
Test status
Simulation time 40006154 ps
CPU time 0.62 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257978992 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2257978992
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.2165650191
Short name T625
Test name
Test status
Simulation time 36844566 ps
CPU time 0.62 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165650191 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2165650191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2186186341
Short name T621
Test name
Test status
Simulation time 17463881 ps
CPU time 0.6 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186186341 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2186186341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.650504676
Short name T626
Test name
Test status
Simulation time 71900950 ps
CPU time 0.66 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650504676 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.650504676
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2932724628
Short name T627
Test name
Test status
Simulation time 42526131 ps
CPU time 0.6 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932724628 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2932724628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3820638790
Short name T629
Test name
Test status
Simulation time 13476473 ps
CPU time 0.62 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820638790 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3820638790
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1879226116
Short name T647
Test name
Test status
Simulation time 222921279 ps
CPU time 5.24 seconds
Started Sep 01 07:03:02 AM UTC 24
Finished Sep 01 07:03:48 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879226116 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1879226116
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4163670827
Short name T549
Test name
Test status
Simulation time 111443438 ps
CPU time 4.61 seconds
Started Sep 01 07:03:02 AM UTC 24
Finished Sep 01 07:03:10 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163670827 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4163670827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2488123124
Short name T97
Test name
Test status
Simulation time 22990036 ps
CPU time 0.97 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 206664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488123124 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2488123124
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4071822170
Short name T645
Test name
Test status
Simulation time 262874186 ps
CPU time 1.83 seconds
Started Sep 01 07:03:02 AM UTC 24
Finished Sep 01 07:03:48 AM UTC 24
Peak memory 224076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4071822170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.4071822170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.1325191309
Short name T110
Test name
Test status
Simulation time 31802604 ps
CPU time 0.85 seconds
Started Sep 01 07:03:02 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325191309 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1325191309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.2221121728
Short name T541
Test name
Test status
Simulation time 15800623 ps
CPU time 0.7 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:06 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221121728 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2221121728
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4253857884
Short name T651
Test name
Test status
Simulation time 291003383 ps
CPU time 1.52 seconds
Started Sep 01 07:03:02 AM UTC 24
Finished Sep 01 07:04:44 AM UTC 24
Peak memory 206792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253857884 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.4253857884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.3016682446
Short name T545
Test name
Test status
Simulation time 138354772 ps
CPU time 2.32 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:08 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016682446 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3016682446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.549572918
Short name T125
Test name
Test status
Simulation time 105177375 ps
CPU time 2.71 seconds
Started Sep 01 07:03:01 AM UTC 24
Finished Sep 01 07:03:08 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549572918 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.549572918
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.838230468
Short name T630
Test name
Test status
Simulation time 35286784 ps
CPU time 0.55 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838230468 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.838230468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1560819773
Short name T628
Test name
Test status
Simulation time 31191524 ps
CPU time 0.6 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560819773 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1560819773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1954930325
Short name T631
Test name
Test status
Simulation time 14491117 ps
CPU time 0.56 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954930325 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1954930325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.283835861
Short name T632
Test name
Test status
Simulation time 35715760 ps
CPU time 0.61 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283835861 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.283835861
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.3616061072
Short name T633
Test name
Test status
Simulation time 17136225 ps
CPU time 0.6 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616061072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3616061072
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.3880229212
Short name T634
Test name
Test status
Simulation time 18384372 ps
CPU time 0.59 seconds
Started Sep 01 07:03:30 AM UTC 24
Finished Sep 01 07:03:32 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880229212 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3880229212
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2394794582
Short name T635
Test name
Test status
Simulation time 13870446 ps
CPU time 0.62 seconds
Started Sep 01 07:03:31 AM UTC 24
Finished Sep 01 07:03:36 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394794582 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2394794582
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1263835797
Short name T650
Test name
Test status
Simulation time 58924957 ps
CPU time 0.79 seconds
Started Sep 01 07:03:31 AM UTC 24
Finished Sep 01 07:04:24 AM UTC 24
Peak memory 203544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263835797 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1263835797
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3348889230
Short name T649
Test name
Test status
Simulation time 20576343 ps
CPU time 0.66 seconds
Started Sep 01 07:03:31 AM UTC 24
Finished Sep 01 07:04:23 AM UTC 24
Peak memory 203580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348889230 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3348889230
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.375364877
Short name T648
Test name
Test status
Simulation time 49476738 ps
CPU time 0.6 seconds
Started Sep 01 07:03:32 AM UTC 24
Finished Sep 01 07:04:23 AM UTC 24
Peak memory 203608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375364877 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.375364877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3962852823
Short name T546
Test name
Test status
Simulation time 66316252 ps
CPU time 2.22 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:08 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3962852823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.3962852823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2765449929
Short name T100
Test name
Test status
Simulation time 56539576 ps
CPU time 0.75 seconds
Started Sep 01 07:03:03 AM UTC 24
Finished Sep 01 07:03:12 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765449929 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2765449929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.467139120
Short name T564
Test name
Test status
Simulation time 29954260 ps
CPU time 0.7 seconds
Started Sep 01 07:03:03 AM UTC 24
Finished Sep 01 07:03:18 AM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467139120 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.467139120
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2275925452
Short name T112
Test name
Test status
Simulation time 212401438 ps
CPU time 1.14 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 206704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275925452 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.2275925452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3510070926
Short name T568
Test name
Test status
Simulation time 158269782 ps
CPU time 1.7 seconds
Started Sep 01 07:03:03 AM UTC 24
Finished Sep 01 07:03:19 AM UTC 24
Peak memory 206616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510070926 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3510070926
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1778277243
Short name T134
Test name
Test status
Simulation time 573887784 ps
CPU time 4.18 seconds
Started Sep 01 07:03:03 AM UTC 24
Finished Sep 01 07:03:21 AM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778277243 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1778277243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1757688495
Short name T566
Test name
Test status
Simulation time 3227663528 ps
CPU time 11.91 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:18 AM UTC 24
Peak memory 223472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1757688495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.1757688495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1871128877
Short name T98
Test name
Test status
Simulation time 41399997 ps
CPU time 0.88 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871128877 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1871128877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.3918926773
Short name T543
Test name
Test status
Simulation time 43074269 ps
CPU time 0.68 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:07 AM UTC 24
Peak memory 203648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918926773 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3918926773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2632494122
Short name T547
Test name
Test status
Simulation time 45740446 ps
CPU time 2 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:08 AM UTC 24
Peak memory 206792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632494122 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.2632494122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3756155013
Short name T548
Test name
Test status
Simulation time 413349812 ps
CPU time 2.58 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:09 AM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756155013 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3756155013
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3845075060
Short name T126
Test name
Test status
Simulation time 290385669 ps
CPU time 4.12 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:10 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845075060 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3845075060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1633138196
Short name T554
Test name
Test status
Simulation time 47708764 ps
CPU time 1.77 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:14 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1633138196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.1633138196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2797464627
Short name T606
Test name
Test status
Simulation time 30474854 ps
CPU time 1.21 seconds
Started Sep 01 07:03:07 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797464627 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2797464627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3324341662
Short name T561
Test name
Test status
Simulation time 19436869 ps
CPU time 0.62 seconds
Started Sep 01 07:03:05 AM UTC 24
Finished Sep 01 07:03:17 AM UTC 24
Peak memory 203608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324341662 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3324341662
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3952762367
Short name T611
Test name
Test status
Simulation time 96736802 ps
CPU time 1.61 seconds
Started Sep 01 07:03:07 AM UTC 24
Finished Sep 01 07:03:29 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952762367 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.3952762367
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2915759578
Short name T544
Test name
Test status
Simulation time 24423707 ps
CPU time 1.33 seconds
Started Sep 01 07:03:04 AM UTC 24
Finished Sep 01 07:03:08 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915759578 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2915759578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1482055887
Short name T132
Test name
Test status
Simulation time 357914277 ps
CPU time 2.86 seconds
Started Sep 01 07:03:05 AM UTC 24
Finished Sep 01 07:03:19 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482055887 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1482055887
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2779979991
Short name T580
Test name
Test status
Simulation time 65825401 ps
CPU time 1.53 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:24 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2779979991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.2779979991
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3094647892
Short name T577
Test name
Test status
Simulation time 25856029 ps
CPU time 0.92 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:23 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094647892 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3094647892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.3985601435
Short name T576
Test name
Test status
Simulation time 18626527 ps
CPU time 0.85 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:23 AM UTC 24
Peak memory 203608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985601435 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3985601435
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3877461033
Short name T556
Test name
Test status
Simulation time 90207787 ps
CPU time 2.02 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:14 AM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877461033 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.3877461033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2890043560
Short name T557
Test name
Test status
Simulation time 132297880 ps
CPU time 2.58 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:14 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890043560 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2890043560
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.1815028253
Short name T555
Test name
Test status
Simulation time 97719089 ps
CPU time 1.98 seconds
Started Sep 01 07:03:08 AM UTC 24
Finished Sep 01 07:03:14 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815028253 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1815028253
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1038693495
Short name T655
Test name
Test status
Simulation time 104455502963 ps
CPU time 1244.63 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:24:10 AM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1038693495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.1038693495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.41719961
Short name T101
Test name
Test status
Simulation time 39612787 ps
CPU time 0.77 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:03:12 AM UTC 24
Peak memory 206572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41719961 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.41719961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.4172284947
Short name T551
Test name
Test status
Simulation time 15458604 ps
CPU time 0.56 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:03:12 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172284947 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4172284947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1553158419
Short name T552
Test name
Test status
Simulation time 81164143 ps
CPU time 1.01 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:03:12 AM UTC 24
Peak memory 206788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553158419 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.1553158419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.2026059460
Short name T127
Test name
Test status
Simulation time 124233311 ps
CPU time 1.56 seconds
Started Sep 01 07:03:09 AM UTC 24
Finished Sep 01 07:03:13 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026059460 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2026059460
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2021316931
Short name T6
Test name
Test status
Simulation time 632778275 ps
CPU time 19 seconds
Started Sep 01 09:13:43 AM UTC 24
Finished Sep 01 09:14:03 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021316931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2021316931
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.2344452523
Short name T14
Test name
Test status
Simulation time 17616896942 ps
CPU time 55.9 seconds
Started Sep 01 09:13:43 AM UTC 24
Finished Sep 01 09:14:40 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344452523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2344452523
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.2486652661
Short name T140
Test name
Test status
Simulation time 1775359278 ps
CPU time 347.34 seconds
Started Sep 01 09:13:43 AM UTC 24
Finished Sep 01 09:19:34 AM UTC 24
Peak memory 704680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486652661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2486652661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_error.4003818701
Short name T47
Test name
Test status
Simulation time 8978334169 ps
CPU time 143.53 seconds
Started Sep 01 09:13:43 AM UTC 24
Finished Sep 01 09:16:09 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003818701 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4003818701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_long_msg.4121950820
Short name T17
Test name
Test status
Simulation time 7542969432 ps
CPU time 43.58 seconds
Started Sep 01 09:13:43 AM UTC 24
Finished Sep 01 09:14:28 AM UTC 24
Peak memory 217880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121950820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4121950820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.544259356
Short name T64
Test name
Test status
Simulation time 38275835866 ps
CPU time 648.75 seconds
Started Sep 01 09:13:46 AM UTC 24
Finished Sep 01 09:24:43 AM UTC 24
Peak memory 725368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54425935
6 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.544259356
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.2072484443
Short name T19
Test name
Test status
Simulation time 2672911265 ps
CPU time 50.03 seconds
Started Sep 01 09:13:45 AM UTC 24
Finished Sep 01 09:14:37 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072484443 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2072484443
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2516117745
Short name T36
Test name
Test status
Simulation time 9570184252 ps
CPU time 114.26 seconds
Started Sep 01 09:13:45 AM UTC 24
Finished Sep 01 09:15:42 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516117745 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2516117745
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.915138568
Short name T171
Test name
Test status
Simulation time 6018134118 ps
CPU time 151.37 seconds
Started Sep 01 09:13:46 AM UTC 24
Finished Sep 01 09:16:21 AM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915138568 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.915138568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.1966470318
Short name T265
Test name
Test status
Simulation time 13151630122 ps
CPU time 616.43 seconds
Started Sep 01 09:13:44 AM UTC 24
Finished Sep 01 09:24:08 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966470318 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1966470318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.1275563345
Short name T516
Test name
Test status
Simulation time 859947613168 ps
CPU time 2796.66 seconds
Started Sep 01 09:13:45 AM UTC 24
Finished Sep 01 10:00:54 AM UTC 24
Peak memory 221236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275563345 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1275563345
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.4161403217
Short name T517
Test name
Test status
Simulation time 579350433479 ps
CPU time 2857.82 seconds
Started Sep 01 09:13:45 AM UTC 24
Finished Sep 01 10:01:56 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161403217 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.4161403217
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_alert_test.1094762008
Short name T28
Test name
Test status
Simulation time 15390559 ps
CPU time 0.86 seconds
Started Sep 01 09:14:06 AM UTC 24
Finished Sep 01 09:14:08 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094762008 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1094762008
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.4044944031
Short name T4
Test name
Test status
Simulation time 573561047 ps
CPU time 6.21 seconds
Started Sep 01 09:13:50 AM UTC 24
Finished Sep 01 09:13:57 AM UTC 24
Peak memory 207124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044944031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4044944031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.2142328345
Short name T387
Test name
Test status
Simulation time 22373035790 ps
CPU time 1138.12 seconds
Started Sep 01 09:13:50 AM UTC 24
Finished Sep 01 09:33:01 AM UTC 24
Peak memory 768180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142328345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2142328345
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_long_msg.674362810
Short name T7
Test name
Test status
Simulation time 1240965358 ps
CPU time 15.28 seconds
Started Sep 01 09:13:49 AM UTC 24
Finished Sep 01 09:14:05 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674362810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.674362810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.1918469468
Short name T27
Test name
Test status
Simulation time 55849141 ps
CPU time 1.3 seconds
Started Sep 01 09:14:04 AM UTC 24
Finished Sep 01 09:14:06 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918469468 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1918469468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_stress_all.2510961781
Short name T279
Test name
Test status
Simulation time 28969145159 ps
CPU time 673.48 seconds
Started Sep 01 09:14:03 AM UTC 24
Finished Sep 01 09:25:25 AM UTC 24
Peak memory 686360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510961781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2510961781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.2333651449
Short name T46
Test name
Test status
Simulation time 4777586296 ps
CPU time 79.78 seconds
Started Sep 01 09:13:58 AM UTC 24
Finished Sep 01 09:15:20 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333651449 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2333651449
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.61745361
Short name T170
Test name
Test status
Simulation time 39722175289 ps
CPU time 132.02 seconds
Started Sep 01 09:14:01 AM UTC 24
Finished Sep 01 09:16:15 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61745361 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.61745361
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.815125454
Short name T38
Test name
Test status
Simulation time 7031046269 ps
CPU time 105.25 seconds
Started Sep 01 09:14:01 AM UTC 24
Finished Sep 01 09:15:48 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815125454 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.815125454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.2548576794
Short name T143
Test name
Test status
Simulation time 35181326780 ps
CPU time 751.3 seconds
Started Sep 01 09:13:51 AM UTC 24
Finished Sep 01 09:26:33 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548576794 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2548576794
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.331252516
Short name T514
Test name
Test status
Simulation time 278423302239 ps
CPU time 2690.31 seconds
Started Sep 01 09:13:52 AM UTC 24
Finished Sep 01 09:59:13 AM UTC 24
Peak memory 221444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331252516 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.331252516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.2923116760
Short name T505
Test name
Test status
Simulation time 129322359648 ps
CPU time 2441.46 seconds
Started Sep 01 09:13:58 AM UTC 24
Finished Sep 01 09:55:07 AM UTC 24
Peak memory 221256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923116760 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2923116760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.1022743297
Short name T39
Test name
Test status
Simulation time 8203103788 ps
CPU time 117.6 seconds
Started Sep 01 09:13:51 AM UTC 24
Finished Sep 01 09:15:51 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022743297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1022743297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_alert_test.2370726483
Short name T186
Test name
Test status
Simulation time 14559364 ps
CPU time 0.85 seconds
Started Sep 01 09:17:58 AM UTC 24
Finished Sep 01 09:18:00 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370726483 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2370726483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.1095568385
Short name T26
Test name
Test status
Simulation time 2790849979 ps
CPU time 94.15 seconds
Started Sep 01 09:17:40 AM UTC 24
Finished Sep 01 09:19:16 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095568385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1095568385
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.2589942410
Short name T189
Test name
Test status
Simulation time 1733186096 ps
CPU time 32.98 seconds
Started Sep 01 09:17:43 AM UTC 24
Finished Sep 01 09:18:18 AM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589942410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2589942410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.4121954730
Short name T442
Test name
Test status
Simulation time 12529918324 ps
CPU time 1163.85 seconds
Started Sep 01 09:17:40 AM UTC 24
Finished Sep 01 09:37:17 AM UTC 24
Peak memory 700700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121954730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4121954730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_long_msg.3426820387
Short name T192
Test name
Test status
Simulation time 5378206749 ps
CPU time 62.57 seconds
Started Sep 01 09:17:38 AM UTC 24
Finished Sep 01 09:18:43 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426820387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3426820387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_stress_all.1240114657
Short name T59
Test name
Test status
Simulation time 1905998839 ps
CPU time 43.08 seconds
Started Sep 01 09:17:55 AM UTC 24
Finished Sep 01 09:18:40 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240114657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1240114657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.1824169648
Short name T191
Test name
Test status
Simulation time 3573491224 ps
CPU time 26.59 seconds
Started Sep 01 09:17:53 AM UTC 24
Finished Sep 01 09:18:21 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824169648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1824169648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_alert_test.1368117170
Short name T190
Test name
Test status
Simulation time 34094573 ps
CPU time 0.84 seconds
Started Sep 01 09:18:19 AM UTC 24
Finished Sep 01 09:18:20 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368117170 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1368117170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.3902872854
Short name T199
Test name
Test status
Simulation time 925306533 ps
CPU time 59.33 seconds
Started Sep 01 09:18:02 AM UTC 24
Finished Sep 01 09:19:03 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902872854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3902872854
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.3253745700
Short name T198
Test name
Test status
Simulation time 21632856724 ps
CPU time 52.12 seconds
Started Sep 01 09:18:05 AM UTC 24
Finished Sep 01 09:18:59 AM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253745700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3253745700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.2169696030
Short name T476
Test name
Test status
Simulation time 23947516660 ps
CPU time 1330.67 seconds
Started Sep 01 09:18:05 AM UTC 24
Finished Sep 01 09:40:31 AM UTC 24
Peak memory 702896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169696030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2169696030
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_error.1796608334
Short name T227
Test name
Test status
Simulation time 24572348966 ps
CPU time 188.75 seconds
Started Sep 01 09:18:07 AM UTC 24
Finished Sep 01 09:21:19 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796608334 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1796608334
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_smoke.407039852
Short name T188
Test name
Test status
Simulation time 548588644 ps
CPU time 9.09 seconds
Started Sep 01 09:18:01 AM UTC 24
Finished Sep 01 09:18:11 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407039852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.407039852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.1040750410
Short name T162
Test name
Test status
Simulation time 2689903533 ps
CPU time 68.45 seconds
Started Sep 01 09:18:08 AM UTC 24
Finished Sep 01 09:19:19 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040750410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1040750410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_alert_test.2055646279
Short name T196
Test name
Test status
Simulation time 15585429 ps
CPU time 0.71 seconds
Started Sep 01 09:18:48 AM UTC 24
Finished Sep 01 09:18:50 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055646279 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2055646279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.642279134
Short name T147
Test name
Test status
Simulation time 2583966338 ps
CPU time 75.58 seconds
Started Sep 01 09:18:31 AM UTC 24
Finished Sep 01 09:19:49 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642279134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.642279134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.509497776
Short name T148
Test name
Test status
Simulation time 2129398627 ps
CPU time 62.71 seconds
Started Sep 01 09:18:40 AM UTC 24
Finished Sep 01 09:19:45 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509497776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.509497776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.2045326282
Short name T247
Test name
Test status
Simulation time 1659343943 ps
CPU time 275.71 seconds
Started Sep 01 09:18:36 AM UTC 24
Finished Sep 01 09:23:16 AM UTC 24
Peak memory 485792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045326282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2045326282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_error.1564025917
Short name T220
Test name
Test status
Simulation time 6357393222 ps
CPU time 124.79 seconds
Started Sep 01 09:18:46 AM UTC 24
Finished Sep 01 09:20:53 AM UTC 24
Peak memory 207376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564025917 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1564025917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_long_msg.944882000
Short name T207
Test name
Test status
Simulation time 1658863596 ps
CPU time 71.54 seconds
Started Sep 01 09:18:22 AM UTC 24
Finished Sep 01 09:19:35 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944882000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.944882000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_smoke.734550142
Short name T194
Test name
Test status
Simulation time 1779076612 ps
CPU time 21.44 seconds
Started Sep 01 09:18:22 AM UTC 24
Finished Sep 01 09:18:45 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734550142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.734550142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_stress_all.3020088353
Short name T240
Test name
Test status
Simulation time 28267821106 ps
CPU time 223.58 seconds
Started Sep 01 09:18:46 AM UTC 24
Finished Sep 01 09:22:33 AM UTC 24
Peak memory 223852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020088353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3020088353
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3786004291
Short name T204
Test name
Test status
Simulation time 3569216117 ps
CPU time 35.24 seconds
Started Sep 01 09:18:46 AM UTC 24
Finished Sep 01 09:19:22 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786004291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3786004291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_alert_test.2236215830
Short name T201
Test name
Test status
Simulation time 24050539 ps
CPU time 0.92 seconds
Started Sep 01 09:19:06 AM UTC 24
Finished Sep 01 09:19:08 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236215830 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2236215830
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.3865099080
Short name T42
Test name
Test status
Simulation time 22281680058 ps
CPU time 72.26 seconds
Started Sep 01 09:18:52 AM UTC 24
Finished Sep 01 09:20:06 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865099080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3865099080
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.599429864
Short name T149
Test name
Test status
Simulation time 3907093520 ps
CPU time 55.09 seconds
Started Sep 01 09:18:56 AM UTC 24
Finished Sep 01 09:19:52 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599429864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.599429864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.1784769589
Short name T298
Test name
Test status
Simulation time 2723238666 ps
CPU time 462.99 seconds
Started Sep 01 09:18:52 AM UTC 24
Finished Sep 01 09:26:40 AM UTC 24
Peak memory 741868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784769589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1784769589
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_error.2887130277
Short name T202
Test name
Test status
Simulation time 171616076 ps
CPU time 9.87 seconds
Started Sep 01 09:19:00 AM UTC 24
Finished Sep 01 09:19:11 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887130277 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2887130277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_long_msg.3621497278
Short name T200
Test name
Test status
Simulation time 579967837 ps
CPU time 15.32 seconds
Started Sep 01 09:18:50 AM UTC 24
Finished Sep 01 09:19:06 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621497278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3621497278
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_smoke.1951899802
Short name T197
Test name
Test status
Simulation time 275947115 ps
CPU time 5.87 seconds
Started Sep 01 09:18:48 AM UTC 24
Finished Sep 01 09:18:55 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951899802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1951899802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_stress_all.567585117
Short name T507
Test name
Test status
Simulation time 73478125874 ps
CPU time 2176.29 seconds
Started Sep 01 09:19:05 AM UTC 24
Finished Sep 01 09:55:45 AM UTC 24
Peak memory 803072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567585117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.567585117
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.3384735477
Short name T213
Test name
Test status
Simulation time 28389400842 ps
CPU time 73.39 seconds
Started Sep 01 09:19:05 AM UTC 24
Finished Sep 01 09:20:20 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384735477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3384735477
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_alert_test.1422998838
Short name T206
Test name
Test status
Simulation time 15481388 ps
CPU time 0.86 seconds
Started Sep 01 09:19:26 AM UTC 24
Finished Sep 01 09:19:28 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422998838 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1422998838
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1245084083
Short name T33
Test name
Test status
Simulation time 1979505744 ps
CPU time 79.28 seconds
Started Sep 01 09:19:11 AM UTC 24
Finished Sep 01 09:20:33 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245084083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1245084083
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.440838549
Short name T217
Test name
Test status
Simulation time 4756915707 ps
CPU time 81.22 seconds
Started Sep 01 09:19:20 AM UTC 24
Finished Sep 01 09:20:43 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440838549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.440838549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.1627904579
Short name T397
Test name
Test status
Simulation time 31655543399 ps
CPU time 859.67 seconds
Started Sep 01 09:19:17 AM UTC 24
Finished Sep 01 09:33:47 AM UTC 24
Peak memory 729368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627904579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1627904579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_error.1656250726
Short name T230
Test name
Test status
Simulation time 6952554056 ps
CPU time 132.89 seconds
Started Sep 01 09:19:20 AM UTC 24
Finished Sep 01 09:21:35 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656250726 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1656250726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_long_msg.2448162528
Short name T254
Test name
Test status
Simulation time 88941640165 ps
CPU time 262.88 seconds
Started Sep 01 09:19:08 AM UTC 24
Finished Sep 01 09:23:35 AM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448162528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2448162528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_smoke.2954341005
Short name T203
Test name
Test status
Simulation time 2163194119 ps
CPU time 9.79 seconds
Started Sep 01 09:19:07 AM UTC 24
Finished Sep 01 09:19:18 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954341005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2954341005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_stress_all.663284359
Short name T524
Test name
Test status
Simulation time 74516813638 ps
CPU time 3039.36 seconds
Started Sep 01 09:19:24 AM UTC 24
Finished Sep 01 10:10:34 AM UTC 24
Peak memory 770360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663284359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.663284359
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.2563222815
Short name T209
Test name
Test status
Simulation time 1287161934 ps
CPU time 23.15 seconds
Started Sep 01 09:19:24 AM UTC 24
Finished Sep 01 09:19:48 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563222815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2563222815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_alert_test.2974694612
Short name T210
Test name
Test status
Simulation time 13969970 ps
CPU time 0.89 seconds
Started Sep 01 09:19:52 AM UTC 24
Finished Sep 01 09:19:54 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974694612 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2974694612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.428579843
Short name T221
Test name
Test status
Simulation time 1278074161 ps
CPU time 75.21 seconds
Started Sep 01 09:19:36 AM UTC 24
Finished Sep 01 09:20:54 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428579843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.428579843
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.1223405607
Short name T215
Test name
Test status
Simulation time 4368455479 ps
CPU time 51.57 seconds
Started Sep 01 09:19:41 AM UTC 24
Finished Sep 01 09:20:34 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223405607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1223405607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.1673324347
Short name T261
Test name
Test status
Simulation time 6651811964 ps
CPU time 256.97 seconds
Started Sep 01 09:19:40 AM UTC 24
Finished Sep 01 09:24:01 AM UTC 24
Peak memory 704792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673324347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1673324347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_error.994727886
Short name T245
Test name
Test status
Simulation time 8215134234 ps
CPU time 202.65 seconds
Started Sep 01 09:19:46 AM UTC 24
Finished Sep 01 09:23:12 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994727886 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.994727886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_long_msg.2248619552
Short name T225
Test name
Test status
Simulation time 3467121948 ps
CPU time 83.12 seconds
Started Sep 01 09:19:36 AM UTC 24
Finished Sep 01 09:21:02 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248619552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2248619552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_smoke.3203491594
Short name T208
Test name
Test status
Simulation time 1650266473 ps
CPU time 7.83 seconds
Started Sep 01 09:19:29 AM UTC 24
Finished Sep 01 09:19:39 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203491594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3203491594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_stress_all.3433692785
Short name T401
Test name
Test status
Simulation time 45706059013 ps
CPU time 841.37 seconds
Started Sep 01 09:19:52 AM UTC 24
Finished Sep 01 09:34:03 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433692785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3433692785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.1691061227
Short name T84
Test name
Test status
Simulation time 848839199 ps
CPU time 29.93 seconds
Started Sep 01 09:19:49 AM UTC 24
Finished Sep 01 09:20:21 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691061227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1691061227
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_alert_test.1089632909
Short name T216
Test name
Test status
Simulation time 21840138 ps
CPU time 0.87 seconds
Started Sep 01 09:20:34 AM UTC 24
Finished Sep 01 09:20:36 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089632909 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1089632909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.2305476839
Short name T233
Test name
Test status
Simulation time 1784368161 ps
CPU time 112.95 seconds
Started Sep 01 09:19:56 AM UTC 24
Finished Sep 01 09:21:51 AM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305476839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2305476839
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.1147334072
Short name T150
Test name
Test status
Simulation time 891310331 ps
CPU time 30.8 seconds
Started Sep 01 09:20:07 AM UTC 24
Finished Sep 01 09:20:39 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147334072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1147334072
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.3097280818
Short name T472
Test name
Test status
Simulation time 22049877314 ps
CPU time 1172.12 seconds
Started Sep 01 09:20:03 AM UTC 24
Finished Sep 01 09:39:48 AM UTC 24
Peak memory 760352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097280818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3097280818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_error.3484192002
Short name T260
Test name
Test status
Simulation time 3247129034 ps
CPU time 218.57 seconds
Started Sep 01 09:20:17 AM UTC 24
Finished Sep 01 09:23:59 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484192002 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3484192002
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_long_msg.3434739493
Short name T239
Test name
Test status
Simulation time 34795513493 ps
CPU time 146.73 seconds
Started Sep 01 09:19:55 AM UTC 24
Finished Sep 01 09:22:24 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434739493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3434739493
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_smoke.2526189156
Short name T211
Test name
Test status
Simulation time 223772670 ps
CPU time 1.8 seconds
Started Sep 01 09:19:53 AM UTC 24
Finished Sep 01 09:19:56 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526189156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2526189156
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2161826180
Short name T526
Test name
Test status
Simulation time 496560372427 ps
CPU time 3126.68 seconds
Started Sep 01 09:20:22 AM UTC 24
Finished Sep 01 10:13:01 AM UTC 24
Peak memory 776388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161826180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2161826180
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.207394680
Short name T117
Test name
Test status
Simulation time 23276054158 ps
CPU time 119.77 seconds
Started Sep 01 09:20:22 AM UTC 24
Finished Sep 01 09:22:24 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207394680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.207394680
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_alert_test.1050249216
Short name T224
Test name
Test status
Simulation time 36377051 ps
CPU time 0.82 seconds
Started Sep 01 09:20:56 AM UTC 24
Finished Sep 01 09:20:57 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050249216 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1050249216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.1163141933
Short name T43
Test name
Test status
Simulation time 464273318 ps
CPU time 18.5 seconds
Started Sep 01 09:20:36 AM UTC 24
Finished Sep 01 09:20:56 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163141933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1163141933
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.1420219663
Short name T222
Test name
Test status
Simulation time 372981775 ps
CPU time 13.66 seconds
Started Sep 01 09:20:40 AM UTC 24
Finished Sep 01 09:20:55 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420219663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1420219663
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.1814142012
Short name T350
Test name
Test status
Simulation time 6177088266 ps
CPU time 579.5 seconds
Started Sep 01 09:20:37 AM UTC 24
Finished Sep 01 09:30:24 AM UTC 24
Peak memory 530704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814142012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1814142012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_error.2288581899
Short name T229
Test name
Test status
Simulation time 2905228172 ps
CPU time 45.03 seconds
Started Sep 01 09:20:44 AM UTC 24
Finished Sep 01 09:21:31 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288581899 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2288581899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_long_msg.3614720131
Short name T248
Test name
Test status
Simulation time 32934961514 ps
CPU time 159.78 seconds
Started Sep 01 09:20:36 AM UTC 24
Finished Sep 01 09:23:19 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614720131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3614720131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_smoke.264616929
Short name T218
Test name
Test status
Simulation time 468556540 ps
CPU time 8.41 seconds
Started Sep 01 09:20:34 AM UTC 24
Finished Sep 01 09:20:43 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264616929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.264616929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_stress_all.502599749
Short name T78
Test name
Test status
Simulation time 100005012662 ps
CPU time 1429.41 seconds
Started Sep 01 09:20:55 AM UTC 24
Finished Sep 01 09:45:02 AM UTC 24
Peak memory 690660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502599749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.502599749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.100349034
Short name T237
Test name
Test status
Simulation time 22135966535 ps
CPU time 88.44 seconds
Started Sep 01 09:20:44 AM UTC 24
Finished Sep 01 09:22:15 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100349034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.100349034
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_alert_test.1035301134
Short name T228
Test name
Test status
Simulation time 40411825 ps
CPU time 0.88 seconds
Started Sep 01 09:21:21 AM UTC 24
Finished Sep 01 09:21:23 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035301134 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1035301134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.4219728950
Short name T234
Test name
Test status
Simulation time 1281227364 ps
CPU time 58.29 seconds
Started Sep 01 09:20:57 AM UTC 24
Finished Sep 01 09:21:57 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219728950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4219728950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.1262275855
Short name T226
Test name
Test status
Simulation time 2348773707 ps
CPU time 8.96 seconds
Started Sep 01 09:21:02 AM UTC 24
Finished Sep 01 09:21:12 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262275855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1262275855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.3712928548
Short name T307
Test name
Test status
Simulation time 2039160287 ps
CPU time 374.25 seconds
Started Sep 01 09:20:58 AM UTC 24
Finished Sep 01 09:27:17 AM UTC 24
Peak memory 430244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712928548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3712928548
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_error.2823798429
Short name T253
Test name
Test status
Simulation time 66752880475 ps
CPU time 141.9 seconds
Started Sep 01 09:21:08 AM UTC 24
Finished Sep 01 09:23:32 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823798429 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2823798429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_long_msg.4191323961
Short name T249
Test name
Test status
Simulation time 9026325068 ps
CPU time 142.16 seconds
Started Sep 01 09:20:56 AM UTC 24
Finished Sep 01 09:23:20 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191323961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4191323961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_smoke.491495473
Short name T145
Test name
Test status
Simulation time 4851026051 ps
CPU time 20.85 seconds
Started Sep 01 09:20:56 AM UTC 24
Finished Sep 01 09:21:18 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491495473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.491495473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2981373556
Short name T81
Test name
Test status
Simulation time 253862698014 ps
CPU time 2601.08 seconds
Started Sep 01 09:21:19 AM UTC 24
Finished Sep 01 10:05:09 AM UTC 24
Peak memory 778476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981373556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2981373556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.2792817732
Short name T116
Test name
Test status
Simulation time 21655560235 ps
CPU time 50.44 seconds
Started Sep 01 09:21:14 AM UTC 24
Finished Sep 01 09:22:06 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792817732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2792817732
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_alert_test.102106384
Short name T236
Test name
Test status
Simulation time 44457037 ps
CPU time 0.87 seconds
Started Sep 01 09:22:04 AM UTC 24
Finished Sep 01 09:22:06 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102106384 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.102106384
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.1991250370
Short name T241
Test name
Test status
Simulation time 903431178 ps
CPU time 64.97 seconds
Started Sep 01 09:21:37 AM UTC 24
Finished Sep 01 09:22:44 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991250370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1991250370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.1977202649
Short name T154
Test name
Test status
Simulation time 1240206342 ps
CPU time 70.93 seconds
Started Sep 01 09:21:45 AM UTC 24
Finished Sep 01 09:22:57 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977202649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1977202649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.1168138916
Short name T389
Test name
Test status
Simulation time 3728794429 ps
CPU time 684.65 seconds
Started Sep 01 09:21:40 AM UTC 24
Finished Sep 01 09:33:12 AM UTC 24
Peak memory 735716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168138916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1168138916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_error.2849812682
Short name T246
Test name
Test status
Simulation time 12374536322 ps
CPU time 79.77 seconds
Started Sep 01 09:21:53 AM UTC 24
Finished Sep 01 09:23:15 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849812682 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2849812682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_long_msg.513874058
Short name T235
Test name
Test status
Simulation time 5476527978 ps
CPU time 29.72 seconds
Started Sep 01 09:21:32 AM UTC 24
Finished Sep 01 09:22:04 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513874058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.513874058
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_smoke.2106340875
Short name T231
Test name
Test status
Simulation time 220689838 ps
CPU time 14.28 seconds
Started Sep 01 09:21:24 AM UTC 24
Finished Sep 01 09:21:39 AM UTC 24
Peak memory 207368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106340875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2106340875
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_stress_all.742327896
Short name T118
Test name
Test status
Simulation time 8586754713 ps
CPU time 45.56 seconds
Started Sep 01 09:21:58 AM UTC 24
Finished Sep 01 09:22:45 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742327896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.742327896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.3982152484
Short name T258
Test name
Test status
Simulation time 5819265737 ps
CPU time 118.16 seconds
Started Sep 01 09:21:53 AM UTC 24
Finished Sep 01 09:23:54 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982152484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3982152484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_alert_test.1432160598
Short name T52
Test name
Test status
Simulation time 34269152 ps
CPU time 0.76 seconds
Started Sep 01 09:14:48 AM UTC 24
Finished Sep 01 09:14:49 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432160598 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1432160598
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.3254681949
Short name T35
Test name
Test status
Simulation time 1346995872 ps
CPU time 87.21 seconds
Started Sep 01 09:14:08 AM UTC 24
Finished Sep 01 09:15:38 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254681949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3254681949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.463609946
Short name T18
Test name
Test status
Simulation time 10372491433 ps
CPU time 62.37 seconds
Started Sep 01 09:14:19 AM UTC 24
Finished Sep 01 09:15:23 AM UTC 24
Peak memory 207532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463609946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.463609946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.1152439680
Short name T121
Test name
Test status
Simulation time 8412914592 ps
CPU time 128.98 seconds
Started Sep 01 09:14:15 AM UTC 24
Finished Sep 01 09:16:26 AM UTC 24
Peak memory 387332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152439680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1152439680
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_long_msg.3509291398
Short name T82
Test name
Test status
Simulation time 9905343309 ps
CPU time 45.31 seconds
Started Sep 01 09:14:07 AM UTC 24
Finished Sep 01 09:14:54 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509291398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3509291398
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.2823805599
Short name T54
Test name
Test status
Simulation time 121932617 ps
CPU time 1.34 seconds
Started Sep 01 09:14:44 AM UTC 24
Finished Sep 01 09:14:47 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823805599 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2823805599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_smoke.1939174242
Short name T8
Test name
Test status
Simulation time 684792845 ps
CPU time 6.9 seconds
Started Sep 01 09:14:06 AM UTC 24
Finished Sep 01 09:14:14 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939174242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1939174242
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_stress_all.1160030534
Short name T61
Test name
Test status
Simulation time 27702493259 ps
CPU time 378.81 seconds
Started Sep 01 09:14:41 AM UTC 24
Finished Sep 01 09:21:05 AM UTC 24
Peak memory 215700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160030534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1160030534
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.4192084396
Short name T63
Test name
Test status
Simulation time 14578309918 ps
CPU time 532.91 seconds
Started Sep 01 09:14:44 AM UTC 24
Finished Sep 01 09:23:44 AM UTC 24
Peak memory 639388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41920843
96 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.4192084396
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.1901713823
Short name T51
Test name
Test status
Simulation time 4710359272 ps
CPU time 44.07 seconds
Started Sep 01 09:14:33 AM UTC 24
Finished Sep 01 09:15:19 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901713823 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1901713823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.4007805243
Short name T37
Test name
Test status
Simulation time 17790765248 ps
CPU time 64.25 seconds
Started Sep 01 09:14:38 AM UTC 24
Finished Sep 01 09:15:44 AM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007805243 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.4007805243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.2234630752
Short name T168
Test name
Test status
Simulation time 2249906508 ps
CPU time 79.14 seconds
Started Sep 01 09:14:39 AM UTC 24
Finished Sep 01 09:16:00 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234630752 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2234630752
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.3992086801
Short name T284
Test name
Test status
Simulation time 300933524775 ps
CPU time 658.9 seconds
Started Sep 01 09:14:27 AM UTC 24
Finished Sep 01 09:25:34 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992086801 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3992086801
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1152555043
Short name T501
Test name
Test status
Simulation time 35008447537 ps
CPU time 2095.5 seconds
Started Sep 01 09:14:29 AM UTC 24
Finished Sep 01 09:49:51 AM UTC 24
Peak memory 227384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152555043 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1152555043
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.4128715159
Short name T521
Test name
Test status
Simulation time 226521663945 ps
CPU time 3176.84 seconds
Started Sep 01 09:14:30 AM UTC 24
Finished Sep 01 10:08:04 AM UTC 24
Peak memory 221248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128715159 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.4128715159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.2722127966
Short name T177
Test name
Test status
Simulation time 39075609537 ps
CPU time 156.79 seconds
Started Sep 01 09:14:26 AM UTC 24
Finished Sep 01 09:17:05 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722127966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2722127966
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_alert_test.4291746393
Short name T242
Test name
Test status
Simulation time 12250557 ps
CPU time 0.77 seconds
Started Sep 01 09:22:46 AM UTC 24
Finished Sep 01 09:22:48 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291746393 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4291746393
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.621221545
Short name T263
Test name
Test status
Simulation time 1629352857 ps
CPU time 106.76 seconds
Started Sep 01 09:22:16 AM UTC 24
Finished Sep 01 09:24:05 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621221545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.621221545
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3140990597
Short name T243
Test name
Test status
Simulation time 976316923 ps
CPU time 28.12 seconds
Started Sep 01 09:22:25 AM UTC 24
Finished Sep 01 09:22:54 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140990597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3140990597
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2892308265
Short name T450
Test name
Test status
Simulation time 4694317104 ps
CPU time 930.15 seconds
Started Sep 01 09:22:17 AM UTC 24
Finished Sep 01 09:37:58 AM UTC 24
Peak memory 788908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892308265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2892308265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_error.181258646
Short name T259
Test name
Test status
Simulation time 4604523896 ps
CPU time 86.82 seconds
Started Sep 01 09:22:27 AM UTC 24
Finished Sep 01 09:23:56 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181258646 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.181258646
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_long_msg.2851409069
Short name T282
Test name
Test status
Simulation time 54634966836 ps
CPU time 201.61 seconds
Started Sep 01 09:22:07 AM UTC 24
Finished Sep 01 09:25:32 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851409069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2851409069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_smoke.2644576812
Short name T238
Test name
Test status
Simulation time 540609845 ps
CPU time 8.28 seconds
Started Sep 01 09:22:07 AM UTC 24
Finished Sep 01 09:22:17 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644576812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2644576812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_stress_all.3979639458
Short name T530
Test name
Test status
Simulation time 357266242224 ps
CPU time 3957.8 seconds
Started Sep 01 09:22:45 AM UTC 24
Finished Sep 01 10:29:24 AM UTC 24
Peak memory 819316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979639458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3979639458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.4277855295
Short name T120
Test name
Test status
Simulation time 44148735748 ps
CPU time 144.91 seconds
Started Sep 01 09:22:35 AM UTC 24
Finished Sep 01 09:25:03 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277855295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4277855295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_alert_test.676914432
Short name T250
Test name
Test status
Simulation time 15163994 ps
CPU time 0.94 seconds
Started Sep 01 09:23:20 AM UTC 24
Finished Sep 01 09:23:22 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676914432 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.676914432
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.4207245652
Short name T262
Test name
Test status
Simulation time 2149015057 ps
CPU time 64.92 seconds
Started Sep 01 09:22:58 AM UTC 24
Finished Sep 01 09:24:04 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207245652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4207245652
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.3619164809
Short name T152
Test name
Test status
Simulation time 1293763954 ps
CPU time 27.54 seconds
Started Sep 01 09:23:06 AM UTC 24
Finished Sep 01 09:23:35 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619164809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3619164809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.2750618809
Short name T272
Test name
Test status
Simulation time 992285570 ps
CPU time 99.66 seconds
Started Sep 01 09:22:59 AM UTC 24
Finished Sep 01 09:24:41 AM UTC 24
Peak memory 475348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750618809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2750618809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_error.3489887902
Short name T286
Test name
Test status
Simulation time 2488295189 ps
CPU time 151.3 seconds
Started Sep 01 09:23:14 AM UTC 24
Finished Sep 01 09:25:48 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489887902 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3489887902
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_long_msg.888544002
Short name T251
Test name
Test status
Simulation time 16731390891 ps
CPU time 31.33 seconds
Started Sep 01 09:22:56 AM UTC 24
Finished Sep 01 09:23:28 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888544002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.888544002
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_smoke.189846433
Short name T244
Test name
Test status
Simulation time 369622363 ps
CPU time 6.49 seconds
Started Sep 01 09:22:49 AM UTC 24
Finished Sep 01 09:22:57 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189846433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.189846433
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_stress_all.1115287085
Short name T80
Test name
Test status
Simulation time 82041779193 ps
CPU time 2125.98 seconds
Started Sep 01 09:23:18 AM UTC 24
Finished Sep 01 09:59:08 AM UTC 24
Peak memory 756208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115287085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1115287085
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.2136060410
Short name T85
Test name
Test status
Simulation time 10115153140 ps
CPU time 139.91 seconds
Started Sep 01 09:23:16 AM UTC 24
Finished Sep 01 09:25:39 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136060410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2136060410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_alert_test.1000634462
Short name T256
Test name
Test status
Simulation time 53887775 ps
CPU time 0.9 seconds
Started Sep 01 09:23:47 AM UTC 24
Finished Sep 01 09:23:49 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000634462 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1000634462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.1098780044
Short name T269
Test name
Test status
Simulation time 689839013 ps
CPU time 49.34 seconds
Started Sep 01 09:23:29 AM UTC 24
Finished Sep 01 09:24:20 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098780044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1098780044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.835233563
Short name T223
Test name
Test status
Simulation time 1091394527 ps
CPU time 14.72 seconds
Started Sep 01 09:23:34 AM UTC 24
Finished Sep 01 09:23:50 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835233563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.835233563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.407628350
Short name T435
Test name
Test status
Simulation time 13655790125 ps
CPU time 807.94 seconds
Started Sep 01 09:23:29 AM UTC 24
Finished Sep 01 09:37:06 AM UTC 24
Peak memory 739548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407628350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.407628350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_error.61442698
Short name T271
Test name
Test status
Simulation time 14548305477 ps
CPU time 59.06 seconds
Started Sep 01 09:23:37 AM UTC 24
Finished Sep 01 09:24:38 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61442698 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.61442698
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_long_msg.3064206645
Short name T255
Test name
Test status
Simulation time 2699320840 ps
CPU time 13.14 seconds
Started Sep 01 09:23:23 AM UTC 24
Finished Sep 01 09:23:37 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064206645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3064206645
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_smoke.3498197585
Short name T252
Test name
Test status
Simulation time 1295619436 ps
CPU time 5.86 seconds
Started Sep 01 09:23:22 AM UTC 24
Finished Sep 01 09:23:29 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498197585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3498197585
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_stress_all.2938268880
Short name T527
Test name
Test status
Simulation time 218904784728 ps
CPU time 3372.33 seconds
Started Sep 01 09:23:39 AM UTC 24
Finished Sep 01 10:20:28 AM UTC 24
Peak memory 784756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938268880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2938268880
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.3196988666
Short name T119
Test name
Test status
Simulation time 3469316109 ps
CPU time 77.81 seconds
Started Sep 01 09:23:37 AM UTC 24
Finished Sep 01 09:24:57 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196988666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3196988666
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_alert_test.1815805203
Short name T266
Test name
Test status
Simulation time 38608267 ps
CPU time 0.76 seconds
Started Sep 01 09:24:09 AM UTC 24
Finished Sep 01 09:24:11 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815805203 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1815805203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.714197681
Short name T291
Test name
Test status
Simulation time 1713526918 ps
CPU time 132.33 seconds
Started Sep 01 09:23:53 AM UTC 24
Finished Sep 01 09:26:08 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714197681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.714197681
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.1824117522
Short name T268
Test name
Test status
Simulation time 1152765208 ps
CPU time 18.86 seconds
Started Sep 01 09:23:57 AM UTC 24
Finished Sep 01 09:24:17 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824117522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1824117522
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.2378042079
Short name T313
Test name
Test status
Simulation time 12464652510 ps
CPU time 223.42 seconds
Started Sep 01 09:23:55 AM UTC 24
Finished Sep 01 09:27:41 AM UTC 24
Peak memory 712980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378042079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2378042079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_error.3585582254
Short name T275
Test name
Test status
Simulation time 718082667 ps
CPU time 52.02 seconds
Started Sep 01 09:24:01 AM UTC 24
Finished Sep 01 09:24:55 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585582254 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3585582254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_long_msg.2852827044
Short name T328
Test name
Test status
Simulation time 3550904075 ps
CPU time 271.9 seconds
Started Sep 01 09:23:51 AM UTC 24
Finished Sep 01 09:28:27 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852827044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2852827044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_smoke.3514954700
Short name T257
Test name
Test status
Simulation time 17119878 ps
CPU time 1.33 seconds
Started Sep 01 09:23:50 AM UTC 24
Finished Sep 01 09:23:52 AM UTC 24
Peak memory 206192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514954700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3514954700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3186132583
Short name T292
Test name
Test status
Simulation time 7069357973 ps
CPU time 122.97 seconds
Started Sep 01 09:24:03 AM UTC 24
Finished Sep 01 09:26:08 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186132583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3186132583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_alert_test.1698922581
Short name T273
Test name
Test status
Simulation time 18446418 ps
CPU time 0.88 seconds
Started Sep 01 09:24:42 AM UTC 24
Finished Sep 01 09:24:44 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698922581 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1698922581
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.576598474
Short name T270
Test name
Test status
Simulation time 305587436 ps
CPU time 22 seconds
Started Sep 01 09:24:12 AM UTC 24
Finished Sep 01 09:24:36 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576598474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.576598474
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.305490104
Short name T153
Test name
Test status
Simulation time 1019411414 ps
CPU time 61.62 seconds
Started Sep 01 09:24:17 AM UTC 24
Finished Sep 01 09:25:21 AM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305490104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.305490104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.1254890105
Short name T496
Test name
Test status
Simulation time 23173919710 ps
CPU time 1181.01 seconds
Started Sep 01 09:24:16 AM UTC 24
Finished Sep 01 09:44:11 AM UTC 24
Peak memory 790804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254890105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1254890105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_error.3644042086
Short name T304
Test name
Test status
Simulation time 9327806508 ps
CPU time 164.62 seconds
Started Sep 01 09:24:21 AM UTC 24
Finished Sep 01 09:27:09 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644042086 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3644042086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_long_msg.633682369
Short name T294
Test name
Test status
Simulation time 5785713829 ps
CPU time 117.7 seconds
Started Sep 01 09:24:12 AM UTC 24
Finished Sep 01 09:26:13 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633682369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.633682369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_smoke.3792165376
Short name T267
Test name
Test status
Simulation time 188068754 ps
CPU time 5.78 seconds
Started Sep 01 09:24:09 AM UTC 24
Finished Sep 01 09:24:16 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792165376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3792165376
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_stress_all.1178928791
Short name T523
Test name
Test status
Simulation time 38336726385 ps
CPU time 2628.28 seconds
Started Sep 01 09:24:40 AM UTC 24
Finished Sep 01 10:08:55 AM UTC 24
Peak memory 784688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178928791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1178928791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.971296393
Short name T297
Test name
Test status
Simulation time 26335495419 ps
CPU time 112.12 seconds
Started Sep 01 09:24:37 AM UTC 24
Finished Sep 01 09:26:32 AM UTC 24
Peak memory 207564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971296393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.971296393
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_alert_test.2529529031
Short name T278
Test name
Test status
Simulation time 15436027 ps
CPU time 0.87 seconds
Started Sep 01 09:25:13 AM UTC 24
Finished Sep 01 09:25:15 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529529031 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2529529031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.2933791338
Short name T289
Test name
Test status
Simulation time 910591576 ps
CPU time 61.58 seconds
Started Sep 01 09:24:55 AM UTC 24
Finished Sep 01 09:25:58 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933791338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2933791338
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.2814584665
Short name T151
Test name
Test status
Simulation time 182553985 ps
CPU time 10.32 seconds
Started Sep 01 09:24:58 AM UTC 24
Finished Sep 01 09:25:10 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814584665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2814584665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.3854498663
Short name T359
Test name
Test status
Simulation time 7619128937 ps
CPU time 354.05 seconds
Started Sep 01 09:24:56 AM UTC 24
Finished Sep 01 09:30:54 AM UTC 24
Peak memory 686360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854498663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3854498663
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_error.1313001942
Short name T316
Test name
Test status
Simulation time 8392567621 ps
CPU time 158.97 seconds
Started Sep 01 09:25:05 AM UTC 24
Finished Sep 01 09:27:47 AM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313001942 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1313001942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3207704814
Short name T299
Test name
Test status
Simulation time 6863151575 ps
CPU time 114.81 seconds
Started Sep 01 09:24:45 AM UTC 24
Finished Sep 01 09:26:43 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207704814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3207704814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_smoke.834422492
Short name T274
Test name
Test status
Simulation time 581578761 ps
CPU time 7.27 seconds
Started Sep 01 09:24:45 AM UTC 24
Finished Sep 01 09:24:54 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834422492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.834422492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_stress_all.857882585
Short name T88
Test name
Test status
Simulation time 31388279147 ps
CPU time 477.55 seconds
Started Sep 01 09:25:10 AM UTC 24
Finished Sep 01 09:33:14 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857882585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.857882585
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.3506543687
Short name T305
Test name
Test status
Simulation time 39535106760 ps
CPU time 119.8 seconds
Started Sep 01 09:25:07 AM UTC 24
Finished Sep 01 09:27:09 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506543687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3506543687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_alert_test.1364701367
Short name T285
Test name
Test status
Simulation time 19235521 ps
CPU time 0.87 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:25:43 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364701367 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1364701367
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.3859810115
Short name T296
Test name
Test status
Simulation time 972525007 ps
CPU time 56.69 seconds
Started Sep 01 09:25:29 AM UTC 24
Finished Sep 01 09:26:27 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859810115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3859810115
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.946352945
Short name T287
Test name
Test status
Simulation time 1778389257 ps
CPU time 6.09 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:25:48 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946352945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.946352945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.2753833426
Short name T461
Test name
Test status
Simulation time 6890916090 ps
CPU time 785.54 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:38:55 AM UTC 24
Peak memory 735576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753833426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2753833426
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_error.4076535625
Short name T314
Test name
Test status
Simulation time 2287390290 ps
CPU time 121.11 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:27:45 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076535625 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4076535625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_long_msg.2374614506
Short name T280
Test name
Test status
Simulation time 1269256575 ps
CPU time 8.07 seconds
Started Sep 01 09:25:22 AM UTC 24
Finished Sep 01 09:25:31 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374614506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2374614506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_smoke.1192762964
Short name T281
Test name
Test status
Simulation time 259196208 ps
CPU time 14.47 seconds
Started Sep 01 09:25:16 AM UTC 24
Finished Sep 01 09:25:32 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192762964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1192762964
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_stress_all.1028527689
Short name T321
Test name
Test status
Simulation time 24011783356 ps
CPU time 142.01 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:28:06 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028527689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1028527689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.4045249583
Short name T318
Test name
Test status
Simulation time 7065658824 ps
CPU time 130.05 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:27:54 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045249583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4045249583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_alert_test.240954115
Short name T293
Test name
Test status
Simulation time 38189342 ps
CPU time 0.82 seconds
Started Sep 01 09:26:10 AM UTC 24
Finished Sep 01 09:26:12 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240954115 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.240954115
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.1300495454
Short name T302
Test name
Test status
Simulation time 13122018219 ps
CPU time 76.52 seconds
Started Sep 01 09:25:45 AM UTC 24
Finished Sep 01 09:27:04 AM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300495454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1300495454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.979832022
Short name T290
Test name
Test status
Simulation time 299370349 ps
CPU time 9.95 seconds
Started Sep 01 09:25:50 AM UTC 24
Finished Sep 01 09:26:02 AM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979832022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.979832022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.2609789766
Short name T495
Test name
Test status
Simulation time 22516016185 ps
CPU time 1082.88 seconds
Started Sep 01 09:25:50 AM UTC 24
Finished Sep 01 09:44:05 AM UTC 24
Peak memory 688476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609789766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2609789766
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_error.3139236023
Short name T320
Test name
Test status
Simulation time 6302937098 ps
CPU time 121.3 seconds
Started Sep 01 09:25:55 AM UTC 24
Finished Sep 01 09:27:59 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139236023 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3139236023
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_long_msg.2274323112
Short name T311
Test name
Test status
Simulation time 8430980986 ps
CPU time 108.2 seconds
Started Sep 01 09:25:45 AM UTC 24
Finished Sep 01 09:27:36 AM UTC 24
Peak memory 223708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274323112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2274323112
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_smoke.4106995202
Short name T288
Test name
Test status
Simulation time 1041250466 ps
CPU time 11.47 seconds
Started Sep 01 09:25:41 AM UTC 24
Finished Sep 01 09:25:54 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106995202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4106995202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_stress_all.785997113
Short name T315
Test name
Test status
Simulation time 7894141593 ps
CPU time 102.27 seconds
Started Sep 01 09:26:02 AM UTC 24
Finished Sep 01 09:27:47 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785997113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.785997113
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.866614549
Short name T325
Test name
Test status
Simulation time 7126069847 ps
CPU time 132.76 seconds
Started Sep 01 09:25:59 AM UTC 24
Finished Sep 01 09:28:14 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866614549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.866614549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_alert_test.343682561
Short name T300
Test name
Test status
Simulation time 47662166 ps
CPU time 0.9 seconds
Started Sep 01 09:26:42 AM UTC 24
Finished Sep 01 09:26:44 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343682561 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.343682561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.3591307603
Short name T319
Test name
Test status
Simulation time 5697782108 ps
CPU time 99.63 seconds
Started Sep 01 09:26:14 AM UTC 24
Finished Sep 01 09:27:56 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591307603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3591307603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.1417723317
Short name T158
Test name
Test status
Simulation time 3080580710 ps
CPU time 51.32 seconds
Started Sep 01 09:26:29 AM UTC 24
Finished Sep 01 09:27:22 AM UTC 24
Peak memory 215880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417723317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1417723317
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.3044393111
Short name T391
Test name
Test status
Simulation time 36568602573 ps
CPU time 419.89 seconds
Started Sep 01 09:26:17 AM UTC 24
Finished Sep 01 09:33:22 AM UTC 24
Peak memory 676256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044393111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3044393111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_error.835731350
Short name T312
Test name
Test status
Simulation time 3586238479 ps
CPU time 60.58 seconds
Started Sep 01 09:26:36 AM UTC 24
Finished Sep 01 09:27:39 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835731350 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.835731350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_long_msg.2944691987
Short name T330
Test name
Test status
Simulation time 1930999241 ps
CPU time 139.74 seconds
Started Sep 01 09:26:12 AM UTC 24
Finished Sep 01 09:28:35 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944691987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2944691987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_smoke.1681945630
Short name T295
Test name
Test status
Simulation time 1470752052 ps
CPU time 5.34 seconds
Started Sep 01 09:26:10 AM UTC 24
Finished Sep 01 09:26:17 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681945630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1681945630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_stress_all.1569535224
Short name T343
Test name
Test status
Simulation time 10594415612 ps
CPU time 184.29 seconds
Started Sep 01 09:26:42 AM UTC 24
Finished Sep 01 09:29:49 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569535224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1569535224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.132869763
Short name T303
Test name
Test status
Simulation time 1556279479 ps
CPU time 27.47 seconds
Started Sep 01 09:26:36 AM UTC 24
Finished Sep 01 09:27:05 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132869763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.132869763
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_alert_test.3981605237
Short name T308
Test name
Test status
Simulation time 23579213 ps
CPU time 0.85 seconds
Started Sep 01 09:27:19 AM UTC 24
Finished Sep 01 09:27:20 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981605237 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3981605237
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.2647866841
Short name T306
Test name
Test status
Simulation time 512607096 ps
CPU time 20.48 seconds
Started Sep 01 09:26:50 AM UTC 24
Finished Sep 01 09:27:12 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647866841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2647866841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.3494027583
Short name T326
Test name
Test status
Simulation time 7676844192 ps
CPU time 72.93 seconds
Started Sep 01 09:27:06 AM UTC 24
Finished Sep 01 09:28:21 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494027583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3494027583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.4000438700
Short name T327
Test name
Test status
Simulation time 620277300 ps
CPU time 79.32 seconds
Started Sep 01 09:27:06 AM UTC 24
Finished Sep 01 09:28:27 AM UTC 24
Peak memory 415968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000438700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4000438700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_error.818619692
Short name T348
Test name
Test status
Simulation time 13486055778 ps
CPU time 177.57 seconds
Started Sep 01 09:27:10 AM UTC 24
Finished Sep 01 09:30:11 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818619692 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.818619692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_long_msg.2673794882
Short name T356
Test name
Test status
Simulation time 44081988075 ps
CPU time 234.39 seconds
Started Sep 01 09:26:45 AM UTC 24
Finished Sep 01 09:30:43 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673794882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2673794882
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_smoke.2927549591
Short name T301
Test name
Test status
Simulation time 62136120 ps
CPU time 4.6 seconds
Started Sep 01 09:26:44 AM UTC 24
Finished Sep 01 09:26:49 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927549591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2927549591
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_stress_all.2823056459
Short name T159
Test name
Test status
Simulation time 1100046258 ps
CPU time 14.94 seconds
Started Sep 01 09:27:13 AM UTC 24
Finished Sep 01 09:27:29 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823056459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2823056459
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.1121213877
Short name T309
Test name
Test status
Simulation time 1690257553 ps
CPU time 18.38 seconds
Started Sep 01 09:27:11 AM UTC 24
Finished Sep 01 09:27:30 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121213877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1121213877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_alert_test.712351324
Short name T166
Test name
Test status
Simulation time 21677929 ps
CPU time 0.86 seconds
Started Sep 01 09:15:22 AM UTC 24
Finished Sep 01 09:15:24 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712351324 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.712351324
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3024197251
Short name T11
Test name
Test status
Simulation time 291227495 ps
CPU time 21.26 seconds
Started Sep 01 09:14:50 AM UTC 24
Finished Sep 01 09:15:13 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024197251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3024197251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.3573106932
Short name T12
Test name
Test status
Simulation time 602162270 ps
CPU time 20.66 seconds
Started Sep 01 09:14:53 AM UTC 24
Finished Sep 01 09:15:15 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573106932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3573106932
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.3376306502
Short name T141
Test name
Test status
Simulation time 2208903243 ps
CPU time 337.84 seconds
Started Sep 01 09:14:51 AM UTC 24
Finished Sep 01 09:20:34 AM UTC 24
Peak memory 721124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376306502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3376306502
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_error.1849780983
Short name T83
Test name
Test status
Simulation time 170110478 ps
CPU time 12.22 seconds
Started Sep 01 09:14:56 AM UTC 24
Finished Sep 01 09:15:10 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849780983 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1849780983
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2524447277
Short name T178
Test name
Test status
Simulation time 10693960158 ps
CPU time 138.06 seconds
Started Sep 01 09:14:49 AM UTC 24
Finished Sep 01 09:17:10 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524447277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2524447277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.1350136943
Short name T55
Test name
Test status
Simulation time 71441294 ps
CPU time 1.34 seconds
Started Sep 01 09:15:21 AM UTC 24
Finished Sep 01 09:15:23 AM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350136943 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1350136943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_smoke.186187373
Short name T10
Test name
Test status
Simulation time 790951090 ps
CPU time 14.4 seconds
Started Sep 01 09:14:48 AM UTC 24
Finished Sep 01 09:15:03 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186187373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.186187373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_stress_all.3317881010
Short name T77
Test name
Test status
Simulation time 270259945505 ps
CPU time 1552.77 seconds
Started Sep 01 09:15:16 AM UTC 24
Finished Sep 01 09:41:26 AM UTC 24
Peak memory 710944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317881010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3317881010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.4152495663
Short name T172
Test name
Test status
Simulation time 1659225173 ps
CPU time 70.2 seconds
Started Sep 01 09:15:11 AM UTC 24
Finished Sep 01 09:16:23 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152495663 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.4152495663
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.714462758
Short name T176
Test name
Test status
Simulation time 14900457738 ps
CPU time 80.46 seconds
Started Sep 01 09:15:14 AM UTC 24
Finished Sep 01 09:16:36 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714462758 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.714462758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.2737710408
Short name T175
Test name
Test status
Simulation time 2267667981 ps
CPU time 74.55 seconds
Started Sep 01 09:15:16 AM UTC 24
Finished Sep 01 09:16:32 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737710408 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2737710408
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.3951004106
Short name T144
Test name
Test status
Simulation time 145401340344 ps
CPU time 768.46 seconds
Started Sep 01 09:15:04 AM UTC 24
Finished Sep 01 09:28:03 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951004106 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3951004106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.1129969117
Short name T511
Test name
Test status
Simulation time 41865800150 ps
CPU time 2515.25 seconds
Started Sep 01 09:15:07 AM UTC 24
Finished Sep 01 09:57:32 AM UTC 24
Peak memory 221440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129969117 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1129969117
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.4248949380
Short name T519
Test name
Test status
Simulation time 530384861660 ps
CPU time 3049.75 seconds
Started Sep 01 09:15:10 AM UTC 24
Finished Sep 01 10:06:37 AM UTC 24
Peak memory 219504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248949380 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4248949380
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.3206572917
Short name T31
Test name
Test status
Simulation time 9696513740 ps
CPU time 36.52 seconds
Started Sep 01 09:14:57 AM UTC 24
Finished Sep 01 09:15:35 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206572917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3206572917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_alert_test.1695084670
Short name T317
Test name
Test status
Simulation time 34233984 ps
CPU time 0.89 seconds
Started Sep 01 09:27:46 AM UTC 24
Finished Sep 01 09:27:48 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695084670 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1695084670
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3709940066
Short name T32
Test name
Test status
Simulation time 531783148 ps
CPU time 36.49 seconds
Started Sep 01 09:27:30 AM UTC 24
Finished Sep 01 09:28:08 AM UTC 24
Peak memory 215596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709940066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3709940066
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.3629962140
Short name T329
Test name
Test status
Simulation time 3117234571 ps
CPU time 55.04 seconds
Started Sep 01 09:27:35 AM UTC 24
Finished Sep 01 09:28:33 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629962140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3629962140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.4008419552
Short name T480
Test name
Test status
Simulation time 7793918067 ps
CPU time 805.77 seconds
Started Sep 01 09:27:31 AM UTC 24
Finished Sep 01 09:41:06 AM UTC 24
Peak memory 696788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008419552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4008419552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_error.2780771428
Short name T351
Test name
Test status
Simulation time 12551607942 ps
CPU time 165.56 seconds
Started Sep 01 09:27:37 AM UTC 24
Finished Sep 01 09:30:25 AM UTC 24
Peak memory 207440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780771428 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2780771428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_long_msg.4167976729
Short name T365
Test name
Test status
Simulation time 27068817168 ps
CPU time 238.32 seconds
Started Sep 01 09:27:23 AM UTC 24
Finished Sep 01 09:31:25 AM UTC 24
Peak memory 217744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167976729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.4167976729
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_smoke.3582439780
Short name T310
Test name
Test status
Simulation time 620905046 ps
CPU time 11.15 seconds
Started Sep 01 09:27:22 AM UTC 24
Finished Sep 01 09:27:34 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582439780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3582439780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_stress_all.1966000270
Short name T520
Test name
Test status
Simulation time 46817425073 ps
CPU time 2349.56 seconds
Started Sep 01 09:27:43 AM UTC 24
Finished Sep 01 10:07:18 AM UTC 24
Peak memory 772324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966000270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1966000270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.1297080976
Short name T86
Test name
Test status
Simulation time 1403983141 ps
CPU time 66.32 seconds
Started Sep 01 09:27:39 AM UTC 24
Finished Sep 01 09:28:48 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297080976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1297080976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_alert_test.3440762167
Short name T323
Test name
Test status
Simulation time 89300496 ps
CPU time 0.89 seconds
Started Sep 01 09:28:09 AM UTC 24
Finished Sep 01 09:28:11 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440762167 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3440762167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.1210079829
Short name T342
Test name
Test status
Simulation time 5858975492 ps
CPU time 104.17 seconds
Started Sep 01 09:27:49 AM UTC 24
Finished Sep 01 09:29:36 AM UTC 24
Peak memory 223784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210079829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1210079829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.1067400945
Short name T332
Test name
Test status
Simulation time 8896268788 ps
CPU time 39.69 seconds
Started Sep 01 09:27:57 AM UTC 24
Finished Sep 01 09:28:38 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067400945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1067400945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.3976900906
Short name T500
Test name
Test status
Simulation time 5993211213 ps
CPU time 1197.29 seconds
Started Sep 01 09:27:55 AM UTC 24
Finished Sep 01 09:48:04 AM UTC 24
Peak memory 778464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976900906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3976900906
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_error.1146987657
Short name T336
Test name
Test status
Simulation time 10741033332 ps
CPU time 65.87 seconds
Started Sep 01 09:28:01 AM UTC 24
Finished Sep 01 09:29:08 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146987657 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1146987657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_long_msg.1142545701
Short name T371
Test name
Test status
Simulation time 162360986514 ps
CPU time 243.24 seconds
Started Sep 01 09:27:49 AM UTC 24
Finished Sep 01 09:31:56 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142545701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1142545701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_smoke.2837390915
Short name T322
Test name
Test status
Simulation time 4132565567 ps
CPU time 18.58 seconds
Started Sep 01 09:27:49 AM UTC 24
Finished Sep 01 09:28:09 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837390915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2837390915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_stress_all.61739638
Short name T522
Test name
Test status
Simulation time 309939564342 ps
CPU time 2377.48 seconds
Started Sep 01 09:28:08 AM UTC 24
Finished Sep 01 10:08:12 AM UTC 24
Peak memory 731364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61739638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.61739638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.2239776679
Short name T87
Test name
Test status
Simulation time 1875012468 ps
CPU time 97.89 seconds
Started Sep 01 09:28:06 AM UTC 24
Finished Sep 01 09:29:46 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239776679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2239776679
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_alert_test.3224635048
Short name T331
Test name
Test status
Simulation time 14785109 ps
CPU time 0.87 seconds
Started Sep 01 09:28:36 AM UTC 24
Finished Sep 01 09:28:38 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224635048 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3224635048
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.3068722746
Short name T340
Test name
Test status
Simulation time 7385994962 ps
CPU time 72.84 seconds
Started Sep 01 09:28:14 AM UTC 24
Finished Sep 01 09:29:29 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068722746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3068722746
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.453522215
Short name T335
Test name
Test status
Simulation time 12893053303 ps
CPU time 40 seconds
Started Sep 01 09:28:21 AM UTC 24
Finished Sep 01 09:29:03 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453522215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.453522215
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.2545672150
Short name T367
Test name
Test status
Simulation time 4024156179 ps
CPU time 189.92 seconds
Started Sep 01 09:28:16 AM UTC 24
Finished Sep 01 09:31:29 AM UTC 24
Peak memory 635176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545672150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2545672150
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_error.2096102387
Short name T353
Test name
Test status
Simulation time 6548385645 ps
CPU time 121.99 seconds
Started Sep 01 09:28:29 AM UTC 24
Finished Sep 01 09:30:34 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096102387 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2096102387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_long_msg.1630406754
Short name T368
Test name
Test status
Simulation time 13905062550 ps
CPU time 197.49 seconds
Started Sep 01 09:28:11 AM UTC 24
Finished Sep 01 09:31:32 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630406754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1630406754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_smoke.2115789944
Short name T324
Test name
Test status
Simulation time 125530735 ps
CPU time 2.67 seconds
Started Sep 01 09:28:10 AM UTC 24
Finished Sep 01 09:28:14 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115789944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2115789944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_stress_all.3057238945
Short name T411
Test name
Test status
Simulation time 8518409689 ps
CPU time 367.26 seconds
Started Sep 01 09:28:33 AM UTC 24
Finished Sep 01 09:34:45 AM UTC 24
Peak memory 450916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057238945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3057238945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.4135163497
Short name T349
Test name
Test status
Simulation time 2012690646 ps
CPU time 110.95 seconds
Started Sep 01 09:28:29 AM UTC 24
Finished Sep 01 09:30:22 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135163497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4135163497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_alert_test.4163670601
Short name T338
Test name
Test status
Simulation time 26705670 ps
CPU time 0.91 seconds
Started Sep 01 09:29:16 AM UTC 24
Finished Sep 01 09:29:18 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163670601 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4163670601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.2776628835
Short name T333
Test name
Test status
Simulation time 182136427 ps
CPU time 2.35 seconds
Started Sep 01 09:28:50 AM UTC 24
Finished Sep 01 09:28:53 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776628835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2776628835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.1320673263
Short name T339
Test name
Test status
Simulation time 320668674 ps
CPU time 21.08 seconds
Started Sep 01 09:29:02 AM UTC 24
Finished Sep 01 09:29:24 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320673263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1320673263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.4078542706
Short name T345
Test name
Test status
Simulation time 10274843190 ps
CPU time 57.06 seconds
Started Sep 01 09:28:54 AM UTC 24
Finished Sep 01 09:29:53 AM UTC 24
Peak memory 243944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078542706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4078542706
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_error.3096032867
Short name T360
Test name
Test status
Simulation time 43443866821 ps
CPU time 113.55 seconds
Started Sep 01 09:29:02 AM UTC 24
Finished Sep 01 09:30:57 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096032867 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3096032867
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_long_msg.2459977005
Short name T352
Test name
Test status
Simulation time 5506222387 ps
CPU time 110.96 seconds
Started Sep 01 09:28:39 AM UTC 24
Finished Sep 01 09:30:32 AM UTC 24
Peak memory 207368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459977005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2459977005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_smoke.2994724544
Short name T334
Test name
Test status
Simulation time 303240138 ps
CPU time 17.78 seconds
Started Sep 01 09:28:39 AM UTC 24
Finished Sep 01 09:28:58 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994724544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2994724544
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_stress_all.3111267813
Short name T400
Test name
Test status
Simulation time 17601800219 ps
CPU time 282.05 seconds
Started Sep 01 09:29:09 AM UTC 24
Finished Sep 01 09:33:55 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111267813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3111267813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.3805787621
Short name T337
Test name
Test status
Simulation time 266190202 ps
CPU time 10.33 seconds
Started Sep 01 09:29:04 AM UTC 24
Finished Sep 01 09:29:15 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805787621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3805787621
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_alert_test.2080512877
Short name T346
Test name
Test status
Simulation time 13358281 ps
CPU time 0.9 seconds
Started Sep 01 09:29:54 AM UTC 24
Finished Sep 01 09:29:56 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080512877 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2080512877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.2821747010
Short name T357
Test name
Test status
Simulation time 3868507234 ps
CPU time 71.86 seconds
Started Sep 01 09:29:30 AM UTC 24
Finished Sep 01 09:30:44 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821747010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2821747010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.4015843644
Short name T494
Test name
Test status
Simulation time 4567011752 ps
CPU time 805.76 seconds
Started Sep 01 09:29:35 AM UTC 24
Finished Sep 01 09:43:11 AM UTC 24
Peak memory 706860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015843644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4015843644
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_error.3155152370
Short name T361
Test name
Test status
Simulation time 1371422125 ps
CPU time 73.96 seconds
Started Sep 01 09:29:47 AM UTC 24
Finished Sep 01 09:31:03 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155152370 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3155152370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_long_msg.868241487
Short name T344
Test name
Test status
Simulation time 1476084280 ps
CPU time 26.49 seconds
Started Sep 01 09:29:25 AM UTC 24
Finished Sep 01 09:29:52 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868241487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.868241487
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_smoke.3288057004
Short name T341
Test name
Test status
Simulation time 842892553 ps
CPU time 13.86 seconds
Started Sep 01 09:29:19 AM UTC 24
Finished Sep 01 09:29:35 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288057004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3288057004
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_stress_all.1421755270
Short name T75
Test name
Test status
Simulation time 21184431261 ps
CPU time 264.25 seconds
Started Sep 01 09:29:54 AM UTC 24
Finished Sep 01 09:34:22 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421755270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1421755270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.2723948364
Short name T383
Test name
Test status
Simulation time 37347450270 ps
CPU time 165.36 seconds
Started Sep 01 09:29:51 AM UTC 24
Finished Sep 01 09:32:40 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723948364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2723948364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_alert_test.4133302219
Short name T354
Test name
Test status
Simulation time 14663866 ps
CPU time 0.8 seconds
Started Sep 01 09:30:35 AM UTC 24
Finished Sep 01 09:30:37 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133302219 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4133302219
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.3686793264
Short name T370
Test name
Test status
Simulation time 1335269493 ps
CPU time 96.77 seconds
Started Sep 01 09:30:13 AM UTC 24
Finished Sep 01 09:31:52 AM UTC 24
Peak memory 215688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686793264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3686793264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.3956308793
Short name T355
Test name
Test status
Simulation time 3483700694 ps
CPU time 12.67 seconds
Started Sep 01 09:30:24 AM UTC 24
Finished Sep 01 09:30:38 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956308793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3956308793
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1652269045
Short name T430
Test name
Test status
Simulation time 1743174593 ps
CPU time 384.19 seconds
Started Sep 01 09:30:20 AM UTC 24
Finished Sep 01 09:36:50 AM UTC 24
Peak memory 643360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652269045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1652269045
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_error.3460881657
Short name T369
Test name
Test status
Simulation time 3288961117 ps
CPU time 64.24 seconds
Started Sep 01 09:30:27 AM UTC 24
Finished Sep 01 09:31:33 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460881657 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3460881657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_long_msg.1496786012
Short name T377
Test name
Test status
Simulation time 37453749711 ps
CPU time 133.35 seconds
Started Sep 01 09:30:06 AM UTC 24
Finished Sep 01 09:32:22 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496786012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1496786012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_smoke.2762272249
Short name T347
Test name
Test status
Simulation time 315246253 ps
CPU time 7.46 seconds
Started Sep 01 09:29:57 AM UTC 24
Finished Sep 01 09:30:06 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762272249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2762272249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_stress_all.1776261573
Short name T419
Test name
Test status
Simulation time 4510305873 ps
CPU time 310.55 seconds
Started Sep 01 09:30:34 AM UTC 24
Finished Sep 01 09:35:49 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776261573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1776261573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.2155900194
Short name T89
Test name
Test status
Simulation time 9798965265 ps
CPU time 179.57 seconds
Started Sep 01 09:30:27 AM UTC 24
Finished Sep 01 09:33:30 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155900194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2155900194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_alert_test.347599357
Short name T363
Test name
Test status
Simulation time 36530812 ps
CPU time 0.77 seconds
Started Sep 01 09:31:10 AM UTC 24
Finished Sep 01 09:31:12 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347599357 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.347599357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.3611951450
Short name T364
Test name
Test status
Simulation time 349466824 ps
CPU time 25.49 seconds
Started Sep 01 09:30:45 AM UTC 24
Finished Sep 01 09:31:12 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611951450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3611951450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3191568574
Short name T362
Test name
Test status
Simulation time 2877536086 ps
CPU time 18.56 seconds
Started Sep 01 09:30:50 AM UTC 24
Finished Sep 01 09:31:09 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191568574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3191568574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.1743053154
Short name T475
Test name
Test status
Simulation time 5343163628 ps
CPU time 565.77 seconds
Started Sep 01 09:30:45 AM UTC 24
Finished Sep 01 09:40:18 AM UTC 24
Peak memory 700700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743053154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1743053154
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_error.296605559
Short name T402
Test name
Test status
Simulation time 3398354379 ps
CPU time 185.65 seconds
Started Sep 01 09:30:56 AM UTC 24
Finished Sep 01 09:34:05 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296605559 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.296605559
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_long_msg.2247795301
Short name T378
Test name
Test status
Simulation time 1529046151 ps
CPU time 103.77 seconds
Started Sep 01 09:30:38 AM UTC 24
Finished Sep 01 09:32:24 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247795301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2247795301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_smoke.2860382389
Short name T358
Test name
Test status
Simulation time 307696327 ps
CPU time 8.79 seconds
Started Sep 01 09:30:38 AM UTC 24
Finished Sep 01 09:30:48 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860382389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2860382389
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_stress_all.2103405065
Short name T508
Test name
Test status
Simulation time 95478913659 ps
CPU time 1501.37 seconds
Started Sep 01 09:31:04 AM UTC 24
Finished Sep 01 09:56:22 AM UTC 24
Peak memory 690404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103405065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2103405065
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.308583929
Short name T379
Test name
Test status
Simulation time 7208888468 ps
CPU time 84.91 seconds
Started Sep 01 09:30:59 AM UTC 24
Finished Sep 01 09:32:26 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308583929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.308583929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_alert_test.2947403684
Short name T372
Test name
Test status
Simulation time 22501716 ps
CPU time 0.85 seconds
Started Sep 01 09:31:58 AM UTC 24
Finished Sep 01 09:32:00 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947403684 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2947403684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.4289955302
Short name T376
Test name
Test status
Simulation time 2707695932 ps
CPU time 52.3 seconds
Started Sep 01 09:31:27 AM UTC 24
Finished Sep 01 09:32:21 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289955302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4289955302
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.3839356239
Short name T374
Test name
Test status
Simulation time 7051320570 ps
CPU time 32.65 seconds
Started Sep 01 09:31:31 AM UTC 24
Finished Sep 01 09:32:05 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839356239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3839356239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.3376344774
Short name T486
Test name
Test status
Simulation time 2773083579 ps
CPU time 621.01 seconds
Started Sep 01 09:31:27 AM UTC 24
Finished Sep 01 09:41:56 AM UTC 24
Peak memory 700888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376344774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3376344774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_error.2055184673
Short name T415
Test name
Test status
Simulation time 10898876487 ps
CPU time 194.22 seconds
Started Sep 01 09:31:34 AM UTC 24
Finished Sep 01 09:34:52 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055184673 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2055184673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_long_msg.531100567
Short name T393
Test name
Test status
Simulation time 37001141439 ps
CPU time 141.43 seconds
Started Sep 01 09:31:13 AM UTC 24
Finished Sep 01 09:33:37 AM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531100567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.531100567
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_smoke.4247945469
Short name T366
Test name
Test status
Simulation time 858500210 ps
CPU time 12.48 seconds
Started Sep 01 09:31:12 AM UTC 24
Finished Sep 01 09:31:25 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247945469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4247945469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_stress_all.1159984010
Short name T79
Test name
Test status
Simulation time 157852827194 ps
CPU time 1550.42 seconds
Started Sep 01 09:31:54 AM UTC 24
Finished Sep 01 09:58:01 AM UTC 24
Peak memory 702956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159984010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1159984010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.4128234645
Short name T398
Test name
Test status
Simulation time 3151964269 ps
CPU time 130.62 seconds
Started Sep 01 09:31:34 AM UTC 24
Finished Sep 01 09:33:47 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128234645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4128234645
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_alert_test.3370652310
Short name T382
Test name
Test status
Simulation time 30248236 ps
CPU time 0.82 seconds
Started Sep 01 09:32:34 AM UTC 24
Finished Sep 01 09:32:35 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370652310 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3370652310
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.759017688
Short name T381
Test name
Test status
Simulation time 326481040 ps
CPU time 27.28 seconds
Started Sep 01 09:32:06 AM UTC 24
Finished Sep 01 09:32:34 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759017688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.759017688
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.49985519
Short name T380
Test name
Test status
Simulation time 493378672 ps
CPU time 9.55 seconds
Started Sep 01 09:32:22 AM UTC 24
Finished Sep 01 09:32:33 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49985519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.49985519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2322901753
Short name T432
Test name
Test status
Simulation time 1704789558 ps
CPU time 271.73 seconds
Started Sep 01 09:32:18 AM UTC 24
Finished Sep 01 09:36:53 AM UTC 24
Peak memory 471456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322901753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2322901753
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_error.1544068056
Short name T403
Test name
Test status
Simulation time 4845513233 ps
CPU time 101.73 seconds
Started Sep 01 09:32:24 AM UTC 24
Finished Sep 01 09:34:08 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544068056 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1544068056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_long_msg.3315937750
Short name T412
Test name
Test status
Simulation time 2653116806 ps
CPU time 157.69 seconds
Started Sep 01 09:32:05 AM UTC 24
Finished Sep 01 09:34:46 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315937750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3315937750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_smoke.2236579468
Short name T375
Test name
Test status
Simulation time 795730493 ps
CPU time 13.85 seconds
Started Sep 01 09:32:01 AM UTC 24
Finished Sep 01 09:32:17 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236579468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2236579468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_stress_all.32537937
Short name T525
Test name
Test status
Simulation time 31370462830 ps
CPU time 2316.7 seconds
Started Sep 01 09:32:27 AM UTC 24
Finished Sep 01 10:11:29 AM UTC 24
Peak memory 788840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32537937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.32537937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.4066723167
Short name T388
Test name
Test status
Simulation time 2309821557 ps
CPU time 35.4 seconds
Started Sep 01 09:32:26 AM UTC 24
Finished Sep 01 09:33:03 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066723167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4066723167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_alert_test.880935196
Short name T390
Test name
Test status
Simulation time 37433365 ps
CPU time 0.78 seconds
Started Sep 01 09:33:14 AM UTC 24
Finished Sep 01 09:33:16 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880935196 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.880935196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.1579358640
Short name T386
Test name
Test status
Simulation time 2254255853 ps
CPU time 13.57 seconds
Started Sep 01 09:32:42 AM UTC 24
Finished Sep 01 09:32:56 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579358640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1579358640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.10438029
Short name T392
Test name
Test status
Simulation time 4408320316 ps
CPU time 45.51 seconds
Started Sep 01 09:32:44 AM UTC 24
Finished Sep 01 09:33:31 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10438029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.10438029
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.3488036382
Short name T503
Test name
Test status
Simulation time 6917375501 ps
CPU time 1225.7 seconds
Started Sep 01 09:32:42 AM UTC 24
Finished Sep 01 09:53:20 AM UTC 24
Peak memory 717096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488036382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3488036382
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_error.3692382961
Short name T426
Test name
Test status
Simulation time 10305000069 ps
CPU time 212.7 seconds
Started Sep 01 09:32:57 AM UTC 24
Finished Sep 01 09:36:33 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692382961 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3692382961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_long_msg.2233589847
Short name T385
Test name
Test status
Simulation time 1199578271 ps
CPU time 5.56 seconds
Started Sep 01 09:32:36 AM UTC 24
Finished Sep 01 09:32:43 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233589847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2233589847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_smoke.1324290088
Short name T384
Test name
Test status
Simulation time 695967364 ps
CPU time 3.88 seconds
Started Sep 01 09:32:36 AM UTC 24
Finished Sep 01 09:32:41 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324290088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1324290088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_stress_all.2051268310
Short name T506
Test name
Test status
Simulation time 207221317978 ps
CPU time 1342.64 seconds
Started Sep 01 09:33:05 AM UTC 24
Finished Sep 01 09:55:42 AM UTC 24
Peak memory 762120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051268310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2051268310
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.1687225324
Short name T396
Test name
Test status
Simulation time 681863966 ps
CPU time 39.78 seconds
Started Sep 01 09:33:05 AM UTC 24
Finished Sep 01 09:33:46 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687225324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1687225324
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_alert_test.3007007907
Short name T167
Test name
Test status
Simulation time 18314834 ps
CPU time 0.81 seconds
Started Sep 01 09:15:50 AM UTC 24
Finished Sep 01 09:15:52 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007007907 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3007007907
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.642639411
Short name T20
Test name
Test status
Simulation time 21502881372 ps
CPU time 83.18 seconds
Started Sep 01 09:15:25 AM UTC 24
Finished Sep 01 09:16:50 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642639411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.642639411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.726509519
Short name T41
Test name
Test status
Simulation time 1757832440 ps
CPU time 40.5 seconds
Started Sep 01 09:15:31 AM UTC 24
Finished Sep 01 09:16:13 AM UTC 24
Peak memory 215640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726509519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.726509519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.2652062293
Short name T373
Test name
Test status
Simulation time 21279882307 ps
CPU time 983.99 seconds
Started Sep 01 09:15:27 AM UTC 24
Finished Sep 01 09:32:02 AM UTC 24
Peak memory 735456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652062293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2652062293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_error.2507569012
Short name T49
Test name
Test status
Simulation time 8468380847 ps
CPU time 35.5 seconds
Started Sep 01 09:15:31 AM UTC 24
Finished Sep 01 09:16:08 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507569012 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2507569012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_long_msg.3147084221
Short name T70
Test name
Test status
Simulation time 6063193933 ps
CPU time 85.75 seconds
Started Sep 01 09:15:24 AM UTC 24
Finished Sep 01 09:16:52 AM UTC 24
Peak memory 207092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147084221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3147084221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.2042938200
Short name T40
Test name
Test status
Simulation time 138530334 ps
CPU time 1.2 seconds
Started Sep 01 09:15:49 AM UTC 24
Finished Sep 01 09:15:52 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042938200 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2042938200
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_smoke.3738300208
Short name T22
Test name
Test status
Simulation time 2592060116 ps
CPU time 11.36 seconds
Started Sep 01 09:15:24 AM UTC 24
Finished Sep 01 09:15:37 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738300208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3738300208
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_stress_all.1809472196
Short name T214
Test name
Test status
Simulation time 26360649446 ps
CPU time 282.21 seconds
Started Sep 01 09:15:45 AM UTC 24
Finished Sep 01 09:20:31 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809472196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1809472196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.1675198354
Short name T73
Test name
Test status
Simulation time 6649223317 ps
CPU time 74.77 seconds
Started Sep 01 09:15:38 AM UTC 24
Finished Sep 01 09:16:54 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675198354 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1675198354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.1970453922
Short name T74
Test name
Test status
Simulation time 4509329508 ps
CPU time 76.73 seconds
Started Sep 01 09:15:40 AM UTC 24
Finished Sep 01 09:16:58 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970453922 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1970453922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.1766784109
Short name T187
Test name
Test status
Simulation time 8333016894 ps
CPU time 137.75 seconds
Started Sep 01 09:15:43 AM UTC 24
Finished Sep 01 09:18:03 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766784109 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1766784109
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.980363924
Short name T142
Test name
Test status
Simulation time 9934379822 ps
CPU time 587.11 seconds
Started Sep 01 09:15:36 AM UTC 24
Finished Sep 01 09:25:31 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980363924 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.980363924
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.1577977054
Short name T504
Test name
Test status
Simulation time 70002419713 ps
CPU time 2247.32 seconds
Started Sep 01 09:15:36 AM UTC 24
Finished Sep 01 09:53:29 AM UTC 24
Peak memory 221248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577977054 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1577977054
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.660513108
Short name T515
Test name
Test status
Simulation time 1025548200308 ps
CPU time 2641.77 seconds
Started Sep 01 09:15:37 AM UTC 24
Finished Sep 01 10:00:09 AM UTC 24
Peak memory 221240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660513108 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.660513108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.149444373
Short name T30
Test name
Test status
Simulation time 23259664 ps
CPU time 0.97 seconds
Started Sep 01 09:15:33 AM UTC 24
Finished Sep 01 09:15:35 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149444373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.149444373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_alert_test.425374634
Short name T399
Test name
Test status
Simulation time 88869544 ps
CPU time 0.78 seconds
Started Sep 01 09:33:47 AM UTC 24
Finished Sep 01 09:33:49 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425374634 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.425374634
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.934412281
Short name T410
Test name
Test status
Simulation time 2262959261 ps
CPU time 67.81 seconds
Started Sep 01 09:33:25 AM UTC 24
Finished Sep 01 09:34:34 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934412281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.934412281
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.832457669
Short name T156
Test name
Test status
Simulation time 911580098 ps
CPU time 32.61 seconds
Started Sep 01 09:33:31 AM UTC 24
Finished Sep 01 09:34:06 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832457669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.832457669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.4169240990
Short name T491
Test name
Test status
Simulation time 2830512819 ps
CPU time 538.27 seconds
Started Sep 01 09:33:31 AM UTC 24
Finished Sep 01 09:42:36 AM UTC 24
Peak memory 674088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169240990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4169240990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_error.808379957
Short name T395
Test name
Test status
Simulation time 20462831 ps
CPU time 1.31 seconds
Started Sep 01 09:33:39 AM UTC 24
Finished Sep 01 09:33:42 AM UTC 24
Peak memory 206400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808379957 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.808379957
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1123953662
Short name T408
Test name
Test status
Simulation time 2481284567 ps
CPU time 68.14 seconds
Started Sep 01 09:33:18 AM UTC 24
Finished Sep 01 09:34:28 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123953662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1123953662
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_smoke.26403362
Short name T394
Test name
Test status
Simulation time 1355946486 ps
CPU time 19.15 seconds
Started Sep 01 09:33:18 AM UTC 24
Finished Sep 01 09:33:38 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26403362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 40.hmac_smoke.26403362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_stress_all.688512871
Short name T528
Test name
Test status
Simulation time 104213084169 ps
CPU time 3104.3 seconds
Started Sep 01 09:33:43 AM UTC 24
Finished Sep 01 10:25:58 AM UTC 24
Peak memory 815344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688512871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.688512871
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.3501006568
Short name T420
Test name
Test status
Simulation time 7881980577 ps
CPU time 133.48 seconds
Started Sep 01 09:33:39 AM UTC 24
Finished Sep 01 09:35:55 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501006568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3501006568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_alert_test.3897565280
Short name T405
Test name
Test status
Simulation time 114523164 ps
CPU time 0.88 seconds
Started Sep 01 09:34:16 AM UTC 24
Finished Sep 01 09:34:18 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897565280 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3897565280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.2999511048
Short name T418
Test name
Test status
Simulation time 1644081574 ps
CPU time 93.58 seconds
Started Sep 01 09:33:51 AM UTC 24
Finished Sep 01 09:35:27 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999511048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2999511048
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.3501859799
Short name T417
Test name
Test status
Simulation time 3093154961 ps
CPU time 56.78 seconds
Started Sep 01 09:34:10 AM UTC 24
Finished Sep 01 09:35:09 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501859799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3501859799
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.770247024
Short name T513
Test name
Test status
Simulation time 7445210568 ps
CPU time 1452.43 seconds
Started Sep 01 09:33:58 AM UTC 24
Finished Sep 01 09:58:26 AM UTC 24
Peak memory 778724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770247024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.770247024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_error.3109648681
Short name T457
Test name
Test status
Simulation time 91800852177 ps
CPU time 261.37 seconds
Started Sep 01 09:34:10 AM UTC 24
Finished Sep 01 09:38:36 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109648681 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3109648681
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_long_msg.3264920536
Short name T425
Test name
Test status
Simulation time 17971160122 ps
CPU time 154.45 seconds
Started Sep 01 09:33:51 AM UTC 24
Finished Sep 01 09:36:28 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264920536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3264920536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_smoke.1374278717
Short name T404
Test name
Test status
Simulation time 2749499806 ps
CPU time 22.94 seconds
Started Sep 01 09:33:51 AM UTC 24
Finished Sep 01 09:34:15 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374278717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1374278717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_stress_all.1747473251
Short name T512
Test name
Test status
Simulation time 28818504926 ps
CPU time 1385.8 seconds
Started Sep 01 09:34:11 AM UTC 24
Finished Sep 01 09:57:33 AM UTC 24
Peak memory 778448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747473251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1747473251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.3301108254
Short name T406
Test name
Test status
Simulation time 1939244208 ps
CPU time 10.18 seconds
Started Sep 01 09:34:11 AM UTC 24
Finished Sep 01 09:34:22 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301108254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3301108254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_alert_test.2213645104
Short name T414
Test name
Test status
Simulation time 13059668 ps
CPU time 0.89 seconds
Started Sep 01 09:34:49 AM UTC 24
Finished Sep 01 09:34:51 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213645104 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2213645104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.995010711
Short name T424
Test name
Test status
Simulation time 5983138270 ps
CPU time 113.45 seconds
Started Sep 01 09:34:25 AM UTC 24
Finished Sep 01 09:36:20 AM UTC 24
Peak memory 217812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995010711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.995010711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.3467687831
Short name T413
Test name
Test status
Simulation time 3879709379 ps
CPU time 17.74 seconds
Started Sep 01 09:34:29 AM UTC 24
Finished Sep 01 09:34:48 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467687831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3467687831
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.1268831262
Short name T509
Test name
Test status
Simulation time 11370114401 ps
CPU time 1304.02 seconds
Started Sep 01 09:34:28 AM UTC 24
Finished Sep 01 09:56:29 AM UTC 24
Peak memory 745744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268831262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1268831262
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_error.159466591
Short name T428
Test name
Test status
Simulation time 5831334393 ps
CPU time 123.23 seconds
Started Sep 01 09:34:34 AM UTC 24
Finished Sep 01 09:36:40 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159466591 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.159466591
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_long_msg.56307855
Short name T407
Test name
Test status
Simulation time 51968323 ps
CPU time 1.54 seconds
Started Sep 01 09:34:25 AM UTC 24
Finished Sep 01 09:34:27 AM UTC 24
Peak memory 206228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56307855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.56307855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_smoke.1099288985
Short name T409
Test name
Test status
Simulation time 833420542 ps
CPU time 13.6 seconds
Started Sep 01 09:34:19 AM UTC 24
Finished Sep 01 09:34:34 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099288985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1099288985
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_stress_all.1417186370
Short name T502
Test name
Test status
Simulation time 8119732903 ps
CPU time 924.6 seconds
Started Sep 01 09:34:49 AM UTC 24
Finished Sep 01 09:50:24 AM UTC 24
Peak memory 721180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417186370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1417186370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.2389071684
Short name T446
Test name
Test status
Simulation time 7372150426 ps
CPU time 170.52 seconds
Started Sep 01 09:34:36 AM UTC 24
Finished Sep 01 09:37:30 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389071684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2389071684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_alert_test.541728577
Short name T422
Test name
Test status
Simulation time 12582666 ps
CPU time 0.86 seconds
Started Sep 01 09:36:02 AM UTC 24
Finished Sep 01 09:36:04 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541728577 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.541728577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.1196248011
Short name T421
Test name
Test status
Simulation time 4466132238 ps
CPU time 65.01 seconds
Started Sep 01 09:34:54 AM UTC 24
Finished Sep 01 09:36:00 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196248011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1196248011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.4237875038
Short name T427
Test name
Test status
Simulation time 12526095652 ps
CPU time 86.67 seconds
Started Sep 01 09:35:10 AM UTC 24
Finished Sep 01 09:36:39 AM UTC 24
Peak memory 217740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237875038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4237875038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.2004980154
Short name T489
Test name
Test status
Simulation time 2268806479 ps
CPU time 432.27 seconds
Started Sep 01 09:35:03 AM UTC 24
Finished Sep 01 09:42:20 AM UTC 24
Peak memory 665828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004980154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2004980154
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_error.3297677463
Short name T437
Test name
Test status
Simulation time 1532023769 ps
CPU time 97.84 seconds
Started Sep 01 09:35:29 AM UTC 24
Finished Sep 01 09:37:09 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297677463 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3297677463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1425021081
Short name T434
Test name
Test status
Simulation time 11236884047 ps
CPU time 128.01 seconds
Started Sep 01 09:34:52 AM UTC 24
Finished Sep 01 09:37:02 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425021081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1425021081
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_smoke.124657041
Short name T416
Test name
Test status
Simulation time 600556972 ps
CPU time 11.85 seconds
Started Sep 01 09:34:49 AM UTC 24
Finished Sep 01 09:35:02 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124657041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.124657041
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_stress_all.3930666220
Short name T493
Test name
Test status
Simulation time 41312209835 ps
CPU time 416.79 seconds
Started Sep 01 09:35:57 AM UTC 24
Finished Sep 01 09:43:00 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930666220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3930666220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2713827904
Short name T456
Test name
Test status
Simulation time 2680984474 ps
CPU time 158.91 seconds
Started Sep 01 09:35:51 AM UTC 24
Finished Sep 01 09:38:33 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713827904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2713827904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_alert_test.3896190091
Short name T433
Test name
Test status
Simulation time 10574361 ps
CPU time 0.82 seconds
Started Sep 01 09:36:52 AM UTC 24
Finished Sep 01 09:36:53 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896190091 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3896190091
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.3810354709
Short name T443
Test name
Test status
Simulation time 1067493498 ps
CPU time 56.56 seconds
Started Sep 01 09:36:22 AM UTC 24
Finished Sep 01 09:37:20 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810354709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3810354709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.339770913
Short name T453
Test name
Test status
Simulation time 18080880161 ps
CPU time 84.25 seconds
Started Sep 01 09:36:35 AM UTC 24
Finished Sep 01 09:38:01 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339770913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.339770913
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.1986760422
Short name T478
Test name
Test status
Simulation time 3502636829 ps
CPU time 252.33 seconds
Started Sep 01 09:36:30 AM UTC 24
Finished Sep 01 09:40:45 AM UTC 24
Peak memory 719076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986760422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1986760422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_error.2780812549
Short name T460
Test name
Test status
Simulation time 9330503960 ps
CPU time 126.53 seconds
Started Sep 01 09:36:39 AM UTC 24
Finished Sep 01 09:38:48 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780812549 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2780812549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_long_msg.668073396
Short name T445
Test name
Test status
Simulation time 4086213995 ps
CPU time 69.27 seconds
Started Sep 01 09:36:18 AM UTC 24
Finished Sep 01 09:37:29 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668073396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.668073396
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_smoke.3570860467
Short name T423
Test name
Test status
Simulation time 499238043 ps
CPU time 10.98 seconds
Started Sep 01 09:36:05 AM UTC 24
Finished Sep 01 09:36:17 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570860467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3570860467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_stress_all.621715202
Short name T455
Test name
Test status
Simulation time 30821361408 ps
CPU time 105.21 seconds
Started Sep 01 09:36:45 AM UTC 24
Finished Sep 01 09:38:32 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621715202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.621715202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.1384881123
Short name T439
Test name
Test status
Simulation time 25159038016 ps
CPU time 29.27 seconds
Started Sep 01 09:36:42 AM UTC 24
Finished Sep 01 09:37:12 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384881123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1384881123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_alert_test.3274364209
Short name T441
Test name
Test status
Simulation time 58187299 ps
CPU time 0.86 seconds
Started Sep 01 09:37:13 AM UTC 24
Finished Sep 01 09:37:15 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274364209 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3274364209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.1164456176
Short name T438
Test name
Test status
Simulation time 270378082 ps
CPU time 10.86 seconds
Started Sep 01 09:36:57 AM UTC 24
Finished Sep 01 09:37:09 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164456176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1164456176
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.2932999399
Short name T448
Test name
Test status
Simulation time 862601864 ps
CPU time 41.57 seconds
Started Sep 01 09:37:08 AM UTC 24
Finished Sep 01 09:37:51 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932999399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2932999399
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.1715313463
Short name T518
Test name
Test status
Simulation time 47046089448 ps
CPU time 1617.37 seconds
Started Sep 01 09:37:04 AM UTC 24
Finished Sep 01 10:04:18 AM UTC 24
Peak memory 764440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715313463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1715313463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_error.2767756639
Short name T477
Test name
Test status
Simulation time 52203537817 ps
CPU time 207.21 seconds
Started Sep 01 09:37:08 AM UTC 24
Finished Sep 01 09:40:39 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767756639 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2767756639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_long_msg.3290390020
Short name T465
Test name
Test status
Simulation time 8309795861 ps
CPU time 131.73 seconds
Started Sep 01 09:36:57 AM UTC 24
Finished Sep 01 09:39:11 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290390020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3290390020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_smoke.1309481151
Short name T436
Test name
Test status
Simulation time 141077340 ps
CPU time 9.57 seconds
Started Sep 01 09:36:57 AM UTC 24
Finished Sep 01 09:37:07 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309481151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1309481151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_stress_all.875979948
Short name T463
Test name
Test status
Simulation time 18644113237 ps
CPU time 113.83 seconds
Started Sep 01 09:37:10 AM UTC 24
Finished Sep 01 09:39:06 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875979948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.875979948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.2134499002
Short name T440
Test name
Test status
Simulation time 41191757 ps
CPU time 1.59 seconds
Started Sep 01 09:37:10 AM UTC 24
Finished Sep 01 09:37:13 AM UTC 24
Peak memory 206228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134499002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2134499002
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_alert_test.841173572
Short name T449
Test name
Test status
Simulation time 31360872 ps
CPU time 0.89 seconds
Started Sep 01 09:37:52 AM UTC 24
Finished Sep 01 09:37:54 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841173572 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.841173572
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.535687599
Short name T466
Test name
Test status
Simulation time 4716735604 ps
CPU time 111.45 seconds
Started Sep 01 09:37:20 AM UTC 24
Finished Sep 01 09:39:14 AM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535687599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.535687599
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.3145977684
Short name T451
Test name
Test status
Simulation time 1043272351 ps
CPU time 34.55 seconds
Started Sep 01 09:37:22 AM UTC 24
Finished Sep 01 09:37:58 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145977684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3145977684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.232764014
Short name T498
Test name
Test status
Simulation time 3079191834 ps
CPU time 503.89 seconds
Started Sep 01 09:37:22 AM UTC 24
Finished Sep 01 09:45:52 AM UTC 24
Peak memory 510168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232764014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.232764014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_error.1984531233
Short name T487
Test name
Test status
Simulation time 11815631206 ps
CPU time 266.41 seconds
Started Sep 01 09:37:30 AM UTC 24
Finished Sep 01 09:42:01 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984531233 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1984531233
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_long_msg.2237330606
Short name T447
Test name
Test status
Simulation time 3325145137 ps
CPU time 29.23 seconds
Started Sep 01 09:37:16 AM UTC 24
Finished Sep 01 09:37:47 AM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237330606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2237330606
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_smoke.497579934
Short name T444
Test name
Test status
Simulation time 4328319772 ps
CPU time 6.62 seconds
Started Sep 01 09:37:13 AM UTC 24
Finished Sep 01 09:37:21 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497579934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.497579934
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_stress_all.3695562546
Short name T529
Test name
Test status
Simulation time 82366764080 ps
CPU time 2884.3 seconds
Started Sep 01 09:37:47 AM UTC 24
Finished Sep 01 10:26:23 AM UTC 24
Peak memory 780528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695562546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3695562546
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.3213235177
Short name T462
Test name
Test status
Simulation time 5577228570 ps
CPU time 88.78 seconds
Started Sep 01 09:37:32 AM UTC 24
Finished Sep 01 09:39:03 AM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213235177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3213235177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_alert_test.156192328
Short name T458
Test name
Test status
Simulation time 51135245 ps
CPU time 0.76 seconds
Started Sep 01 09:38:38 AM UTC 24
Finished Sep 01 09:38:40 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156192328 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.156192328
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.3993010601
Short name T468
Test name
Test status
Simulation time 6918253389 ps
CPU time 84.3 seconds
Started Sep 01 09:38:01 AM UTC 24
Finished Sep 01 09:39:27 AM UTC 24
Peak memory 217800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993010601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3993010601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.3220995488
Short name T454
Test name
Test status
Simulation time 2520983175 ps
CPU time 22.43 seconds
Started Sep 01 09:38:02 AM UTC 24
Finished Sep 01 09:38:26 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220995488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3220995488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2622418175
Short name T484
Test name
Test status
Simulation time 1088721573 ps
CPU time 206.64 seconds
Started Sep 01 09:38:01 AM UTC 24
Finished Sep 01 09:41:31 AM UTC 24
Peak memory 413860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622418175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2622418175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_error.410657179
Short name T490
Test name
Test status
Simulation time 10487703179 ps
CPU time 234.26 seconds
Started Sep 01 09:38:26 AM UTC 24
Finished Sep 01 09:42:24 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410657179 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.410657179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_long_msg.327114420
Short name T481
Test name
Test status
Simulation time 43197081461 ps
CPU time 186.53 seconds
Started Sep 01 09:38:01 AM UTC 24
Finished Sep 01 09:41:10 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327114420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.327114420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_smoke.2680464657
Short name T452
Test name
Test status
Simulation time 791320667 ps
CPU time 3.4 seconds
Started Sep 01 09:37:55 AM UTC 24
Finished Sep 01 09:37:59 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680464657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2680464657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_stress_all.3144806431
Short name T533
Test name
Test status
Simulation time 24818089523 ps
CPU time 4760.57 seconds
Started Sep 01 09:38:36 AM UTC 24
Finished Sep 01 10:58:46 AM UTC 24
Peak memory 813364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144806431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3144806431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.2815980051
Short name T464
Test name
Test status
Simulation time 2651936057 ps
CPU time 33.18 seconds
Started Sep 01 09:38:34 AM UTC 24
Finished Sep 01 09:39:08 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815980051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2815980051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2860778473
Short name T467
Test name
Test status
Simulation time 34562890 ps
CPU time 0.86 seconds
Started Sep 01 09:39:16 AM UTC 24
Finished Sep 01 09:39:18 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860778473 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2860778473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.881836437
Short name T34
Test name
Test status
Simulation time 2447552916 ps
CPU time 111.72 seconds
Started Sep 01 09:38:49 AM UTC 24
Finished Sep 01 09:40:43 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881836437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.881836437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.59362942
Short name T469
Test name
Test status
Simulation time 410824781 ps
CPU time 22.42 seconds
Started Sep 01 09:39:04 AM UTC 24
Finished Sep 01 09:39:27 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59362942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.59362942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.506555187
Short name T497
Test name
Test status
Simulation time 8542466339 ps
CPU time 336.94 seconds
Started Sep 01 09:38:57 AM UTC 24
Finished Sep 01 09:44:39 AM UTC 24
Peak memory 661780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506555187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.506555187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_error.855309099
Short name T488
Test name
Test status
Simulation time 5970168650 ps
CPU time 182.31 seconds
Started Sep 01 09:39:08 AM UTC 24
Finished Sep 01 09:42:13 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855309099 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.855309099
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_long_msg.1958818811
Short name T471
Test name
Test status
Simulation time 799365136 ps
CPU time 62.55 seconds
Started Sep 01 09:38:43 AM UTC 24
Finished Sep 01 09:39:47 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958818811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1958818811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_smoke.1287729984
Short name T459
Test name
Test status
Simulation time 45814695 ps
CPU time 1.45 seconds
Started Sep 01 09:38:40 AM UTC 24
Finished Sep 01 09:38:43 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287729984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1287729984
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_stress_all.3207102137
Short name T531
Test name
Test status
Simulation time 152853734913 ps
CPU time 3841.08 seconds
Started Sep 01 09:39:13 AM UTC 24
Finished Sep 01 10:43:55 AM UTC 24
Peak memory 782508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207102137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3207102137
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.2023769861
Short name T485
Test name
Test status
Simulation time 35413787041 ps
CPU time 142.11 seconds
Started Sep 01 09:39:10 AM UTC 24
Finished Sep 01 09:41:35 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023769861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2023769861
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_alert_test.1075735108
Short name T474
Test name
Test status
Simulation time 40230999 ps
CPU time 0.89 seconds
Started Sep 01 09:40:03 AM UTC 24
Finished Sep 01 09:40:05 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075735108 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1075735108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.3117463299
Short name T479
Test name
Test status
Simulation time 2627587417 ps
CPU time 82.12 seconds
Started Sep 01 09:39:29 AM UTC 24
Finished Sep 01 09:40:53 AM UTC 24
Peak memory 217800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117463299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3117463299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.3504869306
Short name T157
Test name
Test status
Simulation time 172359038 ps
CPU time 11.9 seconds
Started Sep 01 09:39:42 AM UTC 24
Finished Sep 01 09:39:55 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504869306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3504869306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.3408978779
Short name T510
Test name
Test status
Simulation time 11309711179 ps
CPU time 1032.16 seconds
Started Sep 01 09:39:29 AM UTC 24
Finished Sep 01 09:56:52 AM UTC 24
Peak memory 735516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408978779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3408978779
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_error.274519014
Short name T473
Test name
Test status
Simulation time 450621706 ps
CPU time 12.27 seconds
Started Sep 01 09:39:49 AM UTC 24
Finished Sep 01 09:40:02 AM UTC 24
Peak memory 207112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274519014 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.274519014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2208754452
Short name T492
Test name
Test status
Simulation time 23947799284 ps
CPU time 195.45 seconds
Started Sep 01 09:39:24 AM UTC 24
Finished Sep 01 09:42:43 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208754452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2208754452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_smoke.2981724825
Short name T470
Test name
Test status
Simulation time 3540724639 ps
CPU time 21.31 seconds
Started Sep 01 09:39:19 AM UTC 24
Finished Sep 01 09:39:42 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981724825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2981724825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1804388190
Short name T532
Test name
Test status
Simulation time 136419254086 ps
CPU time 4680.14 seconds
Started Sep 01 09:39:56 AM UTC 24
Finished Sep 01 10:58:42 AM UTC 24
Peak memory 852152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804388190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1804388190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.1499304234
Short name T483
Test name
Test status
Simulation time 4967198482 ps
CPU time 89.98 seconds
Started Sep 01 09:39:52 AM UTC 24
Finished Sep 01 09:41:23 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499304234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1499304234
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_alert_test.753368279
Short name T169
Test name
Test status
Simulation time 18852275 ps
CPU time 0.91 seconds
Started Sep 01 09:16:09 AM UTC 24
Finished Sep 01 09:16:11 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753368279 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.753368279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.1287777342
Short name T182
Test name
Test status
Simulation time 1188966289 ps
CPU time 84.54 seconds
Started Sep 01 09:15:53 AM UTC 24
Finished Sep 01 09:17:20 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287777342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1287777342
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3261658041
Short name T71
Test name
Test status
Simulation time 34428477611 ps
CPU time 56.3 seconds
Started Sep 01 09:15:56 AM UTC 24
Finished Sep 01 09:16:54 AM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261658041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3261658041
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.2681234811
Short name T276
Test name
Test status
Simulation time 2693048224 ps
CPU time 545.51 seconds
Started Sep 01 09:15:54 AM UTC 24
Finished Sep 01 09:25:06 AM UTC 24
Peak memory 721252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681234811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2681234811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_error.1095187869
Short name T136
Test name
Test status
Simulation time 11633972624 ps
CPU time 156.66 seconds
Started Sep 01 09:15:56 AM UTC 24
Finished Sep 01 09:18:35 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095187869 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1095187869
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_long_msg.2263432705
Short name T122
Test name
Test status
Simulation time 483284799 ps
CPU time 17.42 seconds
Started Sep 01 09:15:52 AM UTC 24
Finished Sep 01 09:16:11 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263432705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2263432705
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_smoke.2689366000
Short name T139
Test name
Test status
Simulation time 181811123 ps
CPU time 3.31 seconds
Started Sep 01 09:15:52 AM UTC 24
Finished Sep 01 09:15:57 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689366000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2689366000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_stress_all.2203062674
Short name T431
Test name
Test status
Simulation time 94284328611 ps
CPU time 1239.02 seconds
Started Sep 01 09:16:01 AM UTC 24
Finished Sep 01 09:36:53 AM UTC 24
Peak memory 774368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203062674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2203062674
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.970750840
Short name T161
Test name
Test status
Simulation time 11541810465 ps
CPU time 97.96 seconds
Started Sep 01 09:15:57 AM UTC 24
Finished Sep 01 09:17:37 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970750840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.970750840
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_alert_test.778542180
Short name T174
Test name
Test status
Simulation time 14544563 ps
CPU time 0.87 seconds
Started Sep 01 09:16:28 AM UTC 24
Finished Sep 01 09:16:30 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778542180 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.778542180
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.3025084573
Short name T21
Test name
Test status
Simulation time 5197370874 ps
CPU time 48.51 seconds
Started Sep 01 09:16:12 AM UTC 24
Finished Sep 01 09:17:02 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025084573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3025084573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.1056828037
Short name T44
Test name
Test status
Simulation time 911602904 ps
CPU time 49.87 seconds
Started Sep 01 09:16:16 AM UTC 24
Finished Sep 01 09:17:08 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056828037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1056828037
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1455729277
Short name T165
Test name
Test status
Simulation time 2578553971 ps
CPU time 100.99 seconds
Started Sep 01 09:16:14 AM UTC 24
Finished Sep 01 09:17:57 AM UTC 24
Peak memory 415968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455729277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1455729277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_error.1976711877
Short name T205
Test name
Test status
Simulation time 9779025333 ps
CPU time 178.2 seconds
Started Sep 01 09:16:22 AM UTC 24
Finished Sep 01 09:19:24 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976711877 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1976711877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_long_msg.667772922
Short name T173
Test name
Test status
Simulation time 727735718 ps
CPU time 14.63 seconds
Started Sep 01 09:16:12 AM UTC 24
Finished Sep 01 09:16:27 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667772922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.667772922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_smoke.421887690
Short name T138
Test name
Test status
Simulation time 267964389 ps
CPU time 11.05 seconds
Started Sep 01 09:16:10 AM UTC 24
Finished Sep 01 09:16:23 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421887690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.421887690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_stress_all.1117798075
Short name T76
Test name
Test status
Simulation time 499193540772 ps
CPU time 1440.74 seconds
Started Sep 01 09:16:25 AM UTC 24
Finished Sep 01 09:40:42 AM UTC 24
Peak memory 536860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117798075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1117798075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.3462836868
Short name T113
Test name
Test status
Simulation time 91786167264 ps
CPU time 77.07 seconds
Started Sep 01 09:16:23 AM UTC 24
Finished Sep 01 09:17:42 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462836868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3462836868
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_alert_test.2511205189
Short name T72
Test name
Test status
Simulation time 16718267 ps
CPU time 0.88 seconds
Started Sep 01 09:16:52 AM UTC 24
Finished Sep 01 09:16:54 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511205189 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2511205189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.3828270973
Short name T29
Test name
Test status
Simulation time 1702740809 ps
CPU time 30.2 seconds
Started Sep 01 09:16:33 AM UTC 24
Finished Sep 01 09:17:05 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828270973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3828270973
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.2737466231
Short name T160
Test name
Test status
Simulation time 1835554283 ps
CPU time 27.76 seconds
Started Sep 01 09:16:38 AM UTC 24
Finished Sep 01 09:17:07 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737466231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2737466231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.1383426931
Short name T429
Test name
Test status
Simulation time 19845812706 ps
CPU time 1191.43 seconds
Started Sep 01 09:16:36 AM UTC 24
Finished Sep 01 09:36:41 AM UTC 24
Peak memory 688528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383426931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1383426931
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_error.2028160315
Short name T137
Test name
Test status
Simulation time 10897905604 ps
CPU time 155.4 seconds
Started Sep 01 09:16:44 AM UTC 24
Finished Sep 01 09:19:22 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028160315 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2028160315
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_long_msg.1238512347
Short name T193
Test name
Test status
Simulation time 2068639840 ps
CPU time 129.74 seconds
Started Sep 01 09:16:31 AM UTC 24
Finished Sep 01 09:18:44 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238512347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1238512347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_smoke.635279440
Short name T53
Test name
Test status
Simulation time 934409009 ps
CPU time 16.46 seconds
Started Sep 01 09:16:28 AM UTC 24
Finished Sep 01 09:16:46 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635279440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.635279440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_stress_all.4132052602
Short name T499
Test name
Test status
Simulation time 20649653689 ps
CPU time 1791.61 seconds
Started Sep 01 09:16:47 AM UTC 24
Finished Sep 01 09:46:58 AM UTC 24
Peak memory 757992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132052602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.4132052602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.3121470356
Short name T65
Test name
Test status
Simulation time 26276307616 ps
CPU time 584.05 seconds
Started Sep 01 09:16:47 AM UTC 24
Finished Sep 01 09:26:39 AM UTC 24
Peak memory 651664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31214703
56 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3121470356
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3541646380
Short name T114
Test name
Test status
Simulation time 8433389382 ps
CPU time 119.53 seconds
Started Sep 01 09:16:46 AM UTC 24
Finished Sep 01 09:18:48 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541646380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3541646380
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1982806288
Short name T179
Test name
Test status
Simulation time 36900660 ps
CPU time 0.88 seconds
Started Sep 01 09:17:09 AM UTC 24
Finished Sep 01 09:17:11 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982806288 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1982806288
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.2804210450
Short name T45
Test name
Test status
Simulation time 1531161125 ps
CPU time 62.66 seconds
Started Sep 01 09:16:55 AM UTC 24
Finished Sep 01 09:18:00 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804210450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2804210450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.3069786564
Short name T163
Test name
Test status
Simulation time 1406626486 ps
CPU time 37.62 seconds
Started Sep 01 09:17:00 AM UTC 24
Finished Sep 01 09:17:39 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069786564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3069786564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.2053226298
Short name T277
Test name
Test status
Simulation time 4306894888 ps
CPU time 490.16 seconds
Started Sep 01 09:16:55 AM UTC 24
Finished Sep 01 09:25:11 AM UTC 24
Peak memory 727320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053226298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2053226298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_error.2729453069
Short name T48
Test name
Test status
Simulation time 850474265 ps
CPU time 57.23 seconds
Started Sep 01 09:17:02 AM UTC 24
Finished Sep 01 09:18:01 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729453069 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2729453069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_long_msg.2527277105
Short name T185
Test name
Test status
Simulation time 3392922680 ps
CPU time 55.32 seconds
Started Sep 01 09:16:55 AM UTC 24
Finished Sep 01 09:17:52 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527277105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2527277105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_smoke.2584336712
Short name T181
Test name
Test status
Simulation time 1036683120 ps
CPU time 23.8 seconds
Started Sep 01 09:16:54 AM UTC 24
Finished Sep 01 09:17:19 AM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584336712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2584336712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_stress_all.2519697309
Short name T283
Test name
Test status
Simulation time 98703442925 ps
CPU time 501.57 seconds
Started Sep 01 09:17:05 AM UTC 24
Finished Sep 01 09:25:33 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519697309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2519697309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.1590853181
Short name T24
Test name
Test status
Simulation time 27476682559 ps
CPU time 273.25 seconds
Started Sep 01 09:17:06 AM UTC 24
Finished Sep 01 09:21:43 AM UTC 24
Peak memory 682520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15908531
81 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1590853181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.2319150255
Short name T183
Test name
Test status
Simulation time 1674986181 ps
CPU time 31.99 seconds
Started Sep 01 09:17:03 AM UTC 24
Finished Sep 01 09:17:37 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319150255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2319150255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_alert_test.446659615
Short name T184
Test name
Test status
Simulation time 38704072 ps
CPU time 0.86 seconds
Started Sep 01 09:17:37 AM UTC 24
Finished Sep 01 09:17:39 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446659615 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.446659615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.427475040
Short name T195
Test name
Test status
Simulation time 21416210543 ps
CPU time 92.48 seconds
Started Sep 01 09:17:11 AM UTC 24
Finished Sep 01 09:18:46 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427475040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.427475040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.87231770
Short name T264
Test name
Test status
Simulation time 2650370495 ps
CPU time 407.29 seconds
Started Sep 01 09:17:13 AM UTC 24
Finished Sep 01 09:24:05 AM UTC 24
Peak memory 514476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87231770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.87231770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_error.149074710
Short name T232
Test name
Test status
Simulation time 16369871783 ps
CPU time 268.44 seconds
Started Sep 01 09:17:17 AM UTC 24
Finished Sep 01 09:21:50 AM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149074710 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.149074710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_long_msg.3964820360
Short name T212
Test name
Test status
Simulation time 11234736701 ps
CPU time 167.19 seconds
Started Sep 01 09:17:11 AM UTC 24
Finished Sep 01 09:20:01 AM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964820360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3964820360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_smoke.3369054507
Short name T180
Test name
Test status
Simulation time 752678301 ps
CPU time 6.64 seconds
Started Sep 01 09:17:09 AM UTC 24
Finished Sep 01 09:17:17 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369054507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3369054507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1969939089
Short name T124
Test name
Test status
Simulation time 35237366891 ps
CPU time 1374.7 seconds
Started Sep 01 09:17:22 AM UTC 24
Finished Sep 01 09:40:33 AM UTC 24
Peak memory 700724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969939089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1969939089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.586446262
Short name T115
Test name
Test status
Simulation time 8858366693 ps
CPU time 147.24 seconds
Started Sep 01 09:17:19 AM UTC 24
Finished Sep 01 09:19:50 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586446262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.586446262
Directory /workspaces/repo/scratch/os_regression_2024_08_31/hmac-sim-vcs/9.hmac_wipe_secret/latest
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