Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17570938	1			T1	3077		T2	2557		T3	5368
all_values[1]	17570938	1			T1	3077		T2	2557		T3	5368
all_values[2]	17570938	1			T1	3077		T2	2557		T3	5368

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290842

1

T2

139

T5

32

T19

25

auto[1]

52421972

1

T1

9231

T2

7532

T3

16104

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44962185

1

T1

8878

T2

6846

T3

13295

auto[1]

7750629

1

T1

353

T2

825

T3

2809

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	108431	1			T11	1250		T7	1		T8	4
all_values[0]	auto[0]	auto[1]	313	1			T11	8		T8	3		T130	2
all_values[0]	auto[1]	auto[0]	17443337	1			T1	3070		T2	2523		T3	5353
all_values[0]	auto[1]	auto[1]	18857	1			T1	7		T2	34		T3	15
all_values[1]	auto[0]	auto[0]	70965	1			T131	2		T132	53		T11	522
all_values[1]	auto[0]	auto[1]	149	1			T8	1		T62	4		T129	2
all_values[1]	auto[1]	auto[0]	17499543	1			T1	3077		T2	2557		T3	5368
all_values[1]	auto[1]	auto[1]	281	1			T23	3		T24	4		T55	5
all_values[2]	auto[0]	auto[0]	70292	1			T2	35		T5	4		T19	3
all_values[2]	auto[0]	auto[1]	40692	1			T2	104		T5	28		T19	22
all_values[2]	auto[1]	auto[0]	9769617	1			T1	2731		T2	1731		T3	2574
all_values[2]	auto[1]	auto[1]	7690337	1			T1	346		T2	687		T3	2794