Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100753

1

T1

4

T2

56

T3

6

auto[1]

103928

1

T1

6

T2

32

T3

10

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	77463	1			T1	3		T2	1		T3	7
len_1026_2046	3800	1			T5	168		T6	13		T18	2
len_514_1022	4144	1			T5	52		T6	10		T21	1
len_2_510	3961	1			T2	1		T5	19		T6	7
len_2056	158	1			T2	4		T4	1		T7	2
len_2048	282	1			T2	1		T5	1		T6	2
len_2040	159	1			T2	8		T7	1		T147	1
len_1032	153	1			T2	4		T67	1		T147	1
len_1024	1782	1			T2	1		T4	2		T10	96
len_1016	152	1			T2	4		T132	1		T7	4
len_520	170	1			T2	3		T67	1		T130	3
len_512	323	1			T2	9		T3	1		T5	2
len_504	159	1			T2	2		T67	2		T68	1
len_8	1067	1			T131	3		T31	5		T34	2
len_0	8567	1			T1	2		T2	6		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

129

1

T2

1

T20

2

T148

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	38630	1			T1	2		T2	1		T3	2
auto[0]	len_1026_2046	1821	1			T5	154		T6	13		T18	1
auto[0]	len_514_1022	2704	1			T5	15		T6	8		T23	5
auto[0]	len_2_510	2409	1			T2	1		T5	10		T6	7
auto[0]	len_2056	86	1			T2	3		T4	1		T8	1
auto[0]	len_2048	165	1			T6	2		T148	1		T132	1
auto[0]	len_2040	80	1			T2	7		T7	1		T130	5
auto[0]	len_1032	73	1			T2	2		T67	1		T147	1
auto[0]	len_1024	243	1			T2	1		T4	2		T5	1
auto[0]	len_1016	81	1			T2	1		T132	1		T7	3
auto[0]	len_520	89	1			T2	2		T130	2		T149	3
auto[0]	len_512	202	1			T2	4		T3	1		T5	1
auto[0]	len_504	88	1			T2	1		T68	1		T89	1
auto[0]	len_8	17	1			T34	2		T89	2		T150	2
auto[0]	len_0	3688	1			T2	5		T4	1		T5	55
auto[1]	len_2050_plus	38833	1			T1	1		T3	5		T5	530
auto[1]	len_1026_2046	1979	1			T5	14		T18	1		T23	6
auto[1]	len_514_1022	1440	1			T5	37		T6	2		T21	1
auto[1]	len_2_510	1552	1			T5	9		T20	1		T146	1
auto[1]	len_2056	72	1			T2	1		T7	2		T130	3
auto[1]	len_2048	117	1			T2	1		T5	1		T18	1
auto[1]	len_2040	79	1			T2	1		T147	1		T130	3
auto[1]	len_1032	80	1			T2	2		T151	1		T152	1
auto[1]	len_1024	1539	1			T10	96		T5	4		T17	75
auto[1]	len_1016	71	1			T2	3		T7	1		T153	1
auto[1]	len_520	81	1			T2	1		T67	1		T130	1
auto[1]	len_512	121	1			T2	5		T5	1		T7	1
auto[1]	len_504	71	1			T2	1		T67	2		T130	1
auto[1]	len_8	1050	1			T131	3		T31	5		T154	15
auto[1]	len_0	4879	1			T1	2		T2	1		T5	159

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

70

1

T2

1

T148

2

T11

3

auto[1]

len_upper

59

1

T20

2

T31

1

T49

1