Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::save_and_restore_cg

Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	9	0	9	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size_cp	3	0	3	100.00	100	1	1	0
save_and_restore_cp	3	0	3	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sar_type_x_digest_size	9	0	9	100.00	100	1	1	0

Summary for Variable digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for digest_size_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	236	1			T5	1		T18	3		T20	3
sha2_384	206	1			T2	1		T3	1		T18	1
sha2_256	215	1			T2	1		T3	3		T6	1

---

Summary for Variable save_and_restore_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for save_and_restore_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	216	1			T3	2		T18	1		T20	1
different_context	213	1			T2	1		T18	2		T20	1
same_context	228	1			T2	1		T3	2		T5	1

---

Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	9	0	9	100.00

Automatically Generated Cross Bins for sar_type_x_digest_size

Bins

save_and_restore_cp	digest_size_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	sha2_512	77	1			T18	1		T20	1		T11	1
stop_and_continue	sha2_384	68	1			T3	1		T45	1		T49	1
stop_and_continue	sha2_256	71	1			T3	1		T45	1		T155	2
different_context	sha2_512	76	1			T18	1		T20	1		T31	1
different_context	sha2_384	74	1			T18	1		T148	1		T146	1
different_context	sha2_256	63	1			T2	1		T11	2		T49	1
same_context	sha2_512	83	1			T5	1		T18	1		T20	1
same_context	sha2_384	64	1			T2	1		T156	1		T157	1
same_context	sha2_256	81	1			T3	2		T6	1		T18	2