Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4482333

1

T1

605

T2

493

T3

7

auto[1]

2642633

1

T1

811

T2

713

T3

10

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2661975

1

T1

383

T2

624

T3

11

auto[1]

4462991

1

T1

1033

T2

582

T3

6

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3134891

1

T1

940

T2

761

T3

5

auto[1]

3990075

1

T1

476

T2

445

T3

12

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4427294

1

T1

1368

T2

710

T3

8

auto[1]

2697672

1

T1

48

T2

496

T3

9

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6451304	1			T1	1131		T2	1178		T3	11
fifo_depth[1]	112743	1			T1	42		T2	15		T4	4
fifo_depth[2]	84110	1			T1	40		T2	9		T4	4
fifo_depth[3]	68131	1			T1	43		T2	4		T4	1
fifo_depth[4]	61672	1			T1	49		T4	3		T10	16
fifo_depth[5]	49628	1			T1	37		T4	3		T10	6
fifo_depth[6]	40553	1			T1	32		T3	1		T10	1
fifo_depth[7]	27215	1			T1	24		T3	1		T4	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673662

1

T1

285

T2

28

T3

6

auto[1]

6451304

1

T1

1131

T2

1178

T3

11

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7115808

1

T1

1416

T2

1206

T3

17

auto[1]

9158

1

T23

203

T24

653

T55

100

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

30631

1

T2

2

T3

1

T4

10

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

32451

1

T2

2

T3

1

T21

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

23744

1

T1

68

T2

2

T19

137

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21726

1

T2

1

T3

1

T20

70

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

136279

1

T1

93

T5

32

T18

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

41836

1

T20

31

T148

2

T146

19

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

31529

1

T2

1

T4

6

T5

14

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27484

1

T5

5

T18

1

T19

66

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53924

1

T2

2

T5

1

T20

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36534

1

T3

1

T5

12

T19

80

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

29619

1

T2

2

T5

9

T31

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29325

1

T1

16

T2

1

T21

14

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36001

1

T2

7

T10

338

T5

15

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

53607

1

T2

2

T5

2

T6

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

49505

1

T1

108

T2

3

T3

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

39467

1

T2

3

T5

26

T11

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

158884

1

T2

101

T3

1

T4

33

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

143868

1

T1

1

T2

60

T6

52

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

151256

1

T1

268

T2

108

T19

388

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

160746

1

T2

143

T4

10

T5

218

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1719165

1

T1

510

T2

141

T4

47

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

143905

1

T2

66

T5

679

T18

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

151319

1

T2

101

T4

61

T5

2006

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

160068

1

T2

33

T3

1

T5

185

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

487311

1

T2

23

T5

30

T19

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

432358

1

T2

28

T3

3

T5

888

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

419105

1

T2

104

T3

2

T4

51

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

450493

1

T1

30

T2

45

T3

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

497934

1

T2

42

T10

3894

T5

729

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

477645

1

T1

1

T2

17

T5

31

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

451088

1

T1

321

T2

71

T3

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

446159

1

T2

95

T3

1

T5

292

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

188932

1

T2

103

T3

2

T4

43

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

175902

1

T1

1

T2

62

T3

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

173923

1

T1

336

T2

110

T19

525

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

181707

1

T2

144

T3

1

T4

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1855111

1

T1

603

T2

141

T4

47

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

184263

1

T2

66

T5

679

T18

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

182054

1

T2

102

T4

67

T5

2020

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

186973

1

T2

33

T3

1

T5

190

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

541034

1

T2

25

T5

31

T19

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

468105

1

T2

28

T3

4

T5

900

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

448478

1

T2

106

T3

2

T4

51

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

479370

1

T1

46

T2

46

T3

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

533504

1

T2

49

T10

4232

T5

744

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

530899

1

T1

1

T2

19

T5

33

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

500013

1

T1

429

T2

74

T3

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

485540

1

T2

98

T3

1

T5

318

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

583

1

T24

3

T46

3

T47

132

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

417

1

T24

7

T55

85

T158

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1077

1

T24

168

T159

23

T47

88

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

765

1

T55

11

T160

2

T161

16

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

333

1

T23

2

T24

4

T47

36

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1478

1

T23

194

T24

6

T55

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

794

1

T24

54

T55

1

T162

66

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

579

1

T24

5

T46

51

T162

41

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

201

1

T23

4

T24

80

T158

12

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

787

1

T159

471

T47

11

T62

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

246

1

T162

1

T163

4

T100

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

448

1

T46

5

T159

88

T164

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

431

1

T47

3

T48

2

T165

358

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

353

1

T24

1

T46

4

T159

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

580

1

T24

292

T159

1

T162

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

86

1

T23

3

T24

33

T46

11

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

158884

1

T2

101

T3

1

T4

33

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

143868

1

T1

1

T2

60

T6

52

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

151256

1

T1

268

T2

108

T19

388

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

160746

1

T2

143

T4

10

T5

218

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1719165

1

T1

510

T2

141

T4

47

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

143905

1

T2

66

T5

679

T18

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

151319

1

T2

101

T4

61

T5

2006

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

160068

1

T2

33

T3

1

T5

185

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

487311

1

T2

23

T5

30

T19

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

432358

1

T2

28

T3

3

T5

888

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

419105

1

T2

104

T3

2

T4

51

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

450493

1

T1

30

T2

45

T3

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

497934

1

T2

42

T10

3894

T5

729

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

477645

1

T1

1

T2

17

T5

31

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

451088

1

T1

321

T2

71

T3

2

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

446159

1

T2

95

T3

1

T5

292

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

2943

1

T4

3

T5

14

T6

5

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3200

1

T2

1

T21

4

T148

4

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3361

1

T1

10

T2

1

T19

34

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3362

1

T2

1

T20

42

T148

36

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

37129

1

T1

16

T5

6

T21

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3198

1

T20

22

T148

1

T146

14

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3622

1

T2

1

T4

1

T5

14

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3406

1

T5

1

T19

22

T132

2

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

7699

1

T2

1

T5

1

T20

10

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5567

1

T19

23

T20

14

T21

12

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5309

1

T2

2

T5

1

T31

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

4911

1

T1

1

T21

14

T148

9

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7159

1

T2

3

T10

136

T5

4

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7523

1

T2

2

T6

2

T20

44

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

7577

1

T1

15

T2

2

T19

9

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6777

1

T2

1

T5

1

T23

9

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2229

1

T2

2

T4

4

T5

11

fifo_depth[2]

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auto[0]

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2478

1

T2

1

T148

1

T25

21

fifo_depth[2]

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auto[0]

auto[1]

auto[0]

2602

1

T1

10

T2

1

T19

31

fifo_depth[2]

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auto[1]

2304

1

T20

19

T148

6

T146

13

fifo_depth[2]

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auto[0]

auto[0]

24025

1

T1

14

T5

6

T21

3

fifo_depth[2]

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auto[0]

auto[1]

2547

1

T20

7

T148

1

T146

5

fifo_depth[2]

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auto[1]

auto[0]

2787

1

T6

1

T146

10

T67

2

fifo_depth[2]

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auto[1]

auto[1]

2786

1

T5

2

T19

28

T146

9

fifo_depth[2]

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auto[0]

auto[0]

6621

1

T2

1

T20

4

T21

2

fifo_depth[2]

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auto[0]

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4609

1

T5

5

T19

17

T20

12

fifo_depth[2]

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auto[1]

auto[0]

4113

1

T5

2

T7

28

T45

1

fifo_depth[2]

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auto[0]

auto[1]

auto[1]

4056

1

T2

1

T148

1

T23

3

fifo_depth[2]

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auto[1]

auto[0]

auto[0]

5268

1

T2

1

T10

115

T5

3

fifo_depth[2]

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auto[1]

auto[0]

auto[1]

6261

1

T6

1

T20

27

T148

2

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

5908

1

T1

16

T2

1

T19

12

fifo_depth[2]

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auto[1]

auto[1]

auto[1]

5516

1

T2

1

T5

10

T23

8

fifo_depth[3]

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auto[0]

auto[0]

auto[0]

1531

1

T5

1

T6

2

T19

10

fifo_depth[3]

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auto[0]

auto[0]

auto[1]

1990

1

T25

12

T94

2

T24

33

fifo_depth[3]

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auto[0]

auto[1]

auto[0]

1979

1

T1

8

T19

30

T21

2

fifo_depth[3]

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auto[0]

auto[1]

auto[1]

1795

1

T20

9

T148

1

T146

5

fifo_depth[3]

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auto[1]

auto[0]

auto[0]

18231

1

T1

15

T5

6

T18

1

fifo_depth[3]

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auto[0]

auto[1]

2123

1

T20

1

T23

7

T25

10

fifo_depth[3]

auto[0]

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auto[1]

auto[0]

2197

1

T4

1

T146

4

T45

60

fifo_depth[3]

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auto[1]

auto[1]

2125

1

T19

13

T132

3

T146

2

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

6034

1

T20

1

T51

22

T23

15

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

3847

1

T19

10

T146

2

T7

20

fifo_depth[3]

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auto[0]

auto[1]

auto[0]

3464

1

T7

32

T130

2

T166

45

fifo_depth[3]

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auto[1]

auto[1]

3479

1

T1

4

T31

14

T7

16

fifo_depth[3]

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auto[1]

auto[0]

auto[0]

4221

1

T2

3

T10

64

T5

2

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

5459

1

T20

8

T148

1

T146

1

fifo_depth[3]

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auto[1]

auto[1]

auto[0]

5119

1

T1

16

T19

9

T20

2

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

4537

1

T2

1

T5

1

T23

9

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

1609

1

T4

2

T5

1

T6

2

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

1943

1

T25

19

T45

1

T167

14

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

1855

1

T1

15

T19

21

T21

1

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

1676

1

T45

24

T8

5

T94

1

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

14054

1

T1

13

T5

5

T23

6

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

2101

1

T20

1

T23

11

T25

11

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[0]

2006

1

T4

1

T11

1

T45

59

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

2023

1

T5

1

T19

3

T25

22

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

5654

1

T51

12

T23

2

T25

13

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

3799

1

T5

7

T19

8

T7

10

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

3243

1

T5

5

T31

2

T7

30

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

3117

1

T1

2

T31

15

T7

8

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

3849

1

T10

16

T5

3

T20

1

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

5602

1

T5

2

T6

3

T20

1

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4808

1

T1

19

T19

3

T20

2

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

4333

1

T5

12

T23

43

T7

23

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1184

1

T4

1

T6

3

T19

10

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1517

1

T25

14

T45

1

T49

1

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1483

1

T1

11

T19

15

T23

2

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1366

1

T45

21

T8

3

T155

30

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

10125

1

T1

12

T5

5

T23

4

fifo_depth[5]

auto[0]

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auto[0]

auto[1]

1597

1

T23

9

T25

12

T45

17

fifo_depth[5]

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auto[0]

1619

1

T4

2

T11

1

T45

67

fifo_depth[5]

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auto[1]

auto[1]

1536

1

T132

4

T25

20

T155

1

fifo_depth[5]

auto[1]

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auto[0]

auto[0]

4755

1

T51

3

T23

15

T25

14

fifo_depth[5]

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auto[0]

auto[1]

3180

1

T19

11

T7

6

T45

65

fifo_depth[5]

auto[1]

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auto[1]

auto[0]

2780

1

T7

27

T166

38

T168

1

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[1]

2717

1

T31

13

T7

1

T45

3

fifo_depth[5]

auto[1]

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auto[0]

auto[0]

3149

1

T10

6

T5

2

T32

114

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

4716

1

T20

1

T25

20

T31

38

fifo_depth[5]

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auto[1]

auto[0]

4166

1

T1

14

T31

7

T45

19

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[1]

3738

1

T23

48

T7

16

T167

1

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1039

1

T19

6

T51

6

T45

18

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

1416

1

T25

13

T45

1

T24

5

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1138

1

T1

5

T19

6

T23

8

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1112

1

T45

11

T8

2

T155

24

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

7632

1

T1

11

T5

2

T23

31

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1289

1

T23

9

T25

10

T45

15

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[0]

1329

1

T45

53

T167

6

T155

41

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[1]

1237

1

T5

1

T18

1

T132

2

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

3825

1

T23

1

T25

17

T7

10

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2593

1

T19

6

T7

5

T45

57

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2172

1

T5

1

T31

2

T7

28

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

2171

1

T1

5

T31

13

T45

9

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

2596

1

T10

1

T5

1

T32

62

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

4297

1

T6

1

T20

1

T25

18

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

3464

1

T1

11

T3

1

T18

1

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

3243

1

T5

1

T23

136

T7

2

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

665

1

T6

1

T45

17

T155

5

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

1167

1

T25

6

T24

33

T169

1

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

822

1

T1

4

T23

5

T25

10

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

748

1

T45

15

T8

3

T155

6

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

4534

1

T1

9

T5

2

T23

36

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

785

1

T23

12

T25

4

T45

3

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

962

1

T4

1

T45

34

T167

4

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

863

1

T132

2

T25

8

T156

1

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

2623

1

T23

14

T25

8

T7

3

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1889

1

T3

1

T19

5

T45

44

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1446

1

T7

14

T166

6

T159

8

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

1515

1

T1

2

T31

5

T45

9

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

1732

1

T32

27

T7

2

T45

5

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

2926

1

T25

5

T31

29

T7

43

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

2421

1

T1

9

T31

6

T45

9

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

2117

1

T23

131

T7

3

T154

9