Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17570938	1			T1	3077		T2	2557		T3	5368
all_pins[1]	17570938	1			T1	3077		T2	2557		T3	5368
all_pins[2]	17570938	1			T1	3077		T2	2557		T3	5368

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45002421	1			T1	8877		T2	6950		T3	13290
values[0x1]	7710393	1			T1	354		T2	721		T3	2814
transitions[0x0=>0x1]	7710259	1			T1	354		T2	721		T3	2814
transitions[0x1=>0x0]	7710269	1			T1	354		T2	721		T3	2814

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17551191	1			T1	3069		T2	2523		T3	5348
all_pins[0]	values[0x1]	19747	1			T1	8		T2	34		T3	20
all_pins[0]	transitions[0x0=>0x1]	19695	1			T1	8		T2	34		T3	20
all_pins[0]	transitions[0x1=>0x0]	7690295	1			T1	346		T2	687		T3	2794
all_pins[1]	values[0x0]	17570629	1			T1	3077		T2	2557		T3	5368
all_pins[1]	values[0x1]	309	1			T23	3		T24	5		T55	6
all_pins[1]	transitions[0x0=>0x1]	265	1			T23	3		T24	5		T55	6
all_pins[1]	transitions[0x1=>0x0]	19703	1			T1	8		T2	34		T3	20
all_pins[2]	values[0x0]	9880601	1			T1	2731		T2	1870		T3	2574
all_pins[2]	values[0x1]	7690337	1			T1	346		T2	687		T3	2794
all_pins[2]	transitions[0x0=>0x1]	7690299	1			T1	346		T2	687		T3	2794
all_pins[2]	transitions[0x1=>0x0]	271	1			T23	3		T24	5		T55	6