Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 678 1 T8 7 T62 15 T22 4
all_values[1] 678 1 T8 7 T62 15 T22 4
all_values[2] 678 1 T8 7 T62 15 T22 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1050 1 T8 10 T62 18 T22 4
auto[1] 984 1 T8 11 T62 27 T22 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 628 1 T8 7 T62 9 T22 4
auto[1] 1406 1 T8 14 T62 36 T22 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1097 1 T8 13 T62 23 T22 7
auto[1] 937 1 T8 8 T62 22 T22 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 131 1 T8 1 T62 1 T22 1
all_values[0] auto[0] auto[0] auto[1] 63 1 T8 2 T62 3 T22 1
all_values[0] auto[0] auto[1] auto[0] 111 1 T62 3 T129 1 T133 5
all_values[0] auto[0] auto[1] auto[1] 68 1 T8 1 T62 2 T133 1
all_values[0] auto[1] auto[0] auto[1] 148 1 T62 2 T129 4 T133 4
all_values[0] auto[1] auto[1] auto[1] 157 1 T8 3 T62 4 T22 2
all_values[1] auto[0] auto[0] auto[0] 109 1 T62 1 T129 2 T133 1
all_values[1] auto[0] auto[0] auto[1] 85 1 T8 1 T62 2 T129 1
all_values[1] auto[0] auto[1] auto[0] 73 1 T8 5 T62 2 T22 2
all_values[1] auto[0] auto[1] auto[1] 96 1 T62 2 T22 1 T129 2
all_values[1] auto[1] auto[0] auto[1] 155 1 T8 1 T62 4 T129 1
all_values[1] auto[1] auto[1] auto[1] 160 1 T62 4 T22 1 T129 4
all_values[2] auto[0] auto[0] auto[0] 87 1 T8 1 T62 2 T129 2
all_values[2] auto[0] auto[0] auto[1] 92 1 T8 1 T62 2 T22 1
all_values[2] auto[0] auto[1] auto[0] 117 1 T22 1 T129 2 T133 3
all_values[2] auto[0] auto[1] auto[1] 65 1 T8 1 T62 3 T134 2
all_values[2] auto[1] auto[0] auto[1] 180 1 T8 3 T62 1 T22 1
all_values[2] auto[1] auto[1] auto[1] 137 1 T8 1 T62 7 T22 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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