Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3891	1			T2	15		T3	6		T4	1
sha2_none	3897	1			T1	2		T2	6		T3	2
sha2_512	7174	1			T1	1		T2	10		T3	1
sha2_384	7078	1			T1	4		T2	9		T3	4
sha2_256	5922	1			T2	11		T3	6		T4	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17928

1

T1

4

T2

23

T3

8

auto[1]

10396

1

T1

3

T2

29

T3

11

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10293

1

T1

3

T2

26

T3

12

auto[1]

18031

1

T1

4

T2

26

T3

7

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14747

1

T1

3

T2

22

T3

13

disabled

13577

1

T1

4

T2

30

T3

6

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4199	1			T2	11		T3	4		T4	1
key_none	7598	1			T2	6		T4	3		T5	7
key_1024	3988	1			T1	3		T2	8		T3	4
key_512	3497	1			T1	1		T2	4		T3	2
key_384	3206	1			T1	1		T2	9		T3	3
key_256	2890	1			T1	1		T2	5		T3	2
key_128	2861	1			T1	1		T2	9		T3	4

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18033

1

T1

4

T2

28

T3

9

auto[1]

10291

1

T1

3

T2

24

T3

10

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28152

1

T1

7

T2

52

T3

19

disabled

172

1

T19

3

T51

1

T30

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1541

1

T2

2

T5

3

T19

2

enabled

auto[0]

auto[0]

auto[1]

1478

1

T2

3

T3

4

T5

7

enabled

auto[0]

auto[1]

auto[0]

1476

1

T2

3

T3

2

T4

2

enabled

auto[0]

auto[1]

auto[1]

1451

1

T1

1

T2

3

T3

1

enabled

auto[1]

auto[0]

auto[0]

4207

1

T2

2

T10

180

T5

4

enabled

auto[1]

auto[0]

auto[1]

1496

1

T1

1

T2

2

T5

4

enabled

auto[1]

auto[1]

auto[0]

1636

1

T1

1

T2

3

T3

5

enabled

auto[1]

auto[1]

auto[1]

1462

1

T2

4

T3

1

T5

5

disabled

auto[0]

auto[0]

auto[0]

1099

1

T2

3

T3

2

T4

1

disabled

auto[0]

auto[0]

auto[1]

1094

1

T1

1

T2

3

T3

2

disabled

auto[0]

auto[1]

auto[0]

1047

1

T1

1

T2

4

T6

1

disabled

auto[0]

auto[1]

auto[1]

1107

1

T2

5

T3

1

T4

1

disabled

auto[1]

auto[0]

auto[0]

5935

1

T1

2

T2

6

T4

1

disabled

auto[1]

auto[0]

auto[1]

1078

1

T2

2

T5

3

T18

2

disabled

auto[1]

auto[1]

auto[0]

1092

1

T2

5

T4

2

T5

2

disabled

auto[1]

auto[1]

auto[1]

1125

1

T2

2

T3

1

T5

7

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14661

1

T1

3

T2

22

T3

13

enabled

disabled

86

1

T19

1

T51

1

T30

1

disabled

disabled

86

1

T19

2

T7

1

T145

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13491

1

T1

4

T2

30

T3

6

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1033	1			T2	5		T6	1		T19	6
key_invalid	sha2_none	770	1			T2	1		T3	2		T6	1
key_invalid	sha2_512	751	1			T5	7		T6	2		T19	4
key_invalid	sha2_384	801	1			T2	4		T3	1		T5	2
key_invalid	sha2_256	743	1			T2	1		T3	1		T4	1
key_none	sha2_invalid	496	1			T2	3		T5	1		T18	4
key_none	sha2_none	506	1			T2	1		T4	2		T5	2
key_none	sha2_512	2481	1			T18	1		T21	1		T131	2
key_none	sha2_384	2515	1			T4	1		T5	2		T20	2
key_none	sha2_256	1541	1			T2	2		T5	1		T19	3
key_1024	sha2_invalid	423	1			T2	1		T3	2		T4	1
key_1024	sha2_none	515	1			T1	1		T2	1		T5	1
key_1024	sha2_512	1664	1			T2	4		T3	1		T5	1
key_1024	sha2_384	816	1			T1	2		T2	1		T3	1
key_512	sha2_invalid	448	1			T2	1		T5	2		T20	1
key_512	sha2_none	487	1			T6	1		T18	1		T146	1
key_512	sha2_512	594	1			T2	1		T18	1		T19	1
key_512	sha2_384	1167	1			T1	1		T3	1		T10	120
key_512	sha2_256	755	1			T2	2		T3	1		T4	1
key_384	sha2_invalid	482	1			T2	3		T3	3		T20	1
key_384	sha2_none	532	1			T1	1		T2	1		T5	4
key_384	sha2_512	540	1			T2	1		T19	1		T20	1
key_384	sha2_384	582	1			T2	3		T5	1		T6	3
key_384	sha2_256	1031	1			T2	1		T5	1		T17	90
key_256	sha2_invalid	491	1			T3	1		T5	1		T6	1
key_256	sha2_none	554	1			T2	1		T5	1		T6	1
key_256	sha2_512	577	1			T2	3		T5	3		T18	2
key_256	sha2_384	536	1			T1	1		T3	1		T5	2
key_256	sha2_256	707	1			T5	2		T6	2		T21	1
key_128	sha2_invalid	500	1			T2	2		T18	2		T19	1
key_128	sha2_none	513	1			T2	1		T6	1		T19	2
key_128	sha2_512	560	1			T1	1		T2	1		T5	1
key_128	sha2_384	639	1			T2	1		T4	1		T5	2
key_128	sha2_256	605	1			T2	4		T3	4		T5	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

528

1

T2

1

T5

2

T18

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1033	1			T2	5		T6	1		T19	6
key_invalid	sha2_none	770	1			T2	1		T3	2		T6	1
key_invalid	sha2_512	751	1			T5	7		T6	2		T19	4
key_invalid	sha2_384	801	1			T2	4		T3	1		T5	2
key_invalid	sha2_256	743	1			T2	1		T3	1		T4	1
key_none	sha2_invalid	496	1			T2	3		T5	1		T18	4
key_none	sha2_none	506	1			T2	1		T4	2		T5	2
key_none	sha2_512	2481	1			T18	1		T21	1		T131	2
key_none	sha2_384	2515	1			T4	1		T5	2		T20	2
key_none	sha2_256	1541	1			T2	2		T5	1		T19	3
key_1024	sha2_invalid	423	1			T2	1		T3	2		T4	1
key_1024	sha2_none	515	1			T1	1		T2	1		T5	1
key_1024	sha2_512	1664	1			T2	4		T3	1		T5	1
key_1024	sha2_384	816	1			T1	2		T2	1		T3	1
key_1024	sha2_256	528	1			T2	1		T5	2		T18	2
key_512	sha2_invalid	448	1			T2	1		T5	2		T20	1
key_512	sha2_none	487	1			T6	1		T18	1		T146	1
key_512	sha2_512	594	1			T2	1		T18	1		T19	1
key_512	sha2_384	1167	1			T1	1		T3	1		T10	120
key_512	sha2_256	755	1			T2	2		T3	1		T4	1
key_384	sha2_invalid	482	1			T2	3		T3	3		T20	1
key_384	sha2_none	532	1			T1	1		T2	1		T5	4
key_384	sha2_512	540	1			T2	1		T19	1		T20	1
key_384	sha2_384	582	1			T2	3		T5	1		T6	3
key_384	sha2_256	1031	1			T2	1		T5	1		T17	90
key_256	sha2_invalid	491	1			T3	1		T5	1		T6	1
key_256	sha2_none	554	1			T2	1		T5	1		T6	1
key_256	sha2_512	577	1			T2	3		T5	3		T18	2
key_256	sha2_384	536	1			T1	1		T3	1		T5	2
key_256	sha2_256	707	1			T5	2		T6	2		T21	1
key_128	sha2_invalid	500	1			T2	2		T18	2		T19	1
key_128	sha2_none	513	1			T2	1		T6	1		T19	2
key_128	sha2_512	560	1			T1	1		T2	1		T5	1
key_128	sha2_384	639	1			T2	1		T4	1		T5	2
key_128	sha2_256	605	1			T2	4		T3	4		T5	1