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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.45 95.40 97.17 100.00 100.00 98.27 98.48 99.85


Total test records in report: 656
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T117 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.3399209960 Sep 04 10:49:56 AM UTC 24 Sep 04 10:49:59 AM UTC 24 109067358 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.271643730 Sep 04 10:49:56 AM UTC 24 Sep 04 10:49:59 AM UTC 24 27399419 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.2990145307 Sep 04 10:49:56 AM UTC 24 Sep 04 10:49:59 AM UTC 24 85486333 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1576814334 Sep 04 10:49:56 AM UTC 24 Sep 04 10:49:59 AM UTC 24 26704764 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3402643760 Sep 04 10:49:56 AM UTC 24 Sep 04 10:49:59 AM UTC 24 241342404 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1492003101 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:00 AM UTC 24 679571539 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1778136398 Sep 04 10:49:58 AM UTC 24 Sep 04 10:50:00 AM UTC 24 136837228 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.763341123 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:01 AM UTC 24 626738038 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.720643705 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:01 AM UTC 24 97336129 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.3039769352 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:01 AM UTC 24 1453020761 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2043865128 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:01 AM UTC 24 820844185 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.199418347 Sep 04 10:49:59 AM UTC 24 Sep 04 10:50:01 AM UTC 24 19477403 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1028423991 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:02 AM UTC 24 131166105 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.2201699875 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:02 AM UTC 24 57683117 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.1388812318 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:02 AM UTC 24 247762345 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.636740685 Sep 04 10:49:59 AM UTC 24 Sep 04 10:50:02 AM UTC 24 170864271 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.672629601 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:02 AM UTC 24 356099351 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1121837563 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:02 AM UTC 24 77383933 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.629394113 Sep 04 10:49:59 AM UTC 24 Sep 04 10:50:03 AM UTC 24 99963170 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.916924346 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:03 AM UTC 24 63870186 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1243050365 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:03 AM UTC 24 83996662 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2416365724 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:03 AM UTC 24 226161268 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2350822076 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:03 AM UTC 24 22689824 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2707736286 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:04 AM UTC 24 63103215 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.3502675924 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:04 AM UTC 24 14348798 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2978839849 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:04 AM UTC 24 17841005 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1934214036 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:04 AM UTC 24 51282534 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1207271642 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:04 AM UTC 24 155512080 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.958201305 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:05 AM UTC 24 127816420 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2824951552 Sep 04 10:50:03 AM UTC 24 Sep 04 10:50:05 AM UTC 24 38347707 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3891374320 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:05 AM UTC 24 36579704 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.1957919646 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:05 AM UTC 24 441706628 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.2959382761 Sep 04 10:49:59 AM UTC 24 Sep 04 10:50:05 AM UTC 24 311683210 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3806928865 Sep 04 10:50:03 AM UTC 24 Sep 04 10:50:05 AM UTC 24 23489123 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1459814085 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:05 AM UTC 24 181017569 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.117851948 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:05 AM UTC 24 338534410 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.138112855 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:06 AM UTC 24 30939436 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3250885603 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:06 AM UTC 24 112401129 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1259466486 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:06 AM UTC 24 172627976 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2591962830 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:06 AM UTC 24 150160366 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1358097202 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:06 AM UTC 24 623659033 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.2036603944 Sep 04 10:49:57 AM UTC 24 Sep 04 10:50:06 AM UTC 24 2278499345 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1243431982 Sep 04 10:50:00 AM UTC 24 Sep 04 10:50:06 AM UTC 24 1219260160 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4221323259 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:06 AM UTC 24 105343094 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.4126483761 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:06 AM UTC 24 400614455 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.2784824994 Sep 04 10:50:03 AM UTC 24 Sep 04 10:50:07 AM UTC 24 596904048 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3634585378 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:07 AM UTC 24 220302796 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.3127688513 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:07 AM UTC 24 83198659 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.3168850432 Sep 04 10:50:05 AM UTC 24 Sep 04 10:50:07 AM UTC 24 17773236 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3541871682 Sep 04 10:49:57 AM UTC 24 Sep 04 10:50:07 AM UTC 24 1027148201 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3277864635 Sep 04 10:50:05 AM UTC 24 Sep 04 10:50:07 AM UTC 24 112057900 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2716678136 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:07 AM UTC 24 134026844 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1937415076 Sep 04 10:50:04 AM UTC 24 Sep 04 10:50:07 AM UTC 24 126176570 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.4037319864 Sep 04 10:50:03 AM UTC 24 Sep 04 10:50:07 AM UTC 24 286841291 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1168033883 Sep 04 10:50:03 AM UTC 24 Sep 04 10:50:08 AM UTC 24 193499355 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2078661683 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:08 AM UTC 24 73504473 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2378207732 Sep 04 10:50:05 AM UTC 24 Sep 04 10:50:08 AM UTC 24 197091635 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2621900333 Sep 04 10:50:02 AM UTC 24 Sep 04 10:50:08 AM UTC 24 289813487 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.353718474 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:08 AM UTC 24 24577482 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1734322592 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:08 AM UTC 24 13506477 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.567938599 Sep 04 10:50:07 AM UTC 24 Sep 04 10:50:08 AM UTC 24 60638682 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.369017231 Sep 04 10:50:05 AM UTC 24 Sep 04 10:50:08 AM UTC 24 442438964 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1927465085 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:09 AM UTC 24 34869721 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.2704412071 Sep 04 10:50:07 AM UTC 24 Sep 04 10:50:09 AM UTC 24 492746036 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.4175562745 Sep 04 10:50:05 AM UTC 24 Sep 04 10:50:09 AM UTC 24 196319677 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.1782219609 Sep 04 10:50:05 AM UTC 24 Sep 04 10:50:09 AM UTC 24 89682464 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.531259314 Sep 04 10:50:07 AM UTC 24 Sep 04 10:50:09 AM UTC 24 195617402 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1203955920 Sep 04 10:50:07 AM UTC 24 Sep 04 10:50:09 AM UTC 24 118207766 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.935115797 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:10 AM UTC 24 272598159 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2275637928 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:10 AM UTC 24 33709599 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.2201552084 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:10 AM UTC 24 33291713 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.940719127 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:10 AM UTC 24 38181293 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1675998028 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:10 AM UTC 24 29247365 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3545121891 Sep 04 10:50:07 AM UTC 24 Sep 04 10:50:10 AM UTC 24 48224487 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3584583689 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:10 AM UTC 24 479094984 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2119612471 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:10 AM UTC 24 116487236 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.1546355473 Sep 04 10:49:56 AM UTC 24 Sep 04 10:50:11 AM UTC 24 1709774703 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.160455915 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:11 AM UTC 24 359801987 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2715160063 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:11 AM UTC 24 73914330 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3600748596 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:11 AM UTC 24 1032963624 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3899941235 Sep 04 10:50:06 AM UTC 24 Sep 04 10:50:11 AM UTC 24 868271591 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.3764673882 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:12 AM UTC 24 167651495 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.588519978 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:12 AM UTC 24 100795922 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.1539538532 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:12 AM UTC 24 13610423 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1028022588 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:12 AM UTC 24 113466435 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.4238632242 Sep 04 10:50:07 AM UTC 24 Sep 04 10:50:12 AM UTC 24 678856632 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4061421649 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:12 AM UTC 24 45606920 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.166220597 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:12 AM UTC 24 56309584 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2695356175 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:12 AM UTC 24 2138223136 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3678167598 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:12 AM UTC 24 28437199 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.918780393 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:12 AM UTC 24 122900435 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2565924497 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:12 AM UTC 24 453014305 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.365648077 Sep 04 10:50:09 AM UTC 24 Sep 04 10:50:13 AM UTC 24 119324304 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2217687562 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:13 AM UTC 24 211763144 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1648864429 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:13 AM UTC 24 174878437 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.1210621784 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:13 AM UTC 24 124425094 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.4242746550 Sep 04 10:50:08 AM UTC 24 Sep 04 10:50:13 AM UTC 24 197751257 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.1236994540 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:13 AM UTC 24 106530299 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.3027101239 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:13 AM UTC 24 39512226 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.109726564 Sep 04 10:50:12 AM UTC 24 Sep 04 10:50:13 AM UTC 24 13024589 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3792616600 Sep 04 10:50:12 AM UTC 24 Sep 04 10:50:14 AM UTC 24 13201199 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.386885555 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:14 AM UTC 24 33511453 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.328022981 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:14 AM UTC 24 46046444 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4201988179 Sep 04 10:50:12 AM UTC 24 Sep 04 10:50:15 AM UTC 24 108789534 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3919638529 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 31690928 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3934620244 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:15 AM UTC 24 933995865 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3713887886 Sep 04 10:50:10 AM UTC 24 Sep 04 10:50:15 AM UTC 24 226215788 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2110816195 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 13570622 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.1935547005 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 99488712 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1453506717 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 34687161 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.626069053 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:15 AM UTC 24 300011466 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2757338706 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 24862147 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2376120209 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 19959806 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1310614731 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 14208661 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2287978301 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 34755961 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2910199496 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:15 AM UTC 24 345220910 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.379112346 Sep 04 10:50:12 AM UTC 24 Sep 04 10:50:15 AM UTC 24 153873755 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1099448231 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:15 AM UTC 24 169639558 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.862464769 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:16 AM UTC 24 981011531 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2056730614 Sep 04 10:50:12 AM UTC 24 Sep 04 10:50:16 AM UTC 24 177562139 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1129589042 Sep 04 10:50:14 AM UTC 24 Sep 04 10:50:16 AM UTC 24 10799440 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2003875265 Sep 04 10:50:14 AM UTC 24 Sep 04 10:50:16 AM UTC 24 14701738 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1886822325 Sep 04 10:50:14 AM UTC 24 Sep 04 10:50:16 AM UTC 24 48014415 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.236284826 Sep 04 10:50:14 AM UTC 24 Sep 04 10:50:16 AM UTC 24 30436877 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2931904415 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:16 AM UTC 24 46891767 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2350338668 Sep 04 10:50:11 AM UTC 24 Sep 04 10:50:16 AM UTC 24 227552724 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.4023925493 Sep 04 10:50:15 AM UTC 24 Sep 04 10:50:16 AM UTC 24 35845056 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.260165035 Sep 04 10:50:15 AM UTC 24 Sep 04 10:50:16 AM UTC 24 15354672 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.369171186 Sep 04 10:50:15 AM UTC 24 Sep 04 10:50:16 AM UTC 24 44864135 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.731013473 Sep 04 10:50:15 AM UTC 24 Sep 04 10:50:16 AM UTC 24 43928223 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.1854661999 Sep 04 10:50:15 AM UTC 24 Sep 04 10:50:16 AM UTC 24 19063931 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.3223196275 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:16 AM UTC 24 272003246 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1691178491 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:17 AM UTC 24 265729923 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2162470001 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:17 AM UTC 24 158687764 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2385812354 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:17 AM UTC 24 92175702 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.1213015509 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:17 AM UTC 24 1442458669 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2611485079 Sep 04 10:50:13 AM UTC 24 Sep 04 10:50:17 AM UTC 24 188342246 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3110748785 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 21793723 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1785183553 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 55158074 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1074064298 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 37624369 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.1701811276 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 14510137 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.100465325 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 17220376 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.2128029823 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 21359843 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.4175849116 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 16806896 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.52275030 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 15455582 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2033087842 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 14005936 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.831969063 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 25045418 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1577800021 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 119662820 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.56535866 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 14091720 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3245565701 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 22849413 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3284699710 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 49596329 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.4221868207 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 45237322 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1033806177 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 129217148 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1744824264 Sep 04 10:50:16 AM UTC 24 Sep 04 10:50:18 AM UTC 24 49599737 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1347830295 Sep 04 10:50:05 AM UTC 24 Sep 04 11:02:10 AM UTC 24 196793864745 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1167619712 Sep 04 10:49:56 AM UTC 24 Sep 04 11:05:17 AM UTC 24 1174876720157 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_smoke.702938912
Short name T2
Test name
Test status
Simulation time 4237302055 ps
CPU time 19.5 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:03:29 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702938912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.702938912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.4274059609
Short name T8
Test name
Test status
Simulation time 31978898022 ps
CPU time 183.02 seconds
Started Sep 04 11:14:03 AM UTC 24
Finished Sep 04 11:17:10 AM UTC 24
Peak memory 375060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42740596
09 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.4274059609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_long_msg.1894143234
Short name T45
Test name
Test status
Simulation time 2834571749 ps
CPU time 158.26 seconds
Started Sep 04 11:14:27 AM UTC 24
Finished Sep 04 11:17:08 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894143234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1894143234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.258342921
Short name T18
Test name
Test status
Simulation time 3300119511 ps
CPU time 46.93 seconds
Started Sep 04 11:04:18 AM UTC 24
Finished Sep 04 11:05:07 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258342921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.258342921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.3637662154
Short name T23
Test name
Test status
Simulation time 642038999 ps
CPU time 34.72 seconds
Started Sep 04 11:08:21 AM UTC 24
Finished Sep 04 11:08:57 AM UTC 24
Peak memory 207436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637662154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3637662154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.672629601
Short name T61
Test name
Test status
Simulation time 356099351 ps
CPU time 4.49 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672629601 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.672629601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.2650817977
Short name T22
Test name
Test status
Simulation time 8967690451 ps
CPU time 232.95 seconds
Started Sep 04 11:36:21 AM UTC 24
Finished Sep 04 11:40:18 AM UTC 24
Peak memory 352180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26508179
77 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2650817977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_error.1473528302
Short name T19
Test name
Test status
Simulation time 2109389566 ps
CPU time 121.8 seconds
Started Sep 04 11:03:09 AM UTC 24
Finished Sep 04 11:05:13 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473528302 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1473528302
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1430901813
Short name T15
Test name
Test status
Simulation time 261894422 ps
CPU time 1.06 seconds
Started Sep 04 11:03:56 AM UTC 24
Finished Sep 04 11:03:58 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430901813 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1430901813
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.2203674474
Short name T26
Test name
Test status
Simulation time 1217967471 ps
CPU time 71.39 seconds
Started Sep 04 11:42:45 AM UTC 24
Finished Sep 04 11:43:58 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203674474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2203674474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.3783846545
Short name T159
Test name
Test status
Simulation time 1214034192 ps
CPU time 66.39 seconds
Started Sep 04 11:36:53 AM UTC 24
Finished Sep 04 11:38:02 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783846545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3783846545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2416365724
Short name T107
Test name
Test status
Simulation time 226161268 ps
CPU time 5.51 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:03 AM UTC 24
Peak memory 207112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416365724 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2416365724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_stress_all.4020595072
Short name T62
Test name
Test status
Simulation time 6004560501 ps
CPU time 74.23 seconds
Started Sep 04 11:38:37 AM UTC 24
Finished Sep 04 11:39:53 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020595072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4020595072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_alert_test.3340442494
Short name T16
Test name
Test status
Simulation time 64954139 ps
CPU time 0.62 seconds
Started Sep 04 11:03:59 AM UTC 24
Finished Sep 04 11:04:00 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340442494 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3340442494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.91331741
Short name T76
Test name
Test status
Simulation time 57827585 ps
CPU time 1.32 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 206852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91331741 -assert nopostproc +UVM_
TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.91331741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.2798825606
Short name T47
Test name
Test status
Simulation time 1476179627 ps
CPU time 89.06 seconds
Started Sep 04 11:37:55 AM UTC 24
Finished Sep 04 11:39:26 AM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798825606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2798825606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2695356175
Short name T141
Test name
Test status
Simulation time 2138223136 ps
CPU time 2.98 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695356175 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2695356175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3899941235
Short name T143
Test name
Test status
Simulation time 868271591 ps
CPU time 3.97 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:11 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899941235 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3899941235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.3196855880
Short name T34
Test name
Test status
Simulation time 36750021681 ps
CPU time 641.64 seconds
Started Sep 04 11:03:09 AM UTC 24
Finished Sep 04 11:14:00 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196855880 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3196855880
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.1395153475
Short name T473
Test name
Test status
Simulation time 1081891529 ps
CPU time 62.88 seconds
Started Sep 04 11:55:39 AM UTC 24
Finished Sep 04 11:56:44 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395153475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1395153475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.1188946916
Short name T6
Test name
Test status
Simulation time 4923122437 ps
CPU time 17.28 seconds
Started Sep 04 11:04:36 AM UTC 24
Finished Sep 04 11:04:54 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188946916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1188946916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.4242746550
Short name T144
Test name
Test status
Simulation time 197751257 ps
CPU time 3.76 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 208048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242746550 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4242746550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.2456733914
Short name T14
Test name
Test status
Simulation time 11298448375 ps
CPU time 366.07 seconds
Started Sep 04 11:36:57 AM UTC 24
Finished Sep 04 11:43:08 AM UTC 24
Peak memory 694724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24567339
14 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2456733914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.117851948
Short name T110
Test name
Test status
Simulation time 338534410 ps
CPU time 8.25 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117851948 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.117851948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3263410678
Short name T535
Test name
Test status
Simulation time 132888681 ps
CPU time 1.03 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:58 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263410678 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3263410678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1167619712
Short name T656
Test name
Test status
Simulation time 1174876720157 ps
CPU time 910.07 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 11:05:17 AM UTC 24
Peak memory 228164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1167619712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.1167619712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.2664136600
Short name T75
Test name
Test status
Simulation time 163877867 ps
CPU time 1.04 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:58 AM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664136600 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2664136600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.1151829036
Short name T534
Test name
Test status
Simulation time 14389684 ps
CPU time 0.59 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:57 AM UTC 24
Peak memory 204644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151829036 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1151829036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.3039769352
Short name T87
Test name
Test status
Simulation time 1453020761 ps
CPU time 3.93 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:01 AM UTC 24
Peak memory 207636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039769352 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3039769352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.2990145307
Short name T59
Test name
Test status
Simulation time 85486333 ps
CPU time 2.02 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990145307 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2990145307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.763341123
Short name T105
Test name
Test status
Simulation time 626738038 ps
CPU time 3.19 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:01 AM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763341123 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.763341123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.1546355473
Short name T580
Test name
Test status
Simulation time 1709774703 ps
CPU time 12.97 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:11 AM UTC 24
Peak memory 207552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546355473 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1546355473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.3688115463
Short name T103
Test name
Test status
Simulation time 32206678 ps
CPU time 0.92 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:58 AM UTC 24
Peak memory 206700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688115463 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3688115463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1576814334
Short name T65
Test name
Test status
Simulation time 26704764 ps
CPU time 1.69 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1576814334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.1576814334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.3399209960
Short name T117
Test name
Test status
Simulation time 109067358 ps
CPU time 1.11 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399209960 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3399209960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2122933127
Short name T74
Test name
Test status
Simulation time 67804662 ps
CPU time 0.59 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:58 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122933127 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2122933127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1492003101
Short name T118
Test name
Test status
Simulation time 679571539 ps
CPU time 2.38 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:00 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492003101 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.1492003101
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3402643760
Short name T66
Test name
Test status
Simulation time 241342404 ps
CPU time 2.22 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402643760 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3402643760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1203955920
Short name T573
Test name
Test status
Simulation time 118207766 ps
CPU time 1.69 seconds
Started Sep 04 10:50:07 AM UTC 24
Finished Sep 04 10:50:09 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1203955920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.1203955920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.2704412071
Short name T114
Test name
Test status
Simulation time 492746036 ps
CPU time 1.17 seconds
Started Sep 04 10:50:07 AM UTC 24
Finished Sep 04 10:50:09 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704412071 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2704412071
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2078661683
Short name T566
Test name
Test status
Simulation time 73504473 ps
CPU time 0.55 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078661683 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2078661683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3545121891
Short name T577
Test name
Test status
Simulation time 48224487 ps
CPU time 2.49 seconds
Started Sep 04 10:50:07 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545121891 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.3545121891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.160455915
Short name T581
Test name
Test status
Simulation time 359801987 ps
CPU time 3.33 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:11 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160455915 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.160455915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4061421649
Short name T589
Test name
Test status
Simulation time 45606920 ps
CPU time 2.85 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 218312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4061421649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.4061421649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2275637928
Short name T115
Test name
Test status
Simulation time 33709599 ps
CPU time 1.03 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275637928 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2275637928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.567938599
Short name T570
Test name
Test status
Simulation time 60638682 ps
CPU time 0.74 seconds
Started Sep 04 10:50:07 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567938599 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.567938599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3584583689
Short name T578
Test name
Test status
Simulation time 479094984 ps
CPU time 1.21 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 206784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584583689 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.3584583689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.4238632242
Short name T588
Test name
Test status
Simulation time 678856632 ps
CPU time 4.06 seconds
Started Sep 04 10:50:07 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 207800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238632242 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4238632242
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.531259314
Short name T139
Test name
Test status
Simulation time 195617402 ps
CPU time 1.56 seconds
Started Sep 04 10:50:07 AM UTC 24
Finished Sep 04 10:50:09 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531259314 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.531259314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2715160063
Short name T582
Test name
Test status
Simulation time 73914330 ps
CPU time 1.84 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:11 AM UTC 24
Peak memory 222488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2715160063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.2715160063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.2201552084
Short name T116
Test name
Test status
Simulation time 33291713 ps
CPU time 0.88 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201552084 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2201552084
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.1675998028
Short name T576
Test name
Test status
Simulation time 29247365 ps
CPU time 0.88 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675998028 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1675998028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3600748596
Short name T583
Test name
Test status
Simulation time 1032963624 ps
CPU time 2.11 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:11 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600748596 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.3600748596
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2565924497
Short name T593
Test name
Test status
Simulation time 453014305 ps
CPU time 2.94 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565924497 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2565924497
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.365648077
Short name T594
Test name
Test status
Simulation time 119324304 ps
CPU time 2.03 seconds
Started Sep 04 10:50:09 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=365648077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_r
eset.365648077
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2119612471
Short name T579
Test name
Test status
Simulation time 116487236 ps
CPU time 0.83 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 205392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119612471 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2119612471
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.940719127
Short name T575
Test name
Test status
Simulation time 38181293 ps
CPU time 0.63 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940719127 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.940719127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1028022588
Short name T587
Test name
Test status
Simulation time 113466435 ps
CPU time 2.35 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028022588 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.1028022588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1379250912
Short name T64
Test name
Test status
Simulation time 63232511 ps
CPU time 1.81 seconds
Started Sep 04 10:50:08 AM UTC 24
Finished Sep 04 10:50:11 AM UTC 24
Peak memory 206608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379250912 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1379250912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.918780393
Short name T592
Test name
Test status
Simulation time 122900435 ps
CPU time 1.32 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=918780393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_r
eset.918780393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.588519978
Short name T585
Test name
Test status
Simulation time 100795922 ps
CPU time 0.82 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 205980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588519978 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.588519978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.3764673882
Short name T584
Test name
Test status
Simulation time 167651495 ps
CPU time 0.85 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 203540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764673882 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3764673882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1648864429
Short name T596
Test name
Test status
Simulation time 174878437 ps
CPU time 2.07 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 207920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648864429 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.1648864429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3678167598
Short name T591
Test name
Test status
Simulation time 28437199 ps
CPU time 1.61 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 206608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678167598 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3678167598
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3934620244
Short name T606
Test name
Test status
Simulation time 933995865 ps
CPU time 4.13 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934620244 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3934620244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2910199496
Short name T616
Test name
Test status
Simulation time 345220910 ps
CPU time 2.86 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 217980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2910199496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.2910199496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.166220597
Short name T590
Test name
Test status
Simulation time 56309584 ps
CPU time 1.01 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166220597 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.166220597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.1539538532
Short name T586
Test name
Test status
Simulation time 13610423 ps
CPU time 0.86 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:12 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539538532 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1539538532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2217687562
Short name T595
Test name
Test status
Simulation time 211763144 ps
CPU time 1.74 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 206740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217687562 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.2217687562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.1236994540
Short name T598
Test name
Test status
Simulation time 106530299 ps
CPU time 2.28 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236994540 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1236994540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3713887886
Short name T607
Test name
Test status
Simulation time 226215788 ps
CPU time 3.98 seconds
Started Sep 04 10:50:10 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713887886 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3713887886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.386885555
Short name T602
Test name
Test status
Simulation time 33511453 ps
CPU time 1.15 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:14 AM UTC 24
Peak memory 206660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=386885555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_r
eset.386885555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.3027101239
Short name T599
Test name
Test status
Simulation time 39512226 ps
CPU time 0.8 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 206948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027101239 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3027101239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.1210621784
Short name T597
Test name
Test status
Simulation time 124425094 ps
CPU time 0.72 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210621784 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1210621784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.626069053
Short name T611
Test name
Test status
Simulation time 300011466 ps
CPU time 2.47 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626069053 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.626069053
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.328022981
Short name T603
Test name
Test status
Simulation time 46046444 ps
CPU time 2.04 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:14 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328022981 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.328022981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2350338668
Short name T626
Test name
Test status
Simulation time 227552724 ps
CPU time 3.88 seconds
Started Sep 04 10:50:11 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350338668 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2350338668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2162470001
Short name T634
Test name
Test status
Simulation time 158687764 ps
CPU time 2.79 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:17 AM UTC 24
Peak memory 217964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2162470001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2162470001
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3792616600
Short name T601
Test name
Test status
Simulation time 13201199 ps
CPU time 0.79 seconds
Started Sep 04 10:50:12 AM UTC 24
Finished Sep 04 10:50:14 AM UTC 24
Peak memory 205656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792616600 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3792616600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.109726564
Short name T600
Test name
Test status
Simulation time 13024589 ps
CPU time 0.66 seconds
Started Sep 04 10:50:12 AM UTC 24
Finished Sep 04 10:50:13 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109726564 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.109726564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4201988179
Short name T604
Test name
Test status
Simulation time 108789534 ps
CPU time 1.72 seconds
Started Sep 04 10:50:12 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 206784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201988179 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.4201988179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.379112346
Short name T617
Test name
Test status
Simulation time 153873755 ps
CPU time 2.79 seconds
Started Sep 04 10:50:12 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379112346 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.379112346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2056730614
Short name T620
Test name
Test status
Simulation time 177562139 ps
CPU time 2.99 seconds
Started Sep 04 10:50:12 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056730614 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2056730614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1691178491
Short name T633
Test name
Test status
Simulation time 265729923 ps
CPU time 2.55 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:17 AM UTC 24
Peak memory 224416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1691178491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.1691178491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1453506717
Short name T610
Test name
Test status
Simulation time 34687161 ps
CPU time 1.03 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453506717 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1453506717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3919638529
Short name T605
Test name
Test status
Simulation time 31690928 ps
CPU time 0.63 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919638529 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3919638529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1099448231
Short name T618
Test name
Test status
Simulation time 169639558 ps
CPU time 1.26 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 206740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099448231 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.1099448231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.3223196275
Short name T632
Test name
Test status
Simulation time 272003246 ps
CPU time 2.63 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223196275 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3223196275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.862464769
Short name T619
Test name
Test status
Simulation time 981011531 ps
CPU time 1.7 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862464769 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.862464769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2385812354
Short name T635
Test name
Test status
Simulation time 92175702 ps
CPU time 2.42 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:17 AM UTC 24
Peak memory 218120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2385812354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.2385812354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2110816195
Short name T608
Test name
Test status
Simulation time 13570622 ps
CPU time 0.76 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 205980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110816195 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2110816195
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.1935547005
Short name T609
Test name
Test status
Simulation time 99488712 ps
CPU time 0.73 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935547005 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1935547005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2931904415
Short name T625
Test name
Test status
Simulation time 46891767 ps
CPU time 1.97 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931904415 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.2931904415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.1213015509
Short name T636
Test name
Test status
Simulation time 1442458669 ps
CPU time 2.76 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:17 AM UTC 24
Peak memory 206892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213015509 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1213015509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2611485079
Short name T637
Test name
Test status
Simulation time 188342246 ps
CPU time 3.16 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:17 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611485079 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2611485079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.2036603944
Short name T112
Test name
Test status
Simulation time 2278499345 ps
CPU time 8.47 seconds
Started Sep 04 10:49:57 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036603944 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2036603944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3541871682
Short name T560
Test name
Test status
Simulation time 1027148201 ps
CPU time 9.12 seconds
Started Sep 04 10:49:57 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 207612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541871682 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3541871682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3169742857
Short name T537
Test name
Test status
Simulation time 47696193 ps
CPU time 0.94 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 205924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169742857 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3169742857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.636740685
Short name T541
Test name
Test status
Simulation time 170864271 ps
CPU time 1.33 seconds
Started Sep 04 10:49:59 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=636740685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_re
set.636740685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.271643730
Short name T104
Test name
Test status
Simulation time 27399419 ps
CPU time 1.09 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:59 AM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271643730 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.271643730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.4150668914
Short name T536
Test name
Test status
Simulation time 35782018 ps
CPU time 0.72 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:49:58 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150668914 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4150668914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1778136398
Short name T119
Test name
Test status
Simulation time 136837228 ps
CPU time 1.58 seconds
Started Sep 04 10:49:58 AM UTC 24
Finished Sep 04 10:50:00 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778136398 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.1778136398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2043865128
Short name T538
Test name
Test status
Simulation time 820844185 ps
CPU time 3.37 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:01 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043865128 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2043865128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.720643705
Short name T60
Test name
Test status
Simulation time 97336129 ps
CPU time 3.04 seconds
Started Sep 04 10:49:56 AM UTC 24
Finished Sep 04 10:50:01 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720643705 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.720643705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2757338706
Short name T612
Test name
Test status
Simulation time 24862147 ps
CPU time 0.69 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757338706 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2757338706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2376120209
Short name T613
Test name
Test status
Simulation time 19959806 ps
CPU time 0.71 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376120209 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2376120209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1310614731
Short name T614
Test name
Test status
Simulation time 14208661 ps
CPU time 0.71 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310614731 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1310614731
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2287978301
Short name T615
Test name
Test status
Simulation time 34755961 ps
CPU time 0.75 seconds
Started Sep 04 10:50:13 AM UTC 24
Finished Sep 04 10:50:15 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287978301 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2287978301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1886822325
Short name T623
Test name
Test status
Simulation time 48014415 ps
CPU time 0.69 seconds
Started Sep 04 10:50:14 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886822325 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1886822325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.236284826
Short name T624
Test name
Test status
Simulation time 30436877 ps
CPU time 0.63 seconds
Started Sep 04 10:50:14 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236284826 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.236284826
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1129589042
Short name T621
Test name
Test status
Simulation time 10799440 ps
CPU time 0.62 seconds
Started Sep 04 10:50:14 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129589042 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1129589042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2003875265
Short name T622
Test name
Test status
Simulation time 14701738 ps
CPU time 0.6 seconds
Started Sep 04 10:50:14 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003875265 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2003875265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.260165035
Short name T628
Test name
Test status
Simulation time 15354672 ps
CPU time 0.71 seconds
Started Sep 04 10:50:15 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260165035 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.260165035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.4023925493
Short name T627
Test name
Test status
Simulation time 35845056 ps
CPU time 0.67 seconds
Started Sep 04 10:50:15 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023925493 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.4023925493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1243431982
Short name T554
Test name
Test status
Simulation time 1219260160 ps
CPU time 5.49 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243431982 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1243431982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.1957919646
Short name T548
Test name
Test status
Simulation time 441706628 ps
CPU time 4.63 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 207612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957919646 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1957919646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1028423991
Short name T540
Test name
Test status
Simulation time 131166105 ps
CPU time 1.11 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028423991 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1028423991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.916924346
Short name T542
Test name
Test status
Simulation time 63870186 ps
CPU time 1.85 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:03 AM UTC 24
Peak memory 206512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=916924346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_re
set.916924346
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.2201699875
Short name T106
Test name
Test status
Simulation time 57683117 ps
CPU time 1.01 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201699875 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2201699875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.199418347
Short name T539
Test name
Test status
Simulation time 19477403 ps
CPU time 0.6 seconds
Started Sep 04 10:49:59 AM UTC 24
Finished Sep 04 10:50:01 AM UTC 24
Peak memory 203412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199418347 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.199418347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1121837563
Short name T120
Test name
Test status
Simulation time 77383933 ps
CPU time 1.23 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121837563 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.1121837563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.2959382761
Short name T549
Test name
Test status
Simulation time 311683210 ps
CPU time 4.97 seconds
Started Sep 04 10:49:59 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959382761 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2959382761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.629394113
Short name T142
Test name
Test status
Simulation time 99963170 ps
CPU time 2.15 seconds
Started Sep 04 10:49:59 AM UTC 24
Finished Sep 04 10:50:03 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629394113 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.629394113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.731013473
Short name T630
Test name
Test status
Simulation time 43928223 ps
CPU time 0.72 seconds
Started Sep 04 10:50:15 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731013473 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.731013473
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.1854661999
Short name T631
Test name
Test status
Simulation time 19063931 ps
CPU time 0.75 seconds
Started Sep 04 10:50:15 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854661999 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1854661999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.369171186
Short name T629
Test name
Test status
Simulation time 44864135 ps
CPU time 0.65 seconds
Started Sep 04 10:50:15 AM UTC 24
Finished Sep 04 10:50:16 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369171186 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.369171186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.1701811276
Short name T641
Test name
Test status
Simulation time 14510137 ps
CPU time 0.7 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701811276 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1701811276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1785183553
Short name T639
Test name
Test status
Simulation time 55158074 ps
CPU time 0.6 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785183553 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1785183553
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3110748785
Short name T638
Test name
Test status
Simulation time 21793723 ps
CPU time 0.5 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110748785 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3110748785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.52275030
Short name T645
Test name
Test status
Simulation time 15455582 ps
CPU time 0.69 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52275030 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.52275030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1074064298
Short name T640
Test name
Test status
Simulation time 37624369 ps
CPU time 0.61 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074064298 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1074064298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.100465325
Short name T642
Test name
Test status
Simulation time 17220376 ps
CPU time 0.6 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100465325 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.100465325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.4175849116
Short name T644
Test name
Test status
Simulation time 16806896 ps
CPU time 0.56 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175849116 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4175849116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1358097202
Short name T553
Test name
Test status
Simulation time 623659033 ps
CPU time 3.12 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358097202 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1358097202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2621900333
Short name T568
Test name
Test status
Simulation time 289813487 ps
CPU time 5.19 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 207856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621900333 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2621900333
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2350822076
Short name T543
Test name
Test status
Simulation time 22689824 ps
CPU time 0.7 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:03 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350822076 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2350822076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3250885603
Short name T550
Test name
Test status
Simulation time 112401129 ps
CPU time 2.71 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 218024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3250885603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.3250885603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2707736286
Short name T108
Test name
Test status
Simulation time 63103215 ps
CPU time 0.89 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:04 AM UTC 24
Peak memory 206640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707736286 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2707736286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.1388812318
Short name T77
Test name
Test status
Simulation time 247762345 ps
CPU time 0.73 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:02 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388812318 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1388812318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1934214036
Short name T121
Test name
Test status
Simulation time 51282534 ps
CPU time 1.32 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:04 AM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934214036 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.1934214036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1207271642
Short name T545
Test name
Test status
Simulation time 155512080 ps
CPU time 3.28 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:04 AM UTC 24
Peak memory 207804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207271642 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1207271642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1243050365
Short name T135
Test name
Test status
Simulation time 83996662 ps
CPU time 1.73 seconds
Started Sep 04 10:50:00 AM UTC 24
Finished Sep 04 10:50:03 AM UTC 24
Peak memory 206576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243050365 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1243050365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.2128029823
Short name T643
Test name
Test status
Simulation time 21359843 ps
CPU time 0.55 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128029823 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2128029823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1577800021
Short name T648
Test name
Test status
Simulation time 119662820 ps
CPU time 0.71 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577800021 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1577800021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.831969063
Short name T647
Test name
Test status
Simulation time 25045418 ps
CPU time 0.63 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831969063 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.831969063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2033087842
Short name T646
Test name
Test status
Simulation time 14005936 ps
CPU time 0.67 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033087842 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2033087842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.56535866
Short name T649
Test name
Test status
Simulation time 14091720 ps
CPU time 0.62 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56535866 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.56535866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1033806177
Short name T653
Test name
Test status
Simulation time 129217148 ps
CPU time 0.65 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033806177 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1033806177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.3245565701
Short name T650
Test name
Test status
Simulation time 22849413 ps
CPU time 0.53 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245565701 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3245565701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3284699710
Short name T651
Test name
Test status
Simulation time 49596329 ps
CPU time 0.58 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284699710 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3284699710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1744824264
Short name T654
Test name
Test status
Simulation time 49599737 ps
CPU time 0.64 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744824264 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1744824264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.4221868207
Short name T652
Test name
Test status
Simulation time 45237322 ps
CPU time 0.54 seconds
Started Sep 04 10:50:16 AM UTC 24
Finished Sep 04 10:50:18 AM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221868207 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4221868207
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1168033883
Short name T565
Test name
Test status
Simulation time 193499355 ps
CPU time 3.27 seconds
Started Sep 04 10:50:03 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 217972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1168033883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.1168033883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2978839849
Short name T109
Test name
Test status
Simulation time 17841005 ps
CPU time 0.85 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:04 AM UTC 24
Peak memory 206888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978839849 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2978839849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.3502675924
Short name T544
Test name
Test status
Simulation time 14348798 ps
CPU time 0.81 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:04 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502675924 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3502675924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1459814085
Short name T123
Test name
Test status
Simulation time 181017569 ps
CPU time 2.2 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459814085 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.1459814085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3634585378
Short name T557
Test name
Test status
Simulation time 220302796 ps
CPU time 3.56 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634585378 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3634585378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.958201305
Short name T136
Test name
Test status
Simulation time 127816420 ps
CPU time 1.79 seconds
Started Sep 04 10:50:02 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958201305 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.958201305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2716678136
Short name T562
Test name
Test status
Simulation time 134026844 ps
CPU time 2.66 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2716678136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.2716678136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3806928865
Short name T122
Test name
Test status
Simulation time 23489123 ps
CPU time 0.92 seconds
Started Sep 04 10:50:03 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806928865 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3806928865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2824951552
Short name T546
Test name
Test status
Simulation time 38347707 ps
CPU time 0.55 seconds
Started Sep 04 10:50:03 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824951552 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2824951552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1259466486
Short name T551
Test name
Test status
Simulation time 172627976 ps
CPU time 1.3 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 206736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259466486 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.1259466486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.4037319864
Short name T564
Test name
Test status
Simulation time 286841291 ps
CPU time 3.07 seconds
Started Sep 04 10:50:03 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 207628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037319864 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4037319864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.2784824994
Short name T556
Test name
Test status
Simulation time 596904048 ps
CPU time 2.13 seconds
Started Sep 04 10:50:03 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784824994 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2784824994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1937415076
Short name T563
Test name
Test status
Simulation time 126176570 ps
CPU time 2.48 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 208052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1937415076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.1937415076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.138112855
Short name T111
Test name
Test status
Simulation time 30939436 ps
CPU time 0.92 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138112855 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.138112855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3891374320
Short name T547
Test name
Test status
Simulation time 36579704 ps
CPU time 0.55 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:05 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891374320 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3891374320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4221323259
Short name T555
Test name
Test status
Simulation time 105343094 ps
CPU time 1.59 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 206724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221323259 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.4221323259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2591962830
Short name T552
Test name
Test status
Simulation time 150160366 ps
CPU time 1.51 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591962830 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2591962830
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.4126483761
Short name T137
Test name
Test status
Simulation time 400614455 ps
CPU time 1.84 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:06 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126483761 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4126483761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1347830295
Short name T655
Test name
Test status
Simulation time 196793864745 ps
CPU time 717.09 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 11:02:10 AM UTC 24
Peak memory 240028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1347830295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.1347830295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3277864635
Short name T561
Test name
Test status
Simulation time 112057900 ps
CPU time 0.97 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277864635 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3277864635
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.3168850432
Short name T559
Test name
Test status
Simulation time 17773236 ps
CPU time 0.77 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168850432 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3168850432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.369017231
Short name T571
Test name
Test status
Simulation time 442438964 ps
CPU time 2.39 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369017231 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.369017231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.3127688513
Short name T558
Test name
Test status
Simulation time 83198659 ps
CPU time 1.96 seconds
Started Sep 04 10:50:04 AM UTC 24
Finished Sep 04 10:50:07 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127688513 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3127688513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.4175562745
Short name T140
Test name
Test status
Simulation time 196319677 ps
CPU time 2.93 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 10:50:09 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175562745 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4175562745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1927465085
Short name T572
Test name
Test status
Simulation time 34869721 ps
CPU time 1.12 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:09 AM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1927465085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.1927465085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.353718474
Short name T113
Test name
Test status
Simulation time 24577482 ps
CPU time 0.83 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 206464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353718474 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.353718474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1734322592
Short name T569
Test name
Test status
Simulation time 13506477 ps
CPU time 0.75 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 203596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734322592 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1734322592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.935115797
Short name T574
Test name
Test status
Simulation time 272598159 ps
CPU time 2.39 seconds
Started Sep 04 10:50:06 AM UTC 24
Finished Sep 04 10:50:10 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935115797 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.935115797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2378207732
Short name T567
Test name
Test status
Simulation time 197091635 ps
CPU time 1.79 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 10:50:08 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378207732 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2378207732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.1782219609
Short name T138
Test name
Test status
Simulation time 89682464 ps
CPU time 2.88 seconds
Started Sep 04 10:50:05 AM UTC 24
Finished Sep 04 10:50:09 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782219609 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1782219609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.587304923
Short name T3
Test name
Test status
Simulation time 9551593373 ps
CPU time 36.91 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:03:47 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587304923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.587304923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.476634335
Short name T5
Test name
Test status
Simulation time 10269830540 ps
CPU time 69.9 seconds
Started Sep 04 11:03:09 AM UTC 24
Finished Sep 04 11:04:20 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476634335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.476634335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.2512966784
Short name T131
Test name
Test status
Simulation time 1109136216 ps
CPU time 180.77 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:06:12 AM UTC 24
Peak memory 649408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512966784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2512966784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_long_msg.1125105375
Short name T20
Test name
Test status
Simulation time 14300239552 ps
CPU time 126.53 seconds
Started Sep 04 11:03:08 AM UTC 24
Finished Sep 04 11:05:18 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125105375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1125105375
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_stress_all.2040285585
Short name T520
Test name
Test status
Simulation time 135442399750 ps
CPU time 4184.79 seconds
Started Sep 04 11:03:31 AM UTC 24
Finished Sep 04 12:14:07 PM UTC 24
Peak memory 827580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040285585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2040285585
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.1522013322
Short name T7
Test name
Test status
Simulation time 5259214296 ps
CPU time 513.81 seconds
Started Sep 04 11:03:49 AM UTC 24
Finished Sep 04 11:12:30 AM UTC 24
Peak memory 516508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15220133
22 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1522013322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.3338161178
Short name T17
Test name
Test status
Simulation time 4770458447 ps
CPU time 82.99 seconds
Started Sep 04 11:03:10 AM UTC 24
Finished Sep 04 11:04:35 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338161178 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3338161178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.804467935
Short name T10
Test name
Test status
Simulation time 3983657327 ps
CPU time 65.1 seconds
Started Sep 04 11:03:10 AM UTC 24
Finished Sep 04 11:04:17 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804467935 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.804467935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1210773450
Short name T50
Test name
Test status
Simulation time 83817663441 ps
CPU time 142.9 seconds
Started Sep 04 11:03:29 AM UTC 24
Finished Sep 04 11:05:55 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210773450 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1210773450
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.2169858327
Short name T380
Test name
Test status
Simulation time 892384266741 ps
CPU time 2759.65 seconds
Started Sep 04 11:03:09 AM UTC 24
Finished Sep 04 11:49:45 AM UTC 24
Peak memory 225576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169858327 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2169858327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.3952899812
Short name T367
Test name
Test status
Simulation time 259542084391 ps
CPU time 2711.29 seconds
Started Sep 04 11:03:10 AM UTC 24
Finished Sep 04 11:48:56 AM UTC 24
Peak memory 221324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952899812 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3952899812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.2820463881
Short name T1
Test name
Test status
Simulation time 5227068166 ps
CPU time 17.3 seconds
Started Sep 04 11:03:09 AM UTC 24
Finished Sep 04 11:03:27 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820463881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2820463881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_alert_test.1660129046
Short name T52
Test name
Test status
Simulation time 11962750 ps
CPU time 0.63 seconds
Started Sep 04 11:07:14 AM UTC 24
Finished Sep 04 11:07:16 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660129046 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1660129046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.3861292278
Short name T31
Test name
Test status
Simulation time 3666302958 ps
CPU time 428.1 seconds
Started Sep 04 11:04:21 AM UTC 24
Finished Sep 04 11:11:36 AM UTC 24
Peak memory 721248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861292278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3861292278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_error.629691069
Short name T51
Test name
Test status
Simulation time 6832922272 ps
CPU time 76.89 seconds
Started Sep 04 11:04:55 AM UTC 24
Finished Sep 04 11:06:14 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629691069 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.629691069
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_long_msg.973740889
Short name T148
Test name
Test status
Simulation time 54141935692 ps
CPU time 146.73 seconds
Started Sep 04 11:04:06 AM UTC 24
Finished Sep 04 11:06:35 AM UTC 24
Peak memory 223908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973740889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.973740889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.1005469472
Short name T54
Test name
Test status
Simulation time 192445572 ps
CPU time 0.99 seconds
Started Sep 04 11:07:11 AM UTC 24
Finished Sep 04 11:07:13 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005469472 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1005469472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_smoke.2619921138
Short name T4
Test name
Test status
Simulation time 173516627 ps
CPU time 3.65 seconds
Started Sep 04 11:04:01 AM UTC 24
Finished Sep 04 11:04:05 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619921138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2619921138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_stress_all.2214099571
Short name T94
Test name
Test status
Simulation time 120614522431 ps
CPU time 1075.1 seconds
Started Sep 04 11:06:15 AM UTC 24
Finished Sep 04 11:24:24 AM UTC 24
Peak memory 770320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214099571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2214099571
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.3015860531
Short name T170
Test name
Test status
Simulation time 4302607299 ps
CPU time 72.38 seconds
Started Sep 04 11:05:57 AM UTC 24
Finished Sep 04 11:07:11 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015860531 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3015860531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.1542799551
Short name T171
Test name
Test status
Simulation time 26319471979 ps
CPU time 102.28 seconds
Started Sep 04 11:06:06 AM UTC 24
Finished Sep 04 11:07:50 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542799551 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1542799551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.3980245040
Short name T172
Test name
Test status
Simulation time 7874679851 ps
CPU time 122.19 seconds
Started Sep 04 11:06:13 AM UTC 24
Finished Sep 04 11:08:18 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980245040 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3980245040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.2472133950
Short name T68
Test name
Test status
Simulation time 36784440640 ps
CPU time 659.9 seconds
Started Sep 04 11:05:15 AM UTC 24
Finished Sep 04 11:16:24 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472133950 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2472133950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.2643972904
Short name T356
Test name
Test status
Simulation time 143053272814 ps
CPU time 2531.85 seconds
Started Sep 04 11:05:18 AM UTC 24
Finished Sep 04 11:48:04 AM UTC 24
Peak memory 225328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643972904 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2643972904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.986836611
Short name T282
Test name
Test status
Simulation time 40817824253 ps
CPU time 2193.99 seconds
Started Sep 04 11:05:19 AM UTC 24
Finished Sep 04 11:42:22 AM UTC 24
Peak memory 221444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986836611 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.986836611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.29748755
Short name T21
Test name
Test status
Simulation time 6216855238 ps
CPU time 55.23 seconds
Started Sep 04 11:05:08 AM UTC 24
Finished Sep 04 11:06:05 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29748755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.29748755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_alert_test.994455331
Short name T187
Test name
Test status
Simulation time 50899791 ps
CPU time 0.88 seconds
Started Sep 04 11:37:06 AM UTC 24
Finished Sep 04 11:37:08 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994455331 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.994455331
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.1149541560
Short name T231
Test name
Test status
Simulation time 5769813747 ps
CPU time 105.86 seconds
Started Sep 04 11:36:58 AM UTC 24
Finished Sep 04 11:38:46 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149541560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1149541560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.4233369577
Short name T55
Test name
Test status
Simulation time 1614589468 ps
CPU time 21.3 seconds
Started Sep 04 11:36:59 AM UTC 24
Finished Sep 04 11:37:22 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233369577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4233369577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.2839772658
Short name T304
Test name
Test status
Simulation time 10404253451 ps
CPU time 454.6 seconds
Started Sep 04 11:36:58 AM UTC 24
Finished Sep 04 11:44:39 AM UTC 24
Peak memory 754156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839772658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2839772658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_error.3056865298
Short name T214
Test name
Test status
Simulation time 4394446596 ps
CPU time 67.88 seconds
Started Sep 04 11:37:01 AM UTC 24
Finished Sep 04 11:38:10 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056865298 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3056865298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_long_msg.1894350714
Short name T242
Test name
Test status
Simulation time 10254665087 ps
CPU time 152.38 seconds
Started Sep 04 11:36:58 AM UTC 24
Finished Sep 04 11:39:33 AM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894350714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1894350714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_smoke.3567288516
Short name T184
Test name
Test status
Simulation time 26431666 ps
CPU time 1.24 seconds
Started Sep 04 11:36:57 AM UTC 24
Finished Sep 04 11:36:59 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567288516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3567288516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_stress_all.3029599437
Short name T133
Test name
Test status
Simulation time 19842695736 ps
CPU time 329.52 seconds
Started Sep 04 11:37:03 AM UTC 24
Finished Sep 04 11:42:37 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029599437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3029599437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.758510468
Short name T200
Test name
Test status
Simulation time 3720845773 ps
CPU time 32.57 seconds
Started Sep 04 11:37:01 AM UTC 24
Finished Sep 04 11:37:34 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758510468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.758510468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_alert_test.829598174
Short name T194
Test name
Test status
Simulation time 21597991 ps
CPU time 0.83 seconds
Started Sep 04 11:37:26 AM UTC 24
Finished Sep 04 11:37:28 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829598174 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.829598174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.1066376613
Short name T191
Test name
Test status
Simulation time 146321350 ps
CPU time 9.2 seconds
Started Sep 04 11:37:11 AM UTC 24
Finished Sep 04 11:37:21 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066376613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1066376613
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.2494100705
Short name T158
Test name
Test status
Simulation time 183821161 ps
CPU time 12.29 seconds
Started Sep 04 11:37:15 AM UTC 24
Finished Sep 04 11:37:28 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494100705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2494100705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.1398066006
Short name T219
Test name
Test status
Simulation time 1243606286 ps
CPU time 212.28 seconds
Started Sep 04 11:37:14 AM UTC 24
Finished Sep 04 11:40:50 AM UTC 24
Peak memory 694756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398066006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1398066006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_error.2660018199
Short name T224
Test name
Test status
Simulation time 14212850314 ps
CPU time 59.88 seconds
Started Sep 04 11:37:20 AM UTC 24
Finished Sep 04 11:38:21 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660018199 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2660018199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_long_msg.1331975180
Short name T193
Test name
Test status
Simulation time 432086453 ps
CPU time 16.79 seconds
Started Sep 04 11:37:09 AM UTC 24
Finished Sep 04 11:37:27 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331975180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1331975180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_smoke.850999013
Short name T188
Test name
Test status
Simulation time 313287653 ps
CPU time 1.5 seconds
Started Sep 04 11:37:08 AM UTC 24
Finished Sep 04 11:37:10 AM UTC 24
Peak memory 206520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850999013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.850999013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3003412038
Short name T100
Test name
Test status
Simulation time 219459207925 ps
CPU time 672.17 seconds
Started Sep 04 11:37:23 AM UTC 24
Finished Sep 04 11:48:45 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003412038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3003412038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.3098922724
Short name T222
Test name
Test status
Simulation time 8842395855 ps
CPU time 54.19 seconds
Started Sep 04 11:37:22 AM UTC 24
Finished Sep 04 11:38:18 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098922724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3098922724
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_alert_test.184366665
Short name T201
Test name
Test status
Simulation time 12774805 ps
CPU time 0.91 seconds
Started Sep 04 11:37:33 AM UTC 24
Finished Sep 04 11:37:35 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184366665 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.184366665
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.531240327
Short name T208
Test name
Test status
Simulation time 500633840 ps
CPU time 21.28 seconds
Started Sep 04 11:37:29 AM UTC 24
Finished Sep 04 11:37:52 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531240327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.531240327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.2456629884
Short name T203
Test name
Test status
Simulation time 221367181 ps
CPU time 8.02 seconds
Started Sep 04 11:37:31 AM UTC 24
Finished Sep 04 11:37:40 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456629884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2456629884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.3449145347
Short name T290
Test name
Test status
Simulation time 2303371185 ps
CPU time 321.64 seconds
Started Sep 04 11:37:29 AM UTC 24
Finished Sep 04 11:42:55 AM UTC 24
Peak memory 485660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449145347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3449145347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_error.3586937995
Short name T216
Test name
Test status
Simulation time 12911598249 ps
CPU time 38.51 seconds
Started Sep 04 11:37:31 AM UTC 24
Finished Sep 04 11:38:11 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586937995 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3586937995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_long_msg.203223899
Short name T213
Test name
Test status
Simulation time 9026590626 ps
CPU time 38.79 seconds
Started Sep 04 11:37:29 AM UTC 24
Finished Sep 04 11:38:10 AM UTC 24
Peak memory 207584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203223899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.203223899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_smoke.1176594419
Short name T198
Test name
Test status
Simulation time 93654128 ps
CPU time 2.35 seconds
Started Sep 04 11:37:28 AM UTC 24
Finished Sep 04 11:37:31 AM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176594419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1176594419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_stress_all.2294537126
Short name T466
Test name
Test status
Simulation time 36281908333 ps
CPU time 1103.17 seconds
Started Sep 04 11:37:33 AM UTC 24
Finished Sep 04 11:56:09 AM UTC 24
Peak memory 698668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294537126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2294537126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3551118273
Short name T217
Test name
Test status
Simulation time 4146592366 ps
CPU time 38 seconds
Started Sep 04 11:37:33 AM UTC 24
Finished Sep 04 11:38:12 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551118273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3551118273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_alert_test.1217820676
Short name T206
Test name
Test status
Simulation time 23851229 ps
CPU time 0.77 seconds
Started Sep 04 11:37:48 AM UTC 24
Finished Sep 04 11:37:50 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217820676 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1217820676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.3256134983
Short name T12
Test name
Test status
Simulation time 4149495983 ps
CPU time 64.1 seconds
Started Sep 04 11:37:36 AM UTC 24
Finished Sep 04 11:38:42 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256134983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3256134983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.3505068758
Short name T218
Test name
Test status
Simulation time 2933805297 ps
CPU time 31.82 seconds
Started Sep 04 11:37:39 AM UTC 24
Finished Sep 04 11:38:13 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505068758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3505068758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.2964425493
Short name T266
Test name
Test status
Simulation time 1153046970 ps
CPU time 200.89 seconds
Started Sep 04 11:37:37 AM UTC 24
Finished Sep 04 11:41:02 AM UTC 24
Peak memory 421896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964425493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2964425493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_error.3284480285
Short name T238
Test name
Test status
Simulation time 3083809373 ps
CPU time 90.46 seconds
Started Sep 04 11:37:41 AM UTC 24
Finished Sep 04 11:39:13 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284480285 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3284480285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_long_msg.2119696676
Short name T259
Test name
Test status
Simulation time 25438984730 ps
CPU time 174.89 seconds
Started Sep 04 11:37:36 AM UTC 24
Finished Sep 04 11:40:34 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119696676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2119696676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_smoke.3243069229
Short name T168
Test name
Test status
Simulation time 455218246 ps
CPU time 14.39 seconds
Started Sep 04 11:37:34 AM UTC 24
Finished Sep 04 11:37:50 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243069229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3243069229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_stress_all.2832763369
Short name T525
Test name
Test status
Simulation time 194265225854 ps
CPU time 2732.21 seconds
Started Sep 04 11:37:47 AM UTC 24
Finished Sep 04 12:23:52 PM UTC 24
Peak memory 819384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832763369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2832763369
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2027267601
Short name T126
Test name
Test status
Simulation time 6140878791 ps
CPU time 125.97 seconds
Started Sep 04 11:37:44 AM UTC 24
Finished Sep 04 11:39:52 AM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027267601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2027267601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_alert_test.3796968745
Short name T211
Test name
Test status
Simulation time 18703576 ps
CPU time 0.87 seconds
Started Sep 04 11:38:05 AM UTC 24
Finished Sep 04 11:38:07 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796968745 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3796968745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1057345439
Short name T215
Test name
Test status
Simulation time 213168447 ps
CPU time 17 seconds
Started Sep 04 11:37:52 AM UTC 24
Finished Sep 04 11:38:10 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057345439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1057345439
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.893062759
Short name T78
Test name
Test status
Simulation time 8722298725 ps
CPU time 312.39 seconds
Started Sep 04 11:37:53 AM UTC 24
Finished Sep 04 11:43:10 AM UTC 24
Peak memory 704868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893062759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.893062759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_error.3264913092
Short name T232
Test name
Test status
Simulation time 10706460896 ps
CPU time 47.62 seconds
Started Sep 04 11:37:57 AM UTC 24
Finished Sep 04 11:38:47 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264913092 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3264913092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_long_msg.3552584651
Short name T275
Test name
Test status
Simulation time 21527443817 ps
CPU time 256.4 seconds
Started Sep 04 11:37:51 AM UTC 24
Finished Sep 04 11:42:11 AM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552584651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3552584651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_smoke.437466180
Short name T151
Test name
Test status
Simulation time 1130572833 ps
CPU time 11.78 seconds
Started Sep 04 11:37:51 AM UTC 24
Finished Sep 04 11:38:04 AM UTC 24
Peak memory 207372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437466180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.437466180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_stress_all.3248421186
Short name T128
Test name
Test status
Simulation time 5313081180 ps
CPU time 272.37 seconds
Started Sep 04 11:38:04 AM UTC 24
Finished Sep 04 11:42:40 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248421186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3248421186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.369397742
Short name T212
Test name
Test status
Simulation time 152824616 ps
CPU time 4.13 seconds
Started Sep 04 11:38:02 AM UTC 24
Finished Sep 04 11:38:07 AM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369397742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.369397742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_alert_test.3304358309
Short name T223
Test name
Test status
Simulation time 23982520 ps
CPU time 0.86 seconds
Started Sep 04 11:38:17 AM UTC 24
Finished Sep 04 11:38:18 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304358309 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3304358309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.2808098787
Short name T249
Test name
Test status
Simulation time 5426654305 ps
CPU time 99.89 seconds
Started Sep 04 11:38:10 AM UTC 24
Finished Sep 04 11:39:52 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808098787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2808098787
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.2253607212
Short name T162
Test name
Test status
Simulation time 2675366493 ps
CPU time 46.42 seconds
Started Sep 04 11:38:12 AM UTC 24
Finished Sep 04 11:39:00 AM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253607212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2253607212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.4022044708
Short name T497
Test name
Test status
Simulation time 24995523135 ps
CPU time 1359.82 seconds
Started Sep 04 11:38:12 AM UTC 24
Finished Sep 04 12:01:06 PM UTC 24
Peak memory 788708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022044708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4022044708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_error.740937682
Short name T256
Test name
Test status
Simulation time 2268310655 ps
CPU time 127.69 seconds
Started Sep 04 11:38:12 AM UTC 24
Finished Sep 04 11:40:22 AM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740937682 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.740937682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_long_msg.3964176341
Short name T244
Test name
Test status
Simulation time 6653378226 ps
CPU time 92.62 seconds
Started Sep 04 11:38:08 AM UTC 24
Finished Sep 04 11:39:43 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964176341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3964176341
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_smoke.1805839685
Short name T152
Test name
Test status
Simulation time 541392082 ps
CPU time 6.23 seconds
Started Sep 04 11:38:08 AM UTC 24
Finished Sep 04 11:38:15 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805839685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1805839685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_stress_all.3830509921
Short name T284
Test name
Test status
Simulation time 61055449970 ps
CPU time 251.71 seconds
Started Sep 04 11:38:14 AM UTC 24
Finished Sep 04 11:42:29 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830509921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3830509921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.267709606
Short name T240
Test name
Test status
Simulation time 15224640204 ps
CPU time 59.58 seconds
Started Sep 04 11:38:14 AM UTC 24
Finished Sep 04 11:39:15 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267709606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.267709606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_alert_test.2583264638
Short name T229
Test name
Test status
Simulation time 11450191 ps
CPU time 0.71 seconds
Started Sep 04 11:38:42 AM UTC 24
Finished Sep 04 11:38:44 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583264638 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2583264638
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.2600497343
Short name T13
Test name
Test status
Simulation time 3145477186 ps
CPU time 105.04 seconds
Started Sep 04 11:38:18 AM UTC 24
Finished Sep 04 11:40:05 AM UTC 24
Peak memory 215820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600497343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2600497343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.1648189790
Short name T236
Test name
Test status
Simulation time 2008030711 ps
CPU time 40.08 seconds
Started Sep 04 11:38:19 AM UTC 24
Finished Sep 04 11:39:01 AM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648189790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1648189790
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.300591965
Short name T278
Test name
Test status
Simulation time 1503657106 ps
CPU time 234.3 seconds
Started Sep 04 11:38:19 AM UTC 24
Finished Sep 04 11:42:17 AM UTC 24
Peak memory 477368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300591965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.300591965
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_error.2749359421
Short name T250
Test name
Test status
Simulation time 55676830955 ps
CPU time 88.52 seconds
Started Sep 04 11:38:23 AM UTC 24
Finished Sep 04 11:39:53 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749359421 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2749359421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_long_msg.1527874130
Short name T226
Test name
Test status
Simulation time 338018470 ps
CPU time 18.51 seconds
Started Sep 04 11:38:17 AM UTC 24
Finished Sep 04 11:38:36 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527874130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1527874130
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_smoke.1289160410
Short name T225
Test name
Test status
Simulation time 551432936 ps
CPU time 13.51 seconds
Started Sep 04 11:38:17 AM UTC 24
Finished Sep 04 11:38:31 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289160410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1289160410
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2773752419
Short name T228
Test name
Test status
Simulation time 983062860 ps
CPU time 9.18 seconds
Started Sep 04 11:38:32 AM UTC 24
Finished Sep 04 11:38:42 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773752419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2773752419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_alert_test.2254219970
Short name T235
Test name
Test status
Simulation time 13675200 ps
CPU time 0.84 seconds
Started Sep 04 11:38:58 AM UTC 24
Finished Sep 04 11:39:00 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254219970 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2254219970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.2611380845
Short name T261
Test name
Test status
Simulation time 6210431428 ps
CPU time 109.19 seconds
Started Sep 04 11:38:45 AM UTC 24
Finished Sep 04 11:40:37 AM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611380845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2611380845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.1537517608
Short name T245
Test name
Test status
Simulation time 2370645028 ps
CPU time 54.9 seconds
Started Sep 04 11:38:47 AM UTC 24
Finished Sep 04 11:39:44 AM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537517608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1537517608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.3364421586
Short name T377
Test name
Test status
Simulation time 13868708785 ps
CPU time 642.36 seconds
Started Sep 04 11:38:47 AM UTC 24
Finished Sep 04 11:49:37 AM UTC 24
Peak memory 719072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364421586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3364421586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_error.1979565202
Short name T79
Test name
Test status
Simulation time 14956359149 ps
CPU time 259.47 seconds
Started Sep 04 11:38:49 AM UTC 24
Finished Sep 04 11:43:13 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979565202 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1979565202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_long_msg.1800796165
Short name T247
Test name
Test status
Simulation time 2416321026 ps
CPU time 60.32 seconds
Started Sep 04 11:38:45 AM UTC 24
Finished Sep 04 11:39:47 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800796165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1800796165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_smoke.1853213875
Short name T233
Test name
Test status
Simulation time 1524173997 ps
CPU time 8.37 seconds
Started Sep 04 11:38:45 AM UTC 24
Finished Sep 04 11:38:54 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853213875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1853213875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_stress_all.309839002
Short name T298
Test name
Test status
Simulation time 16057504458 ps
CPU time 280.48 seconds
Started Sep 04 11:38:58 AM UTC 24
Finished Sep 04 11:43:43 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309839002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.309839002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.3300845577
Short name T98
Test name
Test status
Simulation time 6762993513 ps
CPU time 85.15 seconds
Started Sep 04 11:38:49 AM UTC 24
Finished Sep 04 11:40:16 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300845577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3300845577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_alert_test.2536633421
Short name T241
Test name
Test status
Simulation time 24343315 ps
CPU time 0.87 seconds
Started Sep 04 11:39:27 AM UTC 24
Finished Sep 04 11:39:29 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536633421 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2536633421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.1312041162
Short name T257
Test name
Test status
Simulation time 9352046696 ps
CPU time 82.43 seconds
Started Sep 04 11:39:02 AM UTC 24
Finished Sep 04 11:40:26 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312041162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1312041162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.1684932438
Short name T164
Test name
Test status
Simulation time 664228646 ps
CPU time 8.73 seconds
Started Sep 04 11:39:14 AM UTC 24
Finished Sep 04 11:39:24 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684932438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1684932438
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.606589373
Short name T310
Test name
Test status
Simulation time 7022729720 ps
CPU time 369.95 seconds
Started Sep 04 11:39:07 AM UTC 24
Finished Sep 04 11:45:21 AM UTC 24
Peak memory 696600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606589373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.606589373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_error.1673128522
Short name T270
Test name
Test status
Simulation time 45820613886 ps
CPU time 148.22 seconds
Started Sep 04 11:39:16 AM UTC 24
Finished Sep 04 11:41:47 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673128522 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1673128522
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_long_msg.494021406
Short name T239
Test name
Test status
Simulation time 711425453 ps
CPU time 12.87 seconds
Started Sep 04 11:39:01 AM UTC 24
Finished Sep 04 11:39:15 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494021406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.494021406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_smoke.2703371134
Short name T237
Test name
Test status
Simulation time 4160146123 ps
CPU time 4.56 seconds
Started Sep 04 11:39:01 AM UTC 24
Finished Sep 04 11:39:06 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703371134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2703371134
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2797948742
Short name T515
Test name
Test status
Simulation time 271127743238 ps
CPU time 1760.79 seconds
Started Sep 04 11:39:26 AM UTC 24
Finished Sep 04 12:09:07 PM UTC 24
Peak memory 768288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797948742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2797948742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.973811103
Short name T264
Test name
Test status
Simulation time 4437350484 ps
CPU time 89.66 seconds
Started Sep 04 11:39:16 AM UTC 24
Finished Sep 04 11:40:48 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973811103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.973811103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_alert_test.705909620
Short name T251
Test name
Test status
Simulation time 11278804 ps
CPU time 0.83 seconds
Started Sep 04 11:39:57 AM UTC 24
Finished Sep 04 11:40:00 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705909620 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.705909620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.4156634677
Short name T265
Test name
Test status
Simulation time 1316547415 ps
CPU time 81.23 seconds
Started Sep 04 11:39:36 AM UTC 24
Finished Sep 04 11:41:00 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156634677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4156634677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.4164292701
Short name T253
Test name
Test status
Simulation time 1322957436 ps
CPU time 26.17 seconds
Started Sep 04 11:39:44 AM UTC 24
Finished Sep 04 11:40:12 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164292701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4164292701
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3609590769
Short name T441
Test name
Test status
Simulation time 21616965079 ps
CPU time 832.29 seconds
Started Sep 04 11:39:44 AM UTC 24
Finished Sep 04 11:53:45 AM UTC 24
Peak memory 745948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609590769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3609590769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_error.2675887775
Short name T260
Test name
Test status
Simulation time 1525464679 ps
CPU time 46.73 seconds
Started Sep 04 11:39:46 AM UTC 24
Finished Sep 04 11:40:35 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675887775 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2675887775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3489589943
Short name T254
Test name
Test status
Simulation time 560568556 ps
CPU time 40.03 seconds
Started Sep 04 11:39:35 AM UTC 24
Finished Sep 04 11:40:18 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489589943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3489589943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_smoke.896431581
Short name T243
Test name
Test status
Simulation time 363783188 ps
CPU time 2.35 seconds
Started Sep 04 11:39:30 AM UTC 24
Finished Sep 04 11:39:34 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896431581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.896431581
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_stress_all.1078007542
Short name T529
Test name
Test status
Simulation time 149365749188 ps
CPU time 3083.4 seconds
Started Sep 04 11:39:57 AM UTC 24
Finished Sep 04 12:31:56 PM UTC 24
Peak memory 852220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078007542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1078007542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.473216217
Short name T268
Test name
Test status
Simulation time 10888347598 ps
CPU time 103.89 seconds
Started Sep 04 11:39:48 AM UTC 24
Finished Sep 04 11:41:35 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473216217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.473216217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_alert_test.3138497127
Short name T53
Test name
Test status
Simulation time 13988250 ps
CPU time 0.7 seconds
Started Sep 04 11:14:15 AM UTC 24
Finished Sep 04 11:14:16 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138497127 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3138497127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.2677262193
Short name T11
Test name
Test status
Simulation time 2044975534 ps
CPU time 29.67 seconds
Started Sep 04 11:07:52 AM UTC 24
Finished Sep 04 11:08:23 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677262193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2677262193
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.2436488758
Short name T154
Test name
Test status
Simulation time 9009158024 ps
CPU time 646.82 seconds
Started Sep 04 11:08:19 AM UTC 24
Finished Sep 04 11:19:15 AM UTC 24
Peak memory 692708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436488758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2436488758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_error.497329932
Short name T30
Test name
Test status
Simulation time 43960568346 ps
CPU time 125.77 seconds
Started Sep 04 11:08:24 AM UTC 24
Finished Sep 04 11:10:33 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497329932 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.497329932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_long_msg.808300535
Short name T146
Test name
Test status
Simulation time 3260910379 ps
CPU time 57.23 seconds
Started Sep 04 11:07:21 AM UTC 24
Finished Sep 04 11:08:20 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808300535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.808300535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.4252238186
Short name T56
Test name
Test status
Simulation time 37376485 ps
CPU time 1.05 seconds
Started Sep 04 11:14:12 AM UTC 24
Finished Sep 04 11:14:14 AM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252238186 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4252238186
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_smoke.3556254699
Short name T132
Test name
Test status
Simulation time 70000202 ps
CPU time 2 seconds
Started Sep 04 11:07:17 AM UTC 24
Finished Sep 04 11:07:20 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556254699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3556254699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_stress_all.3625655322
Short name T129
Test name
Test status
Simulation time 45878166298 ps
CPU time 1701.26 seconds
Started Sep 04 11:13:40 AM UTC 24
Finished Sep 04 11:42:23 AM UTC 24
Peak memory 776472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625655322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3625655322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.424792068
Short name T32
Test name
Test status
Simulation time 1255471447 ps
CPU time 45.38 seconds
Started Sep 04 11:11:37 AM UTC 24
Finished Sep 04 11:12:24 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424792068 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.424792068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.1533377960
Short name T33
Test name
Test status
Simulation time 5576397778 ps
CPU time 72.01 seconds
Started Sep 04 11:12:25 AM UTC 24
Finished Sep 04 11:13:39 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533377960 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1533377960
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.848078489
Short name T35
Test name
Test status
Simulation time 28281061528 ps
CPU time 96.97 seconds
Started Sep 04 11:12:32 AM UTC 24
Finished Sep 04 11:14:11 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848078489 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.848078489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.1487221468
Short name T89
Test name
Test status
Simulation time 141556942944 ps
CPU time 656.48 seconds
Started Sep 04 11:08:57 AM UTC 24
Finished Sep 04 11:20:03 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487221468 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1487221468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1222314537
Short name T362
Test name
Test status
Simulation time 54004342955 ps
CPU time 2296.64 seconds
Started Sep 04 11:09:59 AM UTC 24
Finished Sep 04 11:48:45 AM UTC 24
Peak memory 227320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222314537 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1222314537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.2188843268
Short name T477
Test name
Test status
Simulation time 863972788308 ps
CPU time 2751.63 seconds
Started Sep 04 11:10:34 AM UTC 24
Finished Sep 04 11:57:01 AM UTC 24
Peak memory 225344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188843268 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2188843268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.3407926551
Short name T25
Test name
Test status
Simulation time 1507298117 ps
CPU time 71.48 seconds
Started Sep 04 11:08:44 AM UTC 24
Finished Sep 04 11:09:58 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407926551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3407926551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_alert_test.3204702562
Short name T255
Test name
Test status
Simulation time 31836413 ps
CPU time 0.85 seconds
Started Sep 04 11:40:20 AM UTC 24
Finished Sep 04 11:40:22 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204702562 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3204702562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.330822042
Short name T271
Test name
Test status
Simulation time 1468351696 ps
CPU time 111.04 seconds
Started Sep 04 11:39:57 AM UTC 24
Finished Sep 04 11:41:50 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330822042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.330822042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.1663091063
Short name T258
Test name
Test status
Simulation time 884696132 ps
CPU time 21.02 seconds
Started Sep 04 11:40:07 AM UTC 24
Finished Sep 04 11:40:30 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663091063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1663091063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.1159504840
Short name T297
Test name
Test status
Simulation time 2176608109 ps
CPU time 217.74 seconds
Started Sep 04 11:40:00 AM UTC 24
Finished Sep 04 11:43:41 AM UTC 24
Peak memory 657696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159504840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1159504840
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_error.3422406028
Short name T40
Test name
Test status
Simulation time 13776182116 ps
CPU time 241.82 seconds
Started Sep 04 11:40:10 AM UTC 24
Finished Sep 04 11:44:16 AM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422406028 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3422406028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_long_msg.406545339
Short name T276
Test name
Test status
Simulation time 26391152574 ps
CPU time 133.2 seconds
Started Sep 04 11:39:57 AM UTC 24
Finished Sep 04 11:42:13 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406545339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.406545339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_smoke.1898314714
Short name T252
Test name
Test status
Simulation time 790879368 ps
CPU time 11.51 seconds
Started Sep 04 11:39:57 AM UTC 24
Finished Sep 04 11:40:10 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898314714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1898314714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_stress_all.1136501711
Short name T70
Test name
Test status
Simulation time 901258066868 ps
CPU time 2205.79 seconds
Started Sep 04 11:40:18 AM UTC 24
Finished Sep 04 12:17:31 PM UTC 24
Peak memory 751888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136501711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1136501711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.660002117
Short name T127
Test name
Test status
Simulation time 17690429069 ps
CPU time 132.32 seconds
Started Sep 04 11:40:12 AM UTC 24
Finished Sep 04 11:42:27 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660002117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.660002117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2146724594
Short name T263
Test name
Test status
Simulation time 23659854 ps
CPU time 0.83 seconds
Started Sep 04 11:40:40 AM UTC 24
Finished Sep 04 11:40:42 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146724594 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2146724594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.737483728
Short name T280
Test name
Test status
Simulation time 1500176531 ps
CPU time 112.81 seconds
Started Sep 04 11:40:24 AM UTC 24
Finished Sep 04 11:42:19 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737483728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.737483728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.3693491127
Short name T274
Test name
Test status
Simulation time 5386853955 ps
CPU time 96.97 seconds
Started Sep 04 11:40:31 AM UTC 24
Finished Sep 04 11:42:10 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693491127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3693491127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3892498976
Short name T323
Test name
Test status
Simulation time 6956923074 ps
CPU time 347.5 seconds
Started Sep 04 11:40:28 AM UTC 24
Finished Sep 04 11:46:20 AM UTC 24
Peak memory 719320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892498976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3892498976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_error.765444430
Short name T302
Test name
Test status
Simulation time 57035201902 ps
CPU time 230.26 seconds
Started Sep 04 11:40:36 AM UTC 24
Finished Sep 04 11:44:30 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765444430 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.765444430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_long_msg.4205567087
Short name T287
Test name
Test status
Simulation time 47008157517 ps
CPU time 144.12 seconds
Started Sep 04 11:40:22 AM UTC 24
Finished Sep 04 11:42:49 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205567087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4205567087
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_smoke.2265258928
Short name T262
Test name
Test status
Simulation time 3511038277 ps
CPU time 18.38 seconds
Started Sep 04 11:40:20 AM UTC 24
Finished Sep 04 11:40:40 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265258928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2265258928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_stress_all.1704308463
Short name T86
Test name
Test status
Simulation time 7514665413 ps
CPU time 178.78 seconds
Started Sep 04 11:40:38 AM UTC 24
Finished Sep 04 11:43:40 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704308463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1704308463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.2241733714
Short name T267
Test name
Test status
Simulation time 3950624080 ps
CPU time 27.29 seconds
Started Sep 04 11:40:36 AM UTC 24
Finished Sep 04 11:41:05 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241733714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2241733714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_alert_test.3546608932
Short name T269
Test name
Test status
Simulation time 11448997 ps
CPU time 0.81 seconds
Started Sep 04 11:41:39 AM UTC 24
Finished Sep 04 11:41:41 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546608932 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3546608932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.2121566904
Short name T285
Test name
Test status
Simulation time 20950524880 ps
CPU time 101.52 seconds
Started Sep 04 11:40:51 AM UTC 24
Finished Sep 04 11:42:35 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121566904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2121566904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.4155191963
Short name T48
Test name
Test status
Simulation time 694195273 ps
CPU time 34.66 seconds
Started Sep 04 11:41:02 AM UTC 24
Finished Sep 04 11:41:38 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155191963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4155191963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.470673606
Short name T319
Test name
Test status
Simulation time 7409009005 ps
CPU time 314.96 seconds
Started Sep 04 11:40:55 AM UTC 24
Finished Sep 04 11:46:14 AM UTC 24
Peak memory 504032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470673606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.470673606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_error.91403592
Short name T306
Test name
Test status
Simulation time 15060048036 ps
CPU time 235.82 seconds
Started Sep 04 11:41:04 AM UTC 24
Finished Sep 04 11:45:03 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91403592 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.91403592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_long_msg.3728036199
Short name T289
Test name
Test status
Simulation time 4767287218 ps
CPU time 123.5 seconds
Started Sep 04 11:40:49 AM UTC 24
Finished Sep 04 11:42:54 AM UTC 24
Peak memory 217944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728036199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3728036199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_smoke.859291928
Short name T227
Test name
Test status
Simulation time 754179735 ps
CPU time 10.18 seconds
Started Sep 04 11:40:43 AM UTC 24
Finished Sep 04 11:40:54 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859291928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.859291928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_stress_all.1030611886
Short name T412
Test name
Test status
Simulation time 127407077105 ps
CPU time 597.48 seconds
Started Sep 04 11:41:37 AM UTC 24
Finished Sep 04 11:51:41 AM UTC 24
Peak memory 215756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030611886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1030611886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.751450520
Short name T292
Test name
Test status
Simulation time 1912725767 ps
CPU time 109.08 seconds
Started Sep 04 11:41:06 AM UTC 24
Finished Sep 04 11:42:57 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751450520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.751450520
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_alert_test.3192078766
Short name T279
Test name
Test status
Simulation time 12187479 ps
CPU time 0.79 seconds
Started Sep 04 11:42:16 AM UTC 24
Finished Sep 04 11:42:18 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192078766 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3192078766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.1562796244
Short name T272
Test name
Test status
Simulation time 219243298 ps
CPU time 5.37 seconds
Started Sep 04 11:41:52 AM UTC 24
Finished Sep 04 11:41:59 AM UTC 24
Peak memory 207068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562796244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1562796244
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.3298531967
Short name T277
Test name
Test status
Simulation time 585843814 ps
CPU time 9.1 seconds
Started Sep 04 11:42:05 AM UTC 24
Finished Sep 04 11:42:15 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298531967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3298531967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.1316157432
Short name T507
Test name
Test status
Simulation time 45270688924 ps
CPU time 1486.36 seconds
Started Sep 04 11:42:00 AM UTC 24
Finished Sep 04 12:07:02 PM UTC 24
Peak memory 792848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316157432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1316157432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_error.233812839
Short name T299
Test name
Test status
Simulation time 1375993660 ps
CPU time 93.12 seconds
Started Sep 04 11:42:11 AM UTC 24
Finished Sep 04 11:43:46 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233812839 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.233812839
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_long_msg.4249700790
Short name T283
Test name
Test status
Simulation time 1012653679 ps
CPU time 37.93 seconds
Started Sep 04 11:41:48 AM UTC 24
Finished Sep 04 11:42:28 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249700790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4249700790
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_smoke.2463569493
Short name T273
Test name
Test status
Simulation time 705077044 ps
CPU time 20.87 seconds
Started Sep 04 11:41:42 AM UTC 24
Finished Sep 04 11:42:04 AM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463569493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2463569493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_stress_all.58082284
Short name T512
Test name
Test status
Simulation time 45832756218 ps
CPU time 1540.9 seconds
Started Sep 04 11:42:14 AM UTC 24
Finished Sep 04 12:08:12 PM UTC 24
Peak memory 778476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58082284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.58082284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3575951474
Short name T42
Test name
Test status
Simulation time 2189256863 ps
CPU time 121.21 seconds
Started Sep 04 11:42:14 AM UTC 24
Finished Sep 04 11:44:18 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575951474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3575951474
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_alert_test.4036604490
Short name T286
Test name
Test status
Simulation time 12441397 ps
CPU time 0.9 seconds
Started Sep 04 11:42:45 AM UTC 24
Finished Sep 04 11:42:47 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036604490 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4036604490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.3726241143
Short name T36
Test name
Test status
Simulation time 1498032486 ps
CPU time 94.64 seconds
Started Sep 04 11:42:21 AM UTC 24
Finished Sep 04 11:43:59 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726241143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3726241143
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2278902584
Short name T85
Test name
Test status
Simulation time 5545020080 ps
CPU time 52.16 seconds
Started Sep 04 11:42:39 AM UTC 24
Finished Sep 04 11:43:32 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278902584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2278902584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.1102558964
Short name T460
Test name
Test status
Simulation time 3715476790 ps
CPU time 773.86 seconds
Started Sep 04 11:42:22 AM UTC 24
Finished Sep 04 11:55:25 AM UTC 24
Peak memory 715232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102558964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1102558964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_error.2329898559
Short name T313
Test name
Test status
Simulation time 12048303847 ps
CPU time 193.8 seconds
Started Sep 04 11:42:39 AM UTC 24
Finished Sep 04 11:45:56 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329898559 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2329898559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_long_msg.2617854542
Short name T288
Test name
Test status
Simulation time 2674644967 ps
CPU time 32.17 seconds
Started Sep 04 11:42:19 AM UTC 24
Finished Sep 04 11:42:52 AM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617854542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2617854542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_smoke.467883136
Short name T281
Test name
Test status
Simulation time 45703758 ps
CPU time 1.15 seconds
Started Sep 04 11:42:19 AM UTC 24
Finished Sep 04 11:42:21 AM UTC 24
Peak memory 206348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467883136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.467883136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_stress_all.1010100874
Short name T348
Test name
Test status
Simulation time 10668256995 ps
CPU time 281.47 seconds
Started Sep 04 11:42:45 AM UTC 24
Finished Sep 04 11:47:30 AM UTC 24
Peak memory 424256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010100874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1010100874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.4252601174
Short name T296
Test name
Test status
Simulation time 4467121260 ps
CPU time 53.2 seconds
Started Sep 04 11:42:45 AM UTC 24
Finished Sep 04 11:43:40 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252601174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.4252601174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_alert_test.518820315
Short name T293
Test name
Test status
Simulation time 158841596 ps
CPU time 0.8 seconds
Started Sep 04 11:42:59 AM UTC 24
Finished Sep 04 11:43:01 AM UTC 24
Peak memory 203544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518820315 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.518820315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.105793998
Short name T291
Test name
Test status
Simulation time 195768450 ps
CPU time 4.12 seconds
Started Sep 04 11:42:50 AM UTC 24
Finished Sep 04 11:42:55 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105793998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.105793998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.1154043859
Short name T435
Test name
Test status
Simulation time 19317765065 ps
CPU time 629.26 seconds
Started Sep 04 11:42:48 AM UTC 24
Finished Sep 04 11:53:25 AM UTC 24
Peak memory 708880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154043859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1154043859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_error.2174435996
Short name T336
Test name
Test status
Simulation time 38856092774 ps
CPU time 249.69 seconds
Started Sep 04 11:42:53 AM UTC 24
Finished Sep 04 11:47:07 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174435996 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2174435996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_long_msg.2995342188
Short name T303
Test name
Test status
Simulation time 4603700149 ps
CPU time 103.84 seconds
Started Sep 04 11:42:45 AM UTC 24
Finished Sep 04 11:44:31 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995342188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2995342188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_smoke.2139822938
Short name T294
Test name
Test status
Simulation time 3812600082 ps
CPU time 14.76 seconds
Started Sep 04 11:42:45 AM UTC 24
Finished Sep 04 11:43:01 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139822938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2139822938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_stress_all.1093538941
Short name T134
Test name
Test status
Simulation time 239843588332 ps
CPU time 382.17 seconds
Started Sep 04 11:42:56 AM UTC 24
Finished Sep 04 11:49:23 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093538941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1093538941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.1682968627
Short name T99
Test name
Test status
Simulation time 28144782266 ps
CPU time 88.74 seconds
Started Sep 04 11:42:56 AM UTC 24
Finished Sep 04 11:44:27 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682968627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1682968627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_alert_test.1671861768
Short name T83
Test name
Test status
Simulation time 37701414 ps
CPU time 0.85 seconds
Started Sep 04 11:43:25 AM UTC 24
Finished Sep 04 11:43:27 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671861768 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1671861768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.2664825865
Short name T41
Test name
Test status
Simulation time 1160274530 ps
CPU time 72.67 seconds
Started Sep 04 11:43:02 AM UTC 24
Finished Sep 04 11:44:17 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664825865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2664825865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.1072564407
Short name T80
Test name
Test status
Simulation time 1842042669 ps
CPU time 11.88 seconds
Started Sep 04 11:43:09 AM UTC 24
Finished Sep 04 11:43:22 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072564407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1072564407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.1404333577
Short name T361
Test name
Test status
Simulation time 8329601328 ps
CPU time 326.22 seconds
Started Sep 04 11:43:04 AM UTC 24
Finished Sep 04 11:48:35 AM UTC 24
Peak memory 686352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404333577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1404333577
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_error.1060176359
Short name T321
Test name
Test status
Simulation time 10785620800 ps
CPU time 182.69 seconds
Started Sep 04 11:43:12 AM UTC 24
Finished Sep 04 11:46:18 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060176359 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1060176359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_long_msg.1253337890
Short name T315
Test name
Test status
Simulation time 23345029298 ps
CPU time 173.04 seconds
Started Sep 04 11:43:01 AM UTC 24
Finished Sep 04 11:45:57 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253337890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1253337890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_smoke.263438178
Short name T295
Test name
Test status
Simulation time 163994602 ps
CPU time 3.27 seconds
Started Sep 04 11:42:59 AM UTC 24
Finished Sep 04 11:43:03 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263438178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.263438178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_stress_all.3495714307
Short name T314
Test name
Test status
Simulation time 20770652992 ps
CPU time 150.24 seconds
Started Sep 04 11:43:23 AM UTC 24
Finished Sep 04 11:45:56 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495714307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3495714307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.3720535751
Short name T81
Test name
Test status
Simulation time 1332811505 ps
CPU time 9.04 seconds
Started Sep 04 11:43:14 AM UTC 24
Finished Sep 04 11:43:24 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720535751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3720535751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_alert_test.2299150811
Short name T300
Test name
Test status
Simulation time 12082576 ps
CPU time 0.88 seconds
Started Sep 04 11:43:47 AM UTC 24
Finished Sep 04 11:43:49 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299150811 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2299150811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.1639206654
Short name T38
Test name
Test status
Simulation time 496768976 ps
CPU time 34.55 seconds
Started Sep 04 11:43:32 AM UTC 24
Finished Sep 04 11:44:08 AM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639206654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1639206654
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.857060664
Short name T39
Test name
Test status
Simulation time 3462608707 ps
CPU time 27.79 seconds
Started Sep 04 11:43:42 AM UTC 24
Finished Sep 04 11:44:11 AM UTC 24
Peak memory 215892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857060664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.857060664
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.697558382
Short name T457
Test name
Test status
Simulation time 3581064147 ps
CPU time 689.82 seconds
Started Sep 04 11:43:33 AM UTC 24
Finished Sep 04 11:55:11 AM UTC 24
Peak memory 688604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697558382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.697558382
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_error.2568981114
Short name T353
Test name
Test status
Simulation time 25454861697 ps
CPU time 232.54 seconds
Started Sep 04 11:43:42 AM UTC 24
Finished Sep 04 11:47:38 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568981114 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2568981114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_long_msg.341990627
Short name T316
Test name
Test status
Simulation time 10222672490 ps
CPU time 149.14 seconds
Started Sep 04 11:43:28 AM UTC 24
Finished Sep 04 11:46:00 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341990627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.341990627
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_smoke.1325726928
Short name T84
Test name
Test status
Simulation time 237601366 ps
CPU time 2.91 seconds
Started Sep 04 11:43:27 AM UTC 24
Finished Sep 04 11:43:31 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325726928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1325726928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_stress_all.1295918837
Short name T374
Test name
Test status
Simulation time 38595751328 ps
CPU time 334.65 seconds
Started Sep 04 11:43:46 AM UTC 24
Finished Sep 04 11:49:25 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295918837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1295918837
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.2107052169
Short name T309
Test name
Test status
Simulation time 26224608767 ps
CPU time 91.29 seconds
Started Sep 04 11:43:43 AM UTC 24
Finished Sep 04 11:45:17 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107052169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2107052169
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1825249342
Short name T43
Test name
Test status
Simulation time 27171660 ps
CPU time 0.85 seconds
Started Sep 04 11:44:18 AM UTC 24
Finished Sep 04 11:44:21 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825249342 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1825249342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2915172358
Short name T301
Test name
Test status
Simulation time 372986353 ps
CPU time 23.99 seconds
Started Sep 04 11:44:01 AM UTC 24
Finished Sep 04 11:44:26 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915172358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2915172358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.2285790407
Short name T163
Test name
Test status
Simulation time 273746571 ps
CPU time 20.17 seconds
Started Sep 04 11:44:07 AM UTC 24
Finished Sep 04 11:44:29 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285790407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2285790407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.1783478418
Short name T486
Test name
Test status
Simulation time 4941970066 ps
CPU time 850.1 seconds
Started Sep 04 11:44:01 AM UTC 24
Finished Sep 04 11:58:21 AM UTC 24
Peak memory 764128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783478418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1783478418
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_error.211318000
Short name T322
Test name
Test status
Simulation time 29316062215 ps
CPU time 126.94 seconds
Started Sep 04 11:44:09 AM UTC 24
Finished Sep 04 11:46:19 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211318000 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.211318000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_long_msg.3613035524
Short name T342
Test name
Test status
Simulation time 99256075311 ps
CPU time 193.76 seconds
Started Sep 04 11:43:57 AM UTC 24
Finished Sep 04 11:47:14 AM UTC 24
Peak memory 215752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613035524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3613035524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_smoke.2015827668
Short name T37
Test name
Test status
Simulation time 245448420 ps
CPU time 14.89 seconds
Started Sep 04 11:43:51 AM UTC 24
Finished Sep 04 11:44:07 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015827668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2015827668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_stress_all.941539550
Short name T102
Test name
Test status
Simulation time 289243491980 ps
CPU time 470.86 seconds
Started Sep 04 11:44:18 AM UTC 24
Finished Sep 04 11:52:16 AM UTC 24
Peak memory 665900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941539550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.941539550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.3255401226
Short name T308
Test name
Test status
Simulation time 5505842505 ps
CPU time 59.95 seconds
Started Sep 04 11:44:12 AM UTC 24
Finished Sep 04 11:45:13 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255401226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3255401226
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_alert_test.1570291464
Short name T305
Test name
Test status
Simulation time 25025715 ps
CPU time 0.87 seconds
Started Sep 04 11:44:41 AM UTC 24
Finished Sep 04 11:44:43 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570291464 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1570291464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.3384197223
Short name T329
Test name
Test status
Simulation time 2091703866 ps
CPU time 128.47 seconds
Started Sep 04 11:44:24 AM UTC 24
Finished Sep 04 11:46:35 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384197223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3384197223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.2182284639
Short name T312
Test name
Test status
Simulation time 2532182989 ps
CPU time 65.29 seconds
Started Sep 04 11:44:29 AM UTC 24
Finished Sep 04 11:45:36 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182284639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2182284639
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.3767150411
Short name T324
Test name
Test status
Simulation time 880581000 ps
CPU time 110.55 seconds
Started Sep 04 11:44:28 AM UTC 24
Finished Sep 04 11:46:20 AM UTC 24
Peak memory 403236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767150411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3767150411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_error.2026003396
Short name T335
Test name
Test status
Simulation time 2079759644 ps
CPU time 151.42 seconds
Started Sep 04 11:44:29 AM UTC 24
Finished Sep 04 11:47:03 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026003396 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2026003396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_long_msg.2119243890
Short name T320
Test name
Test status
Simulation time 7799142907 ps
CPU time 110.47 seconds
Started Sep 04 11:44:22 AM UTC 24
Finished Sep 04 11:46:15 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119243890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2119243890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_smoke.1436441188
Short name T44
Test name
Test status
Simulation time 121910063 ps
CPU time 2.1 seconds
Started Sep 04 11:44:20 AM UTC 24
Finished Sep 04 11:44:23 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436441188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1436441188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_stress_all.318277625
Short name T517
Test name
Test status
Simulation time 376713828226 ps
CPU time 1615.06 seconds
Started Sep 04 11:44:33 AM UTC 24
Finished Sep 04 12:11:47 PM UTC 24
Peak memory 741640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318277625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.318277625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.1804576842
Short name T340
Test name
Test status
Simulation time 7255508414 ps
CPU time 156.68 seconds
Started Sep 04 11:44:31 AM UTC 24
Finished Sep 04 11:47:11 AM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804576842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1804576842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_alert_test.2472712176
Short name T95
Test name
Test status
Simulation time 90830172 ps
CPU time 0.67 seconds
Started Sep 04 11:24:31 AM UTC 24
Finished Sep 04 11:24:32 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472712176 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2472712176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.1408096745
Short name T49
Test name
Test status
Simulation time 1120655797 ps
CPU time 64.22 seconds
Started Sep 04 11:16:27 AM UTC 24
Finished Sep 04 11:17:33 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408096745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1408096745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.2230888675
Short name T167
Test name
Test status
Simulation time 14181836848 ps
CPU time 46.95 seconds
Started Sep 04 11:17:11 AM UTC 24
Finished Sep 04 11:18:00 AM UTC 24
Peak memory 217740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230888675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2230888675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.4175595634
Short name T91
Test name
Test status
Simulation time 4825505572 ps
CPU time 233.49 seconds
Started Sep 04 11:17:09 AM UTC 24
Finished Sep 04 11:21:07 AM UTC 24
Peak memory 496044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175595634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4175595634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_error.1271675699
Short name T173
Test name
Test status
Simulation time 14304378198 ps
CPU time 41.19 seconds
Started Sep 04 11:17:34 AM UTC 24
Finished Sep 04 11:18:17 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271675699 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1271675699
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2496255917
Short name T57
Test name
Test status
Simulation time 89680079 ps
CPU time 1.07 seconds
Started Sep 04 11:24:27 AM UTC 24
Finished Sep 04 11:24:30 AM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496255917 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2496255917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_smoke.2975002088
Short name T67
Test name
Test status
Simulation time 1876050226 ps
CPU time 7.74 seconds
Started Sep 04 11:14:17 AM UTC 24
Finished Sep 04 11:14:26 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975002088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2975002088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_stress_all.405826404
Short name T73
Test name
Test status
Simulation time 365962034841 ps
CPU time 6005.71 seconds
Started Sep 04 11:21:48 AM UTC 24
Finished Sep 04 01:03:07 PM UTC 24
Peak memory 919752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405826404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.405826404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3143906314
Short name T90
Test name
Test status
Simulation time 4891048557 ps
CPU time 44.26 seconds
Started Sep 04 11:20:06 AM UTC 24
Finished Sep 04 11:20:52 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143906314 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3143906314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.3559500267
Short name T92
Test name
Test status
Simulation time 32229763220 ps
CPU time 53.38 seconds
Started Sep 04 11:20:53 AM UTC 24
Finished Sep 04 11:21:48 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559500267 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3559500267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.1486248738
Short name T93
Test name
Test status
Simulation time 46095378132 ps
CPU time 131.74 seconds
Started Sep 04 11:21:08 AM UTC 24
Finished Sep 04 11:23:22 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486248738 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1486248738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.103378361
Short name T150
Test name
Test status
Simulation time 36755005096 ps
CPU time 659.68 seconds
Started Sep 04 11:18:18 AM UTC 24
Finished Sep 04 11:29:27 AM UTC 24
Peak memory 207172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103378361 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.103378361
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.1355972684
Short name T510
Test name
Test status
Simulation time 866397281374 ps
CPU time 2886.56 seconds
Started Sep 04 11:19:17 AM UTC 24
Finished Sep 04 12:08:01 PM UTC 24
Peak memory 227400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355972684 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1355972684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.127303765
Short name T496
Test name
Test status
Simulation time 76479657208 ps
CPU time 2417.18 seconds
Started Sep 04 11:19:42 AM UTC 24
Finished Sep 04 12:00:31 PM UTC 24
Peak memory 227588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127303765 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.127303765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.2348422094
Short name T88
Test name
Test status
Simulation time 83008879453 ps
CPU time 98.31 seconds
Started Sep 04 11:18:01 AM UTC 24
Finished Sep 04 11:19:41 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348422094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2348422094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_alert_test.1477554746
Short name T317
Test name
Test status
Simulation time 32290664 ps
CPU time 0.79 seconds
Started Sep 04 11:45:59 AM UTC 24
Finished Sep 04 11:46:01 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477554746 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1477554746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.600490656
Short name T325
Test name
Test status
Simulation time 2781091372 ps
CPU time 73.03 seconds
Started Sep 04 11:45:06 AM UTC 24
Finished Sep 04 11:46:21 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600490656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.600490656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.883973078
Short name T330
Test name
Test status
Simulation time 13879208639 ps
CPU time 77.47 seconds
Started Sep 04 11:45:17 AM UTC 24
Finished Sep 04 11:46:37 AM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883973078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.883973078
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.3800482465
Short name T494
Test name
Test status
Simulation time 9701987612 ps
CPU time 835.68 seconds
Started Sep 04 11:45:15 AM UTC 24
Finished Sep 04 11:59:19 AM UTC 24
Peak memory 741648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800482465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3800482465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_error.3497258620
Short name T352
Test name
Test status
Simulation time 8836406677 ps
CPU time 131.16 seconds
Started Sep 04 11:45:23 AM UTC 24
Finished Sep 04 11:47:37 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497258620 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3497258620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_long_msg.3300068899
Short name T357
Test name
Test status
Simulation time 13922982802 ps
CPU time 199.6 seconds
Started Sep 04 11:45:05 AM UTC 24
Finished Sep 04 11:48:28 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300068899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3300068899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_smoke.3343955593
Short name T307
Test name
Test status
Simulation time 3465138760 ps
CPU time 20.09 seconds
Started Sep 04 11:44:44 AM UTC 24
Finished Sep 04 11:45:05 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343955593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3343955593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_stress_all.4143384721
Short name T519
Test name
Test status
Simulation time 26369722842 ps
CPU time 1648.09 seconds
Started Sep 04 11:45:37 AM UTC 24
Finished Sep 04 12:13:25 PM UTC 24
Peak memory 747820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143384721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.4143384721
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.2220373443
Short name T338
Test name
Test status
Simulation time 2177020045 ps
CPU time 99.89 seconds
Started Sep 04 11:45:27 AM UTC 24
Finished Sep 04 11:47:09 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220373443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2220373443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_alert_test.1724153119
Short name T326
Test name
Test status
Simulation time 39616590 ps
CPU time 0.81 seconds
Started Sep 04 11:46:21 AM UTC 24
Finished Sep 04 11:46:23 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724153119 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1724153119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.3380301966
Short name T333
Test name
Test status
Simulation time 1594065158 ps
CPU time 46.87 seconds
Started Sep 04 11:46:01 AM UTC 24
Finished Sep 04 11:46:50 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380301966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3380301966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.2288577932
Short name T331
Test name
Test status
Simulation time 574392594 ps
CPU time 39.38 seconds
Started Sep 04 11:46:03 AM UTC 24
Finished Sep 04 11:46:44 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288577932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2288577932
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.1127079730
Short name T391
Test name
Test status
Simulation time 3214520834 ps
CPU time 252.52 seconds
Started Sep 04 11:46:02 AM UTC 24
Finished Sep 04 11:50:18 AM UTC 24
Peak memory 448712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127079730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1127079730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_error.2767159387
Short name T355
Test name
Test status
Simulation time 8595420215 ps
CPU time 96.22 seconds
Started Sep 04 11:46:16 AM UTC 24
Finished Sep 04 11:47:55 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767159387 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2767159387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_long_msg.3307231698
Short name T349
Test name
Test status
Simulation time 27802115845 ps
CPU time 90.46 seconds
Started Sep 04 11:45:59 AM UTC 24
Finished Sep 04 11:47:32 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307231698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3307231698
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_smoke.3335669049
Short name T318
Test name
Test status
Simulation time 234537024 ps
CPU time 2.16 seconds
Started Sep 04 11:45:59 AM UTC 24
Finished Sep 04 11:46:02 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335669049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3335669049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_stress_all.3692762550
Short name T513
Test name
Test status
Simulation time 99708776455 ps
CPU time 1299.63 seconds
Started Sep 04 11:46:21 AM UTC 24
Finished Sep 04 12:08:16 PM UTC 24
Peak memory 729552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692762550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3692762550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1429233262
Short name T328
Test name
Test status
Simulation time 1001898377 ps
CPU time 17.2 seconds
Started Sep 04 11:46:16 AM UTC 24
Finished Sep 04 11:46:35 AM UTC 24
Peak memory 207136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429233262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1429233262
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_alert_test.997946842
Short name T332
Test name
Test status
Simulation time 15100563 ps
CPU time 0.83 seconds
Started Sep 04 11:46:45 AM UTC 24
Finished Sep 04 11:46:47 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997946842 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.997946842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.591709374
Short name T334
Test name
Test status
Simulation time 1150795262 ps
CPU time 35.93 seconds
Started Sep 04 11:46:24 AM UTC 24
Finished Sep 04 11:47:01 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591709374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.591709374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.1669704182
Short name T344
Test name
Test status
Simulation time 5036443284 ps
CPU time 43.18 seconds
Started Sep 04 11:46:31 AM UTC 24
Finished Sep 04 11:47:16 AM UTC 24
Peak memory 215728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669704182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1669704182
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.2542104848
Short name T483
Test name
Test status
Simulation time 3145847834 ps
CPU time 663.24 seconds
Started Sep 04 11:46:24 AM UTC 24
Finished Sep 04 11:57:36 AM UTC 24
Peak memory 690592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542104848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2542104848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_error.3654481624
Short name T360
Test name
Test status
Simulation time 17447716335 ps
CPU time 113.43 seconds
Started Sep 04 11:46:37 AM UTC 24
Finished Sep 04 11:48:33 AM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654481624 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3654481624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_long_msg.1088491486
Short name T341
Test name
Test status
Simulation time 12628969236 ps
CPU time 48.25 seconds
Started Sep 04 11:46:24 AM UTC 24
Finished Sep 04 11:47:13 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088491486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1088491486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_smoke.3406094075
Short name T327
Test name
Test status
Simulation time 509005522 ps
CPU time 8.22 seconds
Started Sep 04 11:46:21 AM UTC 24
Finished Sep 04 11:46:30 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406094075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3406094075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_stress_all.2645513765
Short name T69
Test name
Test status
Simulation time 61329624538 ps
CPU time 500.76 seconds
Started Sep 04 11:46:38 AM UTC 24
Finished Sep 04 11:55:06 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645513765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2645513765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.3413146612
Short name T345
Test name
Test status
Simulation time 49546673971 ps
CPU time 44.64 seconds
Started Sep 04 11:46:37 AM UTC 24
Finished Sep 04 11:47:23 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413146612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3413146612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_alert_test.1323813775
Short name T343
Test name
Test status
Simulation time 35182325 ps
CPU time 0.87 seconds
Started Sep 04 11:47:13 AM UTC 24
Finished Sep 04 11:47:15 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323813775 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1323813775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.2614892893
Short name T337
Test name
Test status
Simulation time 102898409 ps
CPU time 4.13 seconds
Started Sep 04 11:47:02 AM UTC 24
Finished Sep 04 11:47:08 AM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614892893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2614892893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.3810471238
Short name T347
Test name
Test status
Simulation time 1555698060 ps
CPU time 16.67 seconds
Started Sep 04 11:47:10 AM UTC 24
Finished Sep 04 11:47:28 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810471238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3810471238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.1607326779
Short name T505
Test name
Test status
Simulation time 41795911891 ps
CPU time 1045.01 seconds
Started Sep 04 11:47:05 AM UTC 24
Finished Sep 04 12:04:43 PM UTC 24
Peak memory 758032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607326779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1607326779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_error.2487811308
Short name T358
Test name
Test status
Simulation time 1458964445 ps
CPU time 79.39 seconds
Started Sep 04 11:47:10 AM UTC 24
Finished Sep 04 11:48:31 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487811308 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2487811308
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_long_msg.2283818256
Short name T373
Test name
Test status
Simulation time 35074870751 ps
CPU time 150.53 seconds
Started Sep 04 11:46:51 AM UTC 24
Finished Sep 04 11:49:24 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283818256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2283818256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_smoke.3647856317
Short name T339
Test name
Test status
Simulation time 1290353474 ps
CPU time 20.47 seconds
Started Sep 04 11:46:48 AM UTC 24
Finished Sep 04 11:47:10 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647856317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3647856317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_stress_all.2974711261
Short name T489
Test name
Test status
Simulation time 9756304210 ps
CPU time 677.51 seconds
Started Sep 04 11:47:11 AM UTC 24
Finished Sep 04 11:58:37 AM UTC 24
Peak memory 676196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974711261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2974711261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.2379821865
Short name T393
Test name
Test status
Simulation time 12591923887 ps
CPU time 190.71 seconds
Started Sep 04 11:47:10 AM UTC 24
Finished Sep 04 11:50:24 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379821865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2379821865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_alert_test.1817273462
Short name T350
Test name
Test status
Simulation time 41580694 ps
CPU time 0.89 seconds
Started Sep 04 11:47:34 AM UTC 24
Finished Sep 04 11:47:36 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817273462 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1817273462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.1133607457
Short name T369
Test name
Test status
Simulation time 17511409695 ps
CPU time 112.17 seconds
Started Sep 04 11:47:16 AM UTC 24
Finished Sep 04 11:49:11 AM UTC 24
Peak memory 223644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133607457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1133607457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.2078074614
Short name T165
Test name
Test status
Simulation time 929705838 ps
CPU time 53.51 seconds
Started Sep 04 11:47:24 AM UTC 24
Finished Sep 04 11:48:20 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078074614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2078074614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.2759409177
Short name T437
Test name
Test status
Simulation time 2147621730 ps
CPU time 372.36 seconds
Started Sep 04 11:47:16 AM UTC 24
Finished Sep 04 11:53:33 AM UTC 24
Peak memory 696516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759409177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2759409177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_error.2356249274
Short name T399
Test name
Test status
Simulation time 63726167491 ps
CPU time 198.82 seconds
Started Sep 04 11:47:28 AM UTC 24
Finished Sep 04 11:50:50 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356249274 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2356249274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_long_msg.1596105063
Short name T384
Test name
Test status
Simulation time 6940455530 ps
CPU time 159.81 seconds
Started Sep 04 11:47:16 AM UTC 24
Finished Sep 04 11:49:59 AM UTC 24
Peak memory 223692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596105063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1596105063
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_smoke.570199274
Short name T346
Test name
Test status
Simulation time 169714856 ps
CPU time 9.64 seconds
Started Sep 04 11:47:16 AM UTC 24
Finished Sep 04 11:47:27 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570199274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.570199274
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_stress_all.121666080
Short name T403
Test name
Test status
Simulation time 17313154418 ps
CPU time 195.51 seconds
Started Sep 04 11:47:34 AM UTC 24
Finished Sep 04 11:50:52 AM UTC 24
Peak memory 215776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121666080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.121666080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.3215194663
Short name T363
Test name
Test status
Simulation time 24268220012 ps
CPU time 77.26 seconds
Started Sep 04 11:47:29 AM UTC 24
Finished Sep 04 11:48:48 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215194663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3215194663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_alert_test.3437745011
Short name T359
Test name
Test status
Simulation time 15845106 ps
CPU time 0.87 seconds
Started Sep 04 11:48:30 AM UTC 24
Finished Sep 04 11:48:31 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437745011 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3437745011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.2789014021
Short name T365
Test name
Test status
Simulation time 899966905 ps
CPU time 68.36 seconds
Started Sep 04 11:47:41 AM UTC 24
Finished Sep 04 11:48:51 AM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789014021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2789014021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.1867454413
Short name T366
Test name
Test status
Simulation time 4303146076 ps
CPU time 59.37 seconds
Started Sep 04 11:47:53 AM UTC 24
Finished Sep 04 11:48:54 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867454413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1867454413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.4069306379
Short name T504
Test name
Test status
Simulation time 4875754990 ps
CPU time 1005.72 seconds
Started Sep 04 11:47:41 AM UTC 24
Finished Sep 04 12:04:38 PM UTC 24
Peak memory 731492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069306379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.4069306379
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_error.1418484214
Short name T379
Test name
Test status
Simulation time 30029228858 ps
CPU time 104.97 seconds
Started Sep 04 11:47:55 AM UTC 24
Finished Sep 04 11:49:42 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418484214 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1418484214
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_long_msg.1659728686
Short name T372
Test name
Test status
Simulation time 8632133042 ps
CPU time 100.3 seconds
Started Sep 04 11:47:41 AM UTC 24
Finished Sep 04 11:49:23 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659728686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1659728686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_smoke.3874707879
Short name T354
Test name
Test status
Simulation time 1496573845 ps
CPU time 13.86 seconds
Started Sep 04 11:47:37 AM UTC 24
Finished Sep 04 11:47:52 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874707879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3874707879
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_stress_all.4048525973
Short name T503
Test name
Test status
Simulation time 14528988376 ps
CPU time 960.34 seconds
Started Sep 04 11:48:21 AM UTC 24
Finished Sep 04 12:04:34 PM UTC 24
Peak memory 624932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048525973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4048525973
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.1582279211
Short name T385
Test name
Test status
Simulation time 21562185856 ps
CPU time 101.64 seconds
Started Sep 04 11:48:16 AM UTC 24
Finished Sep 04 11:50:00 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582279211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1582279211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_alert_test.3156412187
Short name T368
Test name
Test status
Simulation time 18977223 ps
CPU time 0.76 seconds
Started Sep 04 11:48:56 AM UTC 24
Finished Sep 04 11:48:59 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156412187 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3156412187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.3469711977
Short name T28
Test name
Test status
Simulation time 1220813968 ps
CPU time 89.61 seconds
Started Sep 04 11:48:34 AM UTC 24
Finished Sep 04 11:50:05 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469711977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3469711977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3854666899
Short name T382
Test name
Test status
Simulation time 13531131886 ps
CPU time 57.99 seconds
Started Sep 04 11:48:54 AM UTC 24
Finished Sep 04 11:49:54 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854666899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3854666899
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.2386900200
Short name T491
Test name
Test status
Simulation time 15165082160 ps
CPU time 605.81 seconds
Started Sep 04 11:48:37 AM UTC 24
Finished Sep 04 11:58:49 AM UTC 24
Peak memory 700636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386900200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2386900200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_error.4237613804
Short name T415
Test name
Test status
Simulation time 3050557638 ps
CPU time 181 seconds
Started Sep 04 11:48:54 AM UTC 24
Finished Sep 04 11:51:58 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237613804 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.4237613804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_long_msg.1897265980
Short name T381
Test name
Test status
Simulation time 3912136210 ps
CPU time 76.45 seconds
Started Sep 04 11:48:32 AM UTC 24
Finished Sep 04 11:49:51 AM UTC 24
Peak memory 207360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897265980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1897265980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_smoke.3677366691
Short name T364
Test name
Test status
Simulation time 1173096881 ps
CPU time 16.31 seconds
Started Sep 04 11:48:32 AM UTC 24
Finished Sep 04 11:48:50 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677366691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3677366691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_stress_all.1575554030
Short name T530
Test name
Test status
Simulation time 85328739389 ps
CPU time 3386.05 seconds
Started Sep 04 11:48:56 AM UTC 24
Finished Sep 04 12:46:05 PM UTC 24
Peak memory 821428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575554030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1575554030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.2805077408
Short name T383
Test name
Test status
Simulation time 1204256731 ps
CPU time 61.57 seconds
Started Sep 04 11:48:54 AM UTC 24
Finished Sep 04 11:49:58 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805077408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2805077408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_alert_test.473547457
Short name T375
Test name
Test status
Simulation time 41759179 ps
CPU time 0.79 seconds
Started Sep 04 11:49:30 AM UTC 24
Finished Sep 04 11:49:32 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473547457 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.473547457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.3703651465
Short name T401
Test name
Test status
Simulation time 2792346479 ps
CPU time 99.66 seconds
Started Sep 04 11:49:10 AM UTC 24
Finished Sep 04 11:50:52 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703651465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3703651465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2282286180
Short name T378
Test name
Test status
Simulation time 1139823766 ps
CPU time 21.93 seconds
Started Sep 04 11:49:14 AM UTC 24
Finished Sep 04 11:49:37 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282286180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2282286180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.2838269501
Short name T501
Test name
Test status
Simulation time 3569595020 ps
CPU time 765.55 seconds
Started Sep 04 11:49:14 AM UTC 24
Finished Sep 04 12:02:10 PM UTC 24
Peak memory 735696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838269501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2838269501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_error.2780461679
Short name T434
Test name
Test status
Simulation time 3864960454 ps
CPU time 232.13 seconds
Started Sep 04 11:49:14 AM UTC 24
Finished Sep 04 11:53:10 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780461679 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2780461679
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_long_msg.954569365
Short name T406
Test name
Test status
Simulation time 7136829496 ps
CPU time 126.27 seconds
Started Sep 04 11:49:09 AM UTC 24
Finished Sep 04 11:51:18 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954569365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.954569365
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_smoke.317846383
Short name T370
Test name
Test status
Simulation time 1068460917 ps
CPU time 13.08 seconds
Started Sep 04 11:48:56 AM UTC 24
Finished Sep 04 11:49:11 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317846383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.317846383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_stress_all.1030833442
Short name T509
Test name
Test status
Simulation time 31209948164 ps
CPU time 1059.91 seconds
Started Sep 04 11:49:30 AM UTC 24
Finished Sep 04 12:07:24 PM UTC 24
Peak memory 690404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030833442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1030833442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2351949548
Short name T407
Test name
Test status
Simulation time 11251895788 ps
CPU time 106.45 seconds
Started Sep 04 11:49:30 AM UTC 24
Finished Sep 04 11:51:18 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351949548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2351949548
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_alert_test.2440891529
Short name T387
Test name
Test status
Simulation time 12481934 ps
CPU time 0.9 seconds
Started Sep 04 11:49:59 AM UTC 24
Finished Sep 04 11:50:01 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440891529 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2440891529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.2165507148
Short name T390
Test name
Test status
Simulation time 501452345 ps
CPU time 37.88 seconds
Started Sep 04 11:49:36 AM UTC 24
Finished Sep 04 11:50:15 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165507148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2165507148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.1809276032
Short name T160
Test name
Test status
Simulation time 647455879 ps
CPU time 42.73 seconds
Started Sep 04 11:49:39 AM UTC 24
Finished Sep 04 11:50:23 AM UTC 24
Peak memory 207172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809276032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1809276032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.3647171201
Short name T471
Test name
Test status
Simulation time 3890484882 ps
CPU time 407.62 seconds
Started Sep 04 11:49:38 AM UTC 24
Finished Sep 04 11:56:31 AM UTC 24
Peak memory 506280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647171201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3647171201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_error.3044111631
Short name T423
Test name
Test status
Simulation time 27184356890 ps
CPU time 170.15 seconds
Started Sep 04 11:49:44 AM UTC 24
Finished Sep 04 11:52:37 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044111631 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3044111631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_long_msg.3513721977
Short name T404
Test name
Test status
Simulation time 17726344811 ps
CPU time 80.63 seconds
Started Sep 04 11:49:33 AM UTC 24
Finished Sep 04 11:50:55 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513721977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3513721977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_smoke.2878344526
Short name T376
Test name
Test status
Simulation time 809472564 ps
CPU time 4.29 seconds
Started Sep 04 11:49:30 AM UTC 24
Finished Sep 04 11:49:35 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878344526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2878344526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_stress_all.798035065
Short name T533
Test name
Test status
Simulation time 50935689773 ps
CPU time 3691.13 seconds
Started Sep 04 11:49:59 AM UTC 24
Finished Sep 04 12:52:16 PM UTC 24
Peak memory 870644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798035065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.798035065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.3442461894
Short name T397
Test name
Test status
Simulation time 2307396649 ps
CPU time 38.33 seconds
Started Sep 04 11:49:57 AM UTC 24
Finished Sep 04 11:50:36 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442461894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3442461894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_alert_test.966603662
Short name T392
Test name
Test status
Simulation time 13051378 ps
CPU time 0.84 seconds
Started Sep 04 11:50:17 AM UTC 24
Finished Sep 04 11:50:18 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966603662 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.966603662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.3333887151
Short name T400
Test name
Test status
Simulation time 1544818192 ps
CPU time 48.52 seconds
Started Sep 04 11:50:01 AM UTC 24
Finished Sep 04 11:50:51 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333887151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3333887151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.2549710619
Short name T409
Test name
Test status
Simulation time 13458621535 ps
CPU time 83.86 seconds
Started Sep 04 11:50:04 AM UTC 24
Finished Sep 04 11:51:30 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549710619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2549710619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.346941168
Short name T502
Test name
Test status
Simulation time 14936256309 ps
CPU time 760.99 seconds
Started Sep 04 11:50:01 AM UTC 24
Finished Sep 04 12:02:51 PM UTC 24
Peak memory 524512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346941168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.346941168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_error.3053965163
Short name T436
Test name
Test status
Simulation time 25805419333 ps
CPU time 202.06 seconds
Started Sep 04 11:50:07 AM UTC 24
Finished Sep 04 11:53:32 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053965163 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3053965163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_long_msg.847606124
Short name T389
Test name
Test status
Simulation time 1316073971 ps
CPU time 12.51 seconds
Started Sep 04 11:50:01 AM UTC 24
Finished Sep 04 11:50:15 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847606124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.847606124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_smoke.173542928
Short name T388
Test name
Test status
Simulation time 2053214472 ps
CPU time 10.88 seconds
Started Sep 04 11:49:59 AM UTC 24
Finished Sep 04 11:50:11 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173542928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.173542928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_stress_all.1824802114
Short name T508
Test name
Test status
Simulation time 11254356660 ps
CPU time 1004.8 seconds
Started Sep 04 11:50:17 AM UTC 24
Finished Sep 04 12:07:13 PM UTC 24
Peak memory 751848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824802114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1824802114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.1639505645
Short name T394
Test name
Test status
Simulation time 160984314 ps
CPU time 11.69 seconds
Started Sep 04 11:50:11 AM UTC 24
Finished Sep 04 11:50:24 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639505645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1639505645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_alert_test.4073709181
Short name T177
Test name
Test status
Simulation time 11854334 ps
CPU time 0.65 seconds
Started Sep 04 11:36:22 AM UTC 24
Finished Sep 04 11:36:24 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073709181 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4073709181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.2461209221
Short name T156
Test name
Test status
Simulation time 2667882909 ps
CPU time 37.74 seconds
Started Sep 04 11:25:36 AM UTC 24
Finished Sep 04 11:26:16 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461209221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2461209221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.3596721569
Short name T24
Test name
Test status
Simulation time 2344552165 ps
CPU time 61.76 seconds
Started Sep 04 11:26:30 AM UTC 24
Finished Sep 04 11:27:34 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596721569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3596721569
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.191038475
Short name T176
Test name
Test status
Simulation time 9690888996 ps
CPU time 339.63 seconds
Started Sep 04 11:26:17 AM UTC 24
Finished Sep 04 11:32:02 AM UTC 24
Peak memory 475440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191038475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.191038475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_error.4048562728
Short name T174
Test name
Test status
Simulation time 23495855 ps
CPU time 1.21 seconds
Started Sep 04 11:27:34 AM UTC 24
Finished Sep 04 11:27:37 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048562728 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4048562728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_long_msg.1802286889
Short name T155
Test name
Test status
Simulation time 8807974524 ps
CPU time 109.92 seconds
Started Sep 04 11:24:37 AM UTC 24
Finished Sep 04 11:26:29 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802286889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1802286889
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.1732237575
Short name T58
Test name
Test status
Simulation time 191395569 ps
CPU time 1.22 seconds
Started Sep 04 11:36:22 AM UTC 24
Finished Sep 04 11:36:25 AM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732237575 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1732237575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_smoke.2522816505
Short name T96
Test name
Test status
Simulation time 18159681 ps
CPU time 1.06 seconds
Started Sep 04 11:24:34 AM UTC 24
Finished Sep 04 11:24:36 AM UTC 24
Peak memory 206456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522816505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2522816505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_stress_all.3557690756
Short name T524
Test name
Test status
Simulation time 18955745876 ps
CPU time 2589.84 seconds
Started Sep 04 11:36:21 AM UTC 24
Finished Sep 04 12:20:00 PM UTC 24
Peak memory 807036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557690756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3557690756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.1911068197
Short name T205
Test name
Test status
Simulation time 8794798464 ps
CPU time 84.07 seconds
Started Sep 04 11:36:20 AM UTC 24
Finished Sep 04 11:37:46 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911068197 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1911068197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.2455250041
Short name T190
Test name
Test status
Simulation time 3881824107 ps
CPU time 55.52 seconds
Started Sep 04 11:36:21 AM UTC 24
Finished Sep 04 11:37:18 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455250041 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2455250041
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.2233383167
Short name T209
Test name
Test status
Simulation time 19083956372 ps
CPU time 90.48 seconds
Started Sep 04 11:36:21 AM UTC 24
Finished Sep 04 11:37:54 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233383167 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2233383167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.1574844211
Short name T234
Test name
Test status
Simulation time 44889935484 ps
CPU time 631.6 seconds
Started Sep 04 11:28:14 AM UTC 24
Finished Sep 04 11:38:55 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574844211 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1574844211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.4038315900
Short name T506
Test name
Test status
Simulation time 75180360563 ps
CPU time 2222.93 seconds
Started Sep 04 11:29:30 AM UTC 24
Finished Sep 04 12:07:00 PM UTC 24
Peak memory 221380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038315900 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.4038315900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1821092758
Short name T521
Test name
Test status
Simulation time 723214588173 ps
CPU time 2596.34 seconds
Started Sep 04 11:32:03 AM UTC 24
Finished Sep 04 12:15:52 PM UTC 24
Peak memory 221184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821092758 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1821092758
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.686006633
Short name T175
Test name
Test status
Simulation time 10882401160 ps
CPU time 33.97 seconds
Started Sep 04 11:27:38 AM UTC 24
Finished Sep 04 11:28:13 AM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686006633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.686006633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_alert_test.169620568
Short name T402
Test name
Test status
Simulation time 37163799 ps
CPU time 0.88 seconds
Started Sep 04 11:50:50 AM UTC 24
Finished Sep 04 11:50:52 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169620568 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.169620568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.3069129994
Short name T421
Test name
Test status
Simulation time 11300081859 ps
CPU time 118.19 seconds
Started Sep 04 11:50:23 AM UTC 24
Finished Sep 04 11:52:24 AM UTC 24
Peak memory 217800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069129994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3069129994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.3451203097
Short name T398
Test name
Test status
Simulation time 1789500346 ps
CPU time 21.86 seconds
Started Sep 04 11:50:25 AM UTC 24
Finished Sep 04 11:50:49 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451203097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3451203097
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.239402453
Short name T499
Test name
Test status
Simulation time 29530918325 ps
CPU time 639.92 seconds
Started Sep 04 11:50:25 AM UTC 24
Finished Sep 04 12:01:14 PM UTC 24
Peak memory 727312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239402453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.239402453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_error.319576644
Short name T413
Test name
Test status
Simulation time 5968908909 ps
CPU time 87.03 seconds
Started Sep 04 11:50:26 AM UTC 24
Finished Sep 04 11:51:55 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319576644 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.319576644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_long_msg.2905771527
Short name T395
Test name
Test status
Simulation time 397107675 ps
CPU time 4.15 seconds
Started Sep 04 11:50:19 AM UTC 24
Finished Sep 04 11:50:25 AM UTC 24
Peak memory 207124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905771527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2905771527
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_smoke.1428435432
Short name T396
Test name
Test status
Simulation time 1140655350 ps
CPU time 7.33 seconds
Started Sep 04 11:50:19 AM UTC 24
Finished Sep 04 11:50:28 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428435432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1428435432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_stress_all.1459590226
Short name T72
Test name
Test status
Simulation time 96187999451 ps
CPU time 2686.83 seconds
Started Sep 04 11:50:37 AM UTC 24
Finished Sep 04 12:35:59 PM UTC 24
Peak memory 803248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459590226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1459590226
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.947889629
Short name T430
Test name
Test status
Simulation time 9717283618 ps
CPU time 145.41 seconds
Started Sep 04 11:50:29 AM UTC 24
Finished Sep 04 11:52:57 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947889629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.947889629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_alert_test.515082768
Short name T408
Test name
Test status
Simulation time 11651078 ps
CPU time 0.89 seconds
Started Sep 04 11:51:20 AM UTC 24
Finished Sep 04 11:51:22 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515082768 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.515082768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.3189483773
Short name T411
Test name
Test status
Simulation time 3152419690 ps
CPU time 45.08 seconds
Started Sep 04 11:50:52 AM UTC 24
Finished Sep 04 11:51:39 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189483773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3189483773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.2345952120
Short name T416
Test name
Test status
Simulation time 13041544349 ps
CPU time 63.52 seconds
Started Sep 04 11:50:55 AM UTC 24
Finished Sep 04 11:52:00 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345952120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2345952120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.3400744073
Short name T492
Test name
Test status
Simulation time 4898720318 ps
CPU time 475.46 seconds
Started Sep 04 11:50:55 AM UTC 24
Finished Sep 04 11:58:56 AM UTC 24
Peak memory 628964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400744073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3400744073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_error.2797729046
Short name T426
Test name
Test status
Simulation time 1324931859 ps
CPU time 106 seconds
Started Sep 04 11:50:56 AM UTC 24
Finished Sep 04 11:52:44 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797729046 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2797729046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_long_msg.2488726281
Short name T447
Test name
Test status
Simulation time 3235422201 ps
CPU time 196.16 seconds
Started Sep 04 11:50:52 AM UTC 24
Finished Sep 04 11:54:11 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488726281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2488726281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_smoke.4152123683
Short name T405
Test name
Test status
Simulation time 966623008 ps
CPU time 15.38 seconds
Started Sep 04 11:50:52 AM UTC 24
Finished Sep 04 11:51:09 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152123683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4152123683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_stress_all.501547993
Short name T531
Test name
Test status
Simulation time 110700384250 ps
CPU time 3334.24 seconds
Started Sep 04 11:51:20 AM UTC 24
Finished Sep 04 12:47:40 PM UTC 24
Peak memory 801024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501547993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.501547993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.2372564282
Short name T101
Test name
Test status
Simulation time 660679014 ps
CPU time 50.43 seconds
Started Sep 04 11:51:09 AM UTC 24
Finished Sep 04 11:52:02 AM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372564282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2372564282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_alert_test.1542665526
Short name T418
Test name
Test status
Simulation time 14231801 ps
CPU time 0.83 seconds
Started Sep 04 11:52:04 AM UTC 24
Finished Sep 04 11:52:06 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542665526 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1542665526
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.2323796387
Short name T417
Test name
Test status
Simulation time 1398639958 ps
CPU time 25.68 seconds
Started Sep 04 11:51:34 AM UTC 24
Finished Sep 04 11:52:01 AM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323796387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2323796387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.783946732
Short name T161
Test name
Test status
Simulation time 1239860615 ps
CPU time 69.72 seconds
Started Sep 04 11:51:46 AM UTC 24
Finished Sep 04 11:52:57 AM UTC 24
Peak memory 207232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783946732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.783946732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.2619390033
Short name T500
Test name
Test status
Simulation time 3289122999 ps
CPU time 610.02 seconds
Started Sep 04 11:51:41 AM UTC 24
Finished Sep 04 12:01:58 PM UTC 24
Peak memory 712928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619390033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2619390033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_error.191270940
Short name T452
Test name
Test status
Simulation time 13108981082 ps
CPU time 163.87 seconds
Started Sep 04 11:51:56 AM UTC 24
Finished Sep 04 11:54:43 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191270940 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.191270940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_long_msg.1785383808
Short name T444
Test name
Test status
Simulation time 6935445415 ps
CPU time 136.22 seconds
Started Sep 04 11:51:31 AM UTC 24
Finished Sep 04 11:53:50 AM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785383808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1785383808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_smoke.4120417209
Short name T410
Test name
Test status
Simulation time 177698595 ps
CPU time 9.73 seconds
Started Sep 04 11:51:23 AM UTC 24
Finished Sep 04 11:51:34 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120417209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4120417209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_stress_all.3522719386
Short name T71
Test name
Test status
Simulation time 80369553820 ps
CPU time 2508.85 seconds
Started Sep 04 11:52:04 AM UTC 24
Finished Sep 04 12:34:25 PM UTC 24
Peak memory 801200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522719386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3522719386
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.980556578
Short name T425
Test name
Test status
Simulation time 1777949053 ps
CPU time 37.64 seconds
Started Sep 04 11:52:02 AM UTC 24
Finished Sep 04 11:52:41 AM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980556578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.980556578
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_alert_test.4039170498
Short name T424
Test name
Test status
Simulation time 17429492 ps
CPU time 0.83 seconds
Started Sep 04 11:52:39 AM UTC 24
Finished Sep 04 11:52:41 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039170498 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4039170498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.3401861859
Short name T429
Test name
Test status
Simulation time 603246841 ps
CPU time 46.59 seconds
Started Sep 04 11:52:07 AM UTC 24
Finished Sep 04 11:52:55 AM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401861859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3401861859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.694480571
Short name T422
Test name
Test status
Simulation time 710283858 ps
CPU time 18 seconds
Started Sep 04 11:52:18 AM UTC 24
Finished Sep 04 11:52:37 AM UTC 24
Peak memory 207176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694480571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.694480571
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.3802300000
Short name T428
Test name
Test status
Simulation time 358070651 ps
CPU time 42.48 seconds
Started Sep 04 11:52:11 AM UTC 24
Finished Sep 04 11:52:55 AM UTC 24
Peak memory 242144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802300000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3802300000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_error.1988854999
Short name T454
Test name
Test status
Simulation time 7431267271 ps
CPU time 141.14 seconds
Started Sep 04 11:52:27 AM UTC 24
Finished Sep 04 11:54:51 AM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988854999 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1988854999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1190467132
Short name T438
Test name
Test status
Simulation time 18314769442 ps
CPU time 88.52 seconds
Started Sep 04 11:52:05 AM UTC 24
Finished Sep 04 11:53:35 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190467132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1190467132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_smoke.360577184
Short name T419
Test name
Test status
Simulation time 175693705 ps
CPU time 4.22 seconds
Started Sep 04 11:52:05 AM UTC 24
Finished Sep 04 11:52:10 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360577184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.360577184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_stress_all.3311986257
Short name T516
Test name
Test status
Simulation time 22986802958 ps
CPU time 1132.52 seconds
Started Sep 04 11:52:39 AM UTC 24
Finished Sep 04 12:11:47 PM UTC 24
Peak memory 504040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311986257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3311986257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.3198067933
Short name T448
Test name
Test status
Simulation time 29893302541 ps
CPU time 103.11 seconds
Started Sep 04 11:52:27 AM UTC 24
Finished Sep 04 11:54:12 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198067933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3198067933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_alert_test.1298044328
Short name T432
Test name
Test status
Simulation time 11596661 ps
CPU time 0.86 seconds
Started Sep 04 11:53:04 AM UTC 24
Finished Sep 04 11:53:06 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298044328 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1298044328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.2318600843
Short name T446
Test name
Test status
Simulation time 2156212792 ps
CPU time 79.46 seconds
Started Sep 04 11:52:46 AM UTC 24
Finished Sep 04 11:54:07 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318600843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2318600843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.339818811
Short name T439
Test name
Test status
Simulation time 7236522432 ps
CPU time 43.94 seconds
Started Sep 04 11:52:56 AM UTC 24
Finished Sep 04 11:53:42 AM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339818811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.339818811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.3960687241
Short name T464
Test name
Test status
Simulation time 906737772 ps
CPU time 171.41 seconds
Started Sep 04 11:52:52 AM UTC 24
Finished Sep 04 11:55:46 AM UTC 24
Peak memory 680360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960687241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3960687241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_error.3671959572
Short name T456
Test name
Test status
Simulation time 26769012843 ps
CPU time 128.04 seconds
Started Sep 04 11:52:56 AM UTC 24
Finished Sep 04 11:55:07 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671959572 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3671959572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_long_msg.2027095551
Short name T431
Test name
Test status
Simulation time 2548385661 ps
CPU time 19.18 seconds
Started Sep 04 11:52:42 AM UTC 24
Finished Sep 04 11:53:02 AM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027095551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2027095551
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_smoke.1392105197
Short name T427
Test name
Test status
Simulation time 298686581 ps
CPU time 7.98 seconds
Started Sep 04 11:52:42 AM UTC 24
Finished Sep 04 11:52:51 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392105197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1392105197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_stress_all.226430623
Short name T532
Test name
Test status
Simulation time 33036158386 ps
CPU time 3491.38 seconds
Started Sep 04 11:52:59 AM UTC 24
Finished Sep 04 12:51:58 PM UTC 24
Peak memory 839912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226430623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.226430623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.2402459706
Short name T459
Test name
Test status
Simulation time 9087107994 ps
CPU time 134.13 seconds
Started Sep 04 11:52:59 AM UTC 24
Finished Sep 04 11:55:16 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402459706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2402459706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_alert_test.233824608
Short name T442
Test name
Test status
Simulation time 13319208 ps
CPU time 0.84 seconds
Started Sep 04 11:53:45 AM UTC 24
Finished Sep 04 11:53:47 AM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233824608 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.233824608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.2875947363
Short name T453
Test name
Test status
Simulation time 4770674792 ps
CPU time 89.33 seconds
Started Sep 04 11:53:12 AM UTC 24
Finished Sep 04 11:54:43 AM UTC 24
Peak memory 223636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875947363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2875947363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.2064005040
Short name T440
Test name
Test status
Simulation time 475670215 ps
CPU time 8.48 seconds
Started Sep 04 11:53:34 AM UTC 24
Finished Sep 04 11:53:44 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064005040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2064005040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.27302865
Short name T522
Test name
Test status
Simulation time 27173352736 ps
CPU time 1353.7 seconds
Started Sep 04 11:53:27 AM UTC 24
Finished Sep 04 12:16:18 PM UTC 24
Peak memory 774372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27302865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.27302865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_error.294905334
Short name T480
Test name
Test status
Simulation time 19278967366 ps
CPU time 209.13 seconds
Started Sep 04 11:53:37 AM UTC 24
Finished Sep 04 11:57:09 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294905334 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.294905334
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_long_msg.891233359
Short name T474
Test name
Test status
Simulation time 42283961681 ps
CPU time 213.72 seconds
Started Sep 04 11:53:12 AM UTC 24
Finished Sep 04 11:56:49 AM UTC 24
Peak memory 215596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891233359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.891233359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_smoke.3464113221
Short name T433
Test name
Test status
Simulation time 85760270 ps
CPU time 1.84 seconds
Started Sep 04 11:53:07 AM UTC 24
Finished Sep 04 11:53:10 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464113221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3464113221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_stress_all.3969823048
Short name T526
Test name
Test status
Simulation time 15205544556 ps
CPU time 2024.83 seconds
Started Sep 04 11:53:43 AM UTC 24
Finished Sep 04 12:27:54 PM UTC 24
Peak memory 735672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969823048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3969823048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.1069319499
Short name T455
Test name
Test status
Simulation time 7477087628 ps
CPU time 87.07 seconds
Started Sep 04 11:53:37 AM UTC 24
Finished Sep 04 11:55:06 AM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069319499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1069319499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_alert_test.21751079
Short name T450
Test name
Test status
Simulation time 43301086 ps
CPU time 0.87 seconds
Started Sep 04 11:54:22 AM UTC 24
Finished Sep 04 11:54:24 AM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21751079 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.21751079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.3603011875
Short name T445
Test name
Test status
Simulation time 743917542 ps
CPU time 13.19 seconds
Started Sep 04 11:53:51 AM UTC 24
Finished Sep 04 11:54:05 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603011875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3603011875
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.3692282178
Short name T449
Test name
Test status
Simulation time 936466206 ps
CPU time 13.71 seconds
Started Sep 04 11:54:06 AM UTC 24
Finished Sep 04 11:54:21 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692282178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3692282178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.3781910486
Short name T518
Test name
Test status
Simulation time 10881460207 ps
CPU time 1122.75 seconds
Started Sep 04 11:53:51 AM UTC 24
Finished Sep 04 12:12:49 PM UTC 24
Peak memory 711148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781910486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3781910486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_error.327716194
Short name T493
Test name
Test status
Simulation time 68915464692 ps
CPU time 289.99 seconds
Started Sep 04 11:54:09 AM UTC 24
Finished Sep 04 11:59:06 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327716194 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.327716194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_long_msg.3808759597
Short name T485
Test name
Test status
Simulation time 24314698695 ps
CPU time 239.28 seconds
Started Sep 04 11:53:47 AM UTC 24
Finished Sep 04 11:57:50 AM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808759597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3808759597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_smoke.3289845192
Short name T443
Test name
Test status
Simulation time 22776656 ps
CPU time 1.49 seconds
Started Sep 04 11:53:47 AM UTC 24
Finished Sep 04 11:53:50 AM UTC 24
Peak memory 206536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289845192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3289845192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_stress_all.4020039913
Short name T27
Test name
Test status
Simulation time 57501187507 ps
CPU time 3619.41 seconds
Started Sep 04 11:54:14 AM UTC 24
Finished Sep 04 12:55:19 PM UTC 24
Peak memory 852276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020039913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4020039913
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.2293627032
Short name T469
Test name
Test status
Simulation time 2515865428 ps
CPU time 128.05 seconds
Started Sep 04 11:54:14 AM UTC 24
Finished Sep 04 11:56:24 AM UTC 24
Peak memory 207484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293627032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2293627032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_alert_test.2315401819
Short name T458
Test name
Test status
Simulation time 17001756 ps
CPU time 0.9 seconds
Started Sep 04 11:55:14 AM UTC 24
Finished Sep 04 11:55:16 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315401819 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2315401819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.3480728841
Short name T29
Test name
Test status
Simulation time 15734271941 ps
CPU time 109.98 seconds
Started Sep 04 11:54:45 AM UTC 24
Finished Sep 04 11:56:37 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480728841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3480728841
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.3674880977
Short name T463
Test name
Test status
Simulation time 10484654681 ps
CPU time 51.56 seconds
Started Sep 04 11:54:52 AM UTC 24
Finished Sep 04 11:55:45 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674880977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3674880977
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.3507350017
Short name T523
Test name
Test status
Simulation time 6763682401 ps
CPU time 1466.58 seconds
Started Sep 04 11:54:45 AM UTC 24
Finished Sep 04 12:19:30 PM UTC 24
Peak memory 796952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507350017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3507350017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_error.1625285018
Short name T481
Test name
Test status
Simulation time 91816135993 ps
CPU time 120.7 seconds
Started Sep 04 11:55:09 AM UTC 24
Finished Sep 04 11:57:12 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625285018 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1625285018
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_long_msg.2575476714
Short name T487
Test name
Test status
Simulation time 15056909570 ps
CPU time 225.28 seconds
Started Sep 04 11:54:33 AM UTC 24
Finished Sep 04 11:58:22 AM UTC 24
Peak memory 215756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575476714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2575476714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_smoke.2691314189
Short name T451
Test name
Test status
Simulation time 467551891 ps
CPU time 6.04 seconds
Started Sep 04 11:54:25 AM UTC 24
Finished Sep 04 11:54:32 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691314189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2691314189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2751340281
Short name T462
Test name
Test status
Simulation time 1566744191 ps
CPU time 28.22 seconds
Started Sep 04 11:55:09 AM UTC 24
Finished Sep 04 11:55:39 AM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751340281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2751340281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.629249068
Short name T475
Test name
Test status
Simulation time 25921331251 ps
CPU time 98.22 seconds
Started Sep 04 11:55:09 AM UTC 24
Finished Sep 04 11:56:49 AM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629249068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.629249068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_alert_test.3460977065
Short name T467
Test name
Test status
Simulation time 17070676 ps
CPU time 0.78 seconds
Started Sep 04 11:56:13 AM UTC 24
Finished Sep 04 11:56:15 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460977065 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3460977065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.2954166047
Short name T470
Test name
Test status
Simulation time 7473301436 ps
CPU time 61.26 seconds
Started Sep 04 11:55:27 AM UTC 24
Finished Sep 04 11:56:30 AM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954166047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2954166047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.1794712600
Short name T498
Test name
Test status
Simulation time 8235756161 ps
CPU time 336.24 seconds
Started Sep 04 11:55:32 AM UTC 24
Finished Sep 04 12:01:13 PM UTC 24
Peak memory 725540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794712600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1794712600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_error.2761770751
Short name T495
Test name
Test status
Simulation time 5955285701 ps
CPU time 214.17 seconds
Started Sep 04 11:55:46 AM UTC 24
Finished Sep 04 11:59:24 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761770751 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2761770751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_long_msg.2130010673
Short name T488
Test name
Test status
Simulation time 44264966353 ps
CPU time 184.6 seconds
Started Sep 04 11:55:17 AM UTC 24
Finished Sep 04 11:58:25 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130010673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2130010673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_smoke.3131428938
Short name T461
Test name
Test status
Simulation time 383438203 ps
CPU time 12.84 seconds
Started Sep 04 11:55:17 AM UTC 24
Finished Sep 04 11:55:31 AM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131428938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3131428938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_stress_all.1843755065
Short name T511
Test name
Test status
Simulation time 40574530839 ps
CPU time 714.9 seconds
Started Sep 04 11:56:01 AM UTC 24
Finished Sep 04 12:08:06 PM UTC 24
Peak memory 688332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843755065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1843755065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.3501946743
Short name T465
Test name
Test status
Simulation time 1434302758 ps
CPU time 11.13 seconds
Started Sep 04 11:55:48 AM UTC 24
Finished Sep 04 11:56:00 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501946743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3501946743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_alert_test.418055906
Short name T476
Test name
Test status
Simulation time 15102517 ps
CPU time 0.87 seconds
Started Sep 04 11:56:52 AM UTC 24
Finished Sep 04 11:56:54 AM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418055906 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.418055906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.735951093
Short name T482
Test name
Test status
Simulation time 2982020876 ps
CPU time 61.81 seconds
Started Sep 04 11:56:25 AM UTC 24
Finished Sep 04 11:57:29 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735951093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.735951093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.458819535
Short name T479
Test name
Test status
Simulation time 6062318263 ps
CPU time 29.37 seconds
Started Sep 04 11:56:34 AM UTC 24
Finished Sep 04 11:57:05 AM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458819535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.458819535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.1913396907
Short name T514
Test name
Test status
Simulation time 3574545863 ps
CPU time 715.37 seconds
Started Sep 04 11:56:32 AM UTC 24
Finished Sep 04 12:08:37 PM UTC 24
Peak memory 747948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913396907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1913396907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_error.270027008
Short name T484
Test name
Test status
Simulation time 23598445500 ps
CPU time 72.23 seconds
Started Sep 04 11:56:35 AM UTC 24
Finished Sep 04 11:57:49 AM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270027008 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.270027008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_long_msg.3556774542
Short name T472
Test name
Test status
Simulation time 606951850 ps
CPU time 11.27 seconds
Started Sep 04 11:56:21 AM UTC 24
Finished Sep 04 11:56:34 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556774542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3556774542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_smoke.2360519213
Short name T468
Test name
Test status
Simulation time 234359789 ps
CPU time 3.15 seconds
Started Sep 04 11:56:16 AM UTC 24
Finished Sep 04 11:56:21 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360519213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2360519213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1482120393
Short name T490
Test name
Test status
Simulation time 24370251336 ps
CPU time 110.5 seconds
Started Sep 04 11:56:45 AM UTC 24
Finished Sep 04 11:58:38 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482120393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1482120393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.1802368055
Short name T478
Test name
Test status
Simulation time 262227608 ps
CPU time 21.26 seconds
Started Sep 04 11:56:39 AM UTC 24
Finished Sep 04 11:57:02 AM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802368055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1802368055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_alert_test.1654171144
Short name T178
Test name
Test status
Simulation time 13673465 ps
CPU time 0.81 seconds
Started Sep 04 11:36:26 AM UTC 24
Finished Sep 04 11:36:28 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654171144 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1654171144
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.1595837286
Short name T180
Test name
Test status
Simulation time 3994088338 ps
CPU time 24.07 seconds
Started Sep 04 11:36:22 AM UTC 24
Finished Sep 04 11:36:48 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595837286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1595837286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3603052500
Short name T185
Test name
Test status
Simulation time 6665359430 ps
CPU time 35.12 seconds
Started Sep 04 11:36:24 AM UTC 24
Finished Sep 04 11:37:00 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603052500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3603052500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.1824157982
Short name T311
Test name
Test status
Simulation time 3358566200 ps
CPU time 534.45 seconds
Started Sep 04 11:36:24 AM UTC 24
Finished Sep 04 11:45:24 AM UTC 24
Peak memory 747868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824157982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1824157982
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_error.1245812771
Short name T189
Test name
Test status
Simulation time 2738939061 ps
CPU time 47.59 seconds
Started Sep 04 11:36:24 AM UTC 24
Finished Sep 04 11:37:13 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245812771 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1245812771
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_long_msg.2884864127
Short name T230
Test name
Test status
Simulation time 76665038670 ps
CPU time 139.86 seconds
Started Sep 04 11:36:22 AM UTC 24
Finished Sep 04 11:38:45 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884864127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2884864127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_smoke.495756996
Short name T130
Test name
Test status
Simulation time 1011125758 ps
CPU time 17.35 seconds
Started Sep 04 11:36:22 AM UTC 24
Finished Sep 04 11:36:41 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495756996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.495756996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_stress_all.179291394
Short name T528
Test name
Test status
Simulation time 24858176346 ps
CPU time 3222.83 seconds
Started Sep 04 11:36:25 AM UTC 24
Finished Sep 04 12:30:50 PM UTC 24
Peak memory 837808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179291394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.179291394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.2177674680
Short name T9
Test name
Test status
Simulation time 4257819777 ps
CPU time 46.93 seconds
Started Sep 04 11:36:25 AM UTC 24
Finished Sep 04 11:37:13 AM UTC 24
Peak memory 215892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21776746
80 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2177674680
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.3402067217
Short name T97
Test name
Test status
Simulation time 32325277166 ps
CPU time 134.85 seconds
Started Sep 04 11:36:25 AM UTC 24
Finished Sep 04 11:38:42 AM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402067217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3402067217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_alert_test.3616079570
Short name T179
Test name
Test status
Simulation time 55205939 ps
CPU time 0.73 seconds
Started Sep 04 11:36:38 AM UTC 24
Finished Sep 04 11:36:40 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616079570 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3616079570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.766593968
Short name T157
Test name
Test status
Simulation time 1889699274 ps
CPU time 60.63 seconds
Started Sep 04 11:36:29 AM UTC 24
Finished Sep 04 11:37:32 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766593968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.766593968
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.2894358394
Short name T186
Test name
Test status
Simulation time 1722682462 ps
CPU time 29.65 seconds
Started Sep 04 11:36:33 AM UTC 24
Finished Sep 04 11:37:05 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894358394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2894358394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1729103345
Short name T371
Test name
Test status
Simulation time 6966769580 ps
CPU time 750.94 seconds
Started Sep 04 11:36:31 AM UTC 24
Finished Sep 04 11:49:11 AM UTC 24
Peak memory 665884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729103345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1729103345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_error.4130603028
Short name T204
Test name
Test status
Simulation time 13329245034 ps
CPU time 66.76 seconds
Started Sep 04 11:36:34 AM UTC 24
Finished Sep 04 11:37:43 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130603028 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4130603028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_long_msg.1938174282
Short name T199
Test name
Test status
Simulation time 1150921514 ps
CPU time 64.92 seconds
Started Sep 04 11:36:26 AM UTC 24
Finished Sep 04 11:37:33 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938174282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1938174282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_smoke.696957478
Short name T147
Test name
Test status
Simulation time 587875456 ps
CPU time 3.08 seconds
Started Sep 04 11:36:26 AM UTC 24
Finished Sep 04 11:36:30 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696957478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.696957478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_stress_all.1671339993
Short name T414
Test name
Test status
Simulation time 47687129228 ps
CPU time 909.73 seconds
Started Sep 04 11:36:36 AM UTC 24
Finished Sep 04 11:51:57 AM UTC 24
Peak memory 426200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671339993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1671339993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.1680762266
Short name T125
Test name
Test status
Simulation time 1340192550 ps
CPU time 84.59 seconds
Started Sep 04 11:36:36 AM UTC 24
Finished Sep 04 11:38:03 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680762266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1680762266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_alert_test.231672347
Short name T181
Test name
Test status
Simulation time 97607655 ps
CPU time 0.77 seconds
Started Sep 04 11:36:52 AM UTC 24
Finished Sep 04 11:36:54 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231672347 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.231672347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.4090470471
Short name T195
Test name
Test status
Simulation time 8967985023 ps
CPU time 37.35 seconds
Started Sep 04 11:36:49 AM UTC 24
Finished Sep 04 11:37:28 AM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090470471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4090470471
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.2544536862
Short name T46
Test name
Test status
Simulation time 1046646360 ps
CPU time 55.44 seconds
Started Sep 04 11:36:50 AM UTC 24
Finished Sep 04 11:37:47 AM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544536862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2544536862
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.2427030348
Short name T386
Test name
Test status
Simulation time 19279942382 ps
CPU time 782.66 seconds
Started Sep 04 11:36:50 AM UTC 24
Finished Sep 04 11:50:00 AM UTC 24
Peak memory 774420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427030348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2427030348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_error.3758348136
Short name T196
Test name
Test status
Simulation time 5901005795 ps
CPU time 36.53 seconds
Started Sep 04 11:36:51 AM UTC 24
Finished Sep 04 11:37:29 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758348136 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3758348136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2867991740
Short name T248
Test name
Test status
Simulation time 10792288018 ps
CPU time 187.75 seconds
Started Sep 04 11:36:42 AM UTC 24
Finished Sep 04 11:39:52 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867991740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2867991740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_smoke.1090199763
Short name T169
Test name
Test status
Simulation time 667588746 ps
CPU time 9.83 seconds
Started Sep 04 11:36:40 AM UTC 24
Finished Sep 04 11:36:51 AM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090199763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1090199763
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_stress_all.905625940
Short name T351
Test name
Test status
Simulation time 47270176114 ps
CPU time 637.03 seconds
Started Sep 04 11:36:51 AM UTC 24
Finished Sep 04 11:47:37 AM UTC 24
Peak memory 700728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905625940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.905625940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3549776599
Short name T207
Test name
Test status
Simulation time 9531706584 ps
CPU time 57.82 seconds
Started Sep 04 11:36:51 AM UTC 24
Finished Sep 04 11:37:51 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549776599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3549776599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_alert_test.3494620691
Short name T182
Test name
Test status
Simulation time 27326197 ps
CPU time 0.81 seconds
Started Sep 04 11:36:55 AM UTC 24
Finished Sep 04 11:36:56 AM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494620691 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3494620691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.4175973231
Short name T192
Test name
Test status
Simulation time 11304481588 ps
CPU time 30.46 seconds
Started Sep 04 11:36:52 AM UTC 24
Finished Sep 04 11:37:24 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175973231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4175973231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.3732008085
Short name T166
Test name
Test status
Simulation time 1645887749 ps
CPU time 13.39 seconds
Started Sep 04 11:36:52 AM UTC 24
Finished Sep 04 11:37:07 AM UTC 24
Peak memory 215892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732008085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3732008085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_error.2876856857
Short name T145
Test name
Test status
Simulation time 2417932618 ps
CPU time 34.63 seconds
Started Sep 04 11:36:54 AM UTC 24
Finished Sep 04 11:37:29 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876856857 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2876856857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_long_msg.908406197
Short name T220
Test name
Test status
Simulation time 1435731888 ps
CPU time 81.14 seconds
Started Sep 04 11:36:52 AM UTC 24
Finished Sep 04 11:38:15 AM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908406197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.908406197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_smoke.2893754917
Short name T153
Test name
Test status
Simulation time 94808420 ps
CPU time 4.24 seconds
Started Sep 04 11:36:52 AM UTC 24
Finished Sep 04 11:36:58 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893754917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2893754917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_stress_all.496918689
Short name T420
Test name
Test status
Simulation time 290600195748 ps
CPU time 916.18 seconds
Started Sep 04 11:36:54 AM UTC 24
Finished Sep 04 11:52:21 AM UTC 24
Peak memory 471588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496918689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.496918689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.1168913314
Short name T63
Test name
Test status
Simulation time 26467006869 ps
CPU time 415.36 seconds
Started Sep 04 11:36:54 AM UTC 24
Finished Sep 04 11:43:54 AM UTC 24
Peak memory 272672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11689133
14 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1168913314
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.3161338466
Short name T124
Test name
Test status
Simulation time 13068018681 ps
CPU time 41.29 seconds
Started Sep 04 11:36:54 AM UTC 24
Finished Sep 04 11:37:36 AM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161338466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3161338466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_alert_test.381388681
Short name T183
Test name
Test status
Simulation time 134583105 ps
CPU time 0.79 seconds
Started Sep 04 11:36:57 AM UTC 24
Finished Sep 04 11:36:59 AM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381388681 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.381388681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.603212801
Short name T202
Test name
Test status
Simulation time 2444754255 ps
CPU time 41.96 seconds
Started Sep 04 11:36:55 AM UTC 24
Finished Sep 04 11:37:38 AM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603212801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.603212801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1729775778
Short name T221
Test name
Test status
Simulation time 34160849852 ps
CPU time 78.72 seconds
Started Sep 04 11:36:56 AM UTC 24
Finished Sep 04 11:38:16 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729775778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1729775778
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.70151608
Short name T82
Test name
Test status
Simulation time 2479104069 ps
CPU time 384.46 seconds
Started Sep 04 11:36:56 AM UTC 24
Finished Sep 04 11:43:25 AM UTC 24
Peak memory 518348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70151608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.70151608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_error.1558175793
Short name T210
Test name
Test status
Simulation time 3354747834 ps
CPU time 58.1 seconds
Started Sep 04 11:36:56 AM UTC 24
Finished Sep 04 11:37:56 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558175793 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1558175793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_long_msg.1992998710
Short name T246
Test name
Test status
Simulation time 12038894482 ps
CPU time 166.73 seconds
Started Sep 04 11:36:55 AM UTC 24
Finished Sep 04 11:39:44 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992998710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1992998710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_smoke.3194861061
Short name T149
Test name
Test status
Simulation time 131398975 ps
CPU time 5.83 seconds
Started Sep 04 11:36:55 AM UTC 24
Finished Sep 04 11:37:02 AM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194861061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3194861061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_stress_all.887262746
Short name T527
Test name
Test status
Simulation time 76365516548 ps
CPU time 3116.3 seconds
Started Sep 04 11:36:57 AM UTC 24
Finished Sep 04 12:29:29 PM UTC 24
Peak memory 767976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887262746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.887262746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1535756605
Short name T197
Test name
Test status
Simulation time 2614247476 ps
CPU time 33.41 seconds
Started Sep 04 11:36:56 AM UTC 24
Finished Sep 04 11:37:31 AM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535756605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1535756605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/hmac-sim-vcs/9.hmac_wipe_secret/latest
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