Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15392469	1			T1	635		T2	5973		T4	622
all_values[1]	15392469	1			T1	635		T2	5973		T4	622
all_values[2]	15392469	1			T1	635		T2	5973		T4	622

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250477

1

T1

106

T2

1358

T15

89

auto[1]

45926930

1

T1

1799

T2

16561

T4

1866

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39415423

1

T1

1631

T2

16320

T4

1718

auto[1]

6761984

1

T1

274

T2

1599

T4

148

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84108	1			T1	106		T2	677		T15	87
all_values[0]	auto[0]	auto[1]	333	1			T2	2		T15	2		T11	2
all_values[0]	auto[1]	auto[0]	15290085	1			T1	523		T2	5275		T4	605
all_values[0]	auto[1]	auto[1]	17943	1			T1	6		T2	19		T4	17
all_values[1]	auto[0]	auto[0]	80009	1			T143	1241		T52	2		T54	25
all_values[1]	auto[0]	auto[1]	180	1			T69	4		T74	1		T142	2
all_values[1]	auto[1]	auto[0]	15311996	1			T1	635		T2	5973		T4	622
all_values[1]	auto[1]	auto[1]	284	1			T22	1		T43	3		T69	4
all_values[2]	auto[0]	auto[0]	40197	1			T2	679		T7	6		T29	69
all_values[2]	auto[0]	auto[1]	45650	1			T7	36		T29	271		T16	398
all_values[2]	auto[1]	auto[0]	8609028	1			T1	367		T2	3716		T4	491
all_values[2]	auto[1]	auto[1]	6697594	1			T1	268		T2	1578		T4	131