Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109568

1

T1

6

T2

38

T4

238

auto[1]

97968

1

T1

8

T2

10

T4

80

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	78420	1			T2	20		T4	137		T5	1
len_1026_2046	4906	1			T1	1		T2	2		T4	8
len_514_1022	3974	1			T4	3		T5	3		T9	1
len_2_510	3276	1			T2	1		T4	2		T5	3
len_2056	148	1			T1	3		T5	2		T15	1
len_2048	287	1			T5	9		T9	2		T15	3
len_2040	154	1			T5	1		T9	3		T15	3
len_1032	119	1			T5	3		T9	1		T15	1
len_1024	1776	1			T1	1		T2	1		T4	1
len_1016	140	1			T5	1		T15	6		T6	3
len_520	139	1			T5	1		T9	3		T15	4
len_512	287	1			T1	1		T5	3		T9	2
len_504	174	1			T5	2		T9	4		T15	1
len_8	758	1			T158	3		T20	2		T159	3
len_0	9210	1			T1	1		T4	8		T5	6

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

108

1

T136

1

T22

2

T43

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	41946	1			T2	16		T4	109		T31	3
auto[0]	len_1026_2046	2910	1			T1	1		T2	1		T4	5
auto[0]	len_514_1022	2469	1			T4	2		T5	2		T31	2
auto[0]	len_2_510	2142	1			T2	1		T4	2		T5	1
auto[0]	len_2056	78	1			T1	1		T5	2		T47	1
auto[0]	len_2048	182	1			T5	4		T15	2		T14	1
auto[0]	len_2040	88	1			T9	1		T13	1		T47	1
auto[0]	len_1032	66	1			T5	3		T15	1		T6	3
auto[0]	len_1024	212	1			T2	1		T4	1		T5	1
auto[0]	len_1016	78	1			T5	1		T15	2		T13	2
auto[0]	len_520	84	1			T5	1		T9	1		T15	3
auto[0]	len_512	162	1			T1	1		T5	3		T9	2
auto[0]	len_504	117	1			T5	2		T9	2		T15	1
auto[0]	len_8	18	1			T158	2		T160	2		T161	1
auto[0]	len_0	4232	1			T5	3		T9	6		T15	2
auto[1]	len_2050_plus	36474	1			T2	4		T4	28		T5	1
auto[1]	len_1026_2046	1996	1			T2	1		T4	3		T32	1
auto[1]	len_514_1022	1505	1			T4	1		T5	1		T9	1
auto[1]	len_2_510	1134	1			T5	2		T9	1		T6	1
auto[1]	len_2056	70	1			T1	2		T15	1		T136	2
auto[1]	len_2048	105	1			T5	5		T9	2		T15	1
auto[1]	len_2040	66	1			T5	1		T9	2		T15	3
auto[1]	len_1032	53	1			T9	1		T13	2		T47	1
auto[1]	len_1024	1564	1			T1	1		T5	2		T6	3
auto[1]	len_1016	62	1			T15	4		T6	3		T13	2
auto[1]	len_520	55	1			T9	2		T15	1		T7	1
auto[1]	len_512	125	1			T15	1		T7	4		T13	1
auto[1]	len_504	57	1			T9	2		T6	1		T47	1
auto[1]	len_8	740	1			T158	1		T20	2		T159	3
auto[1]	len_0	4978	1			T1	1		T4	8		T5	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

61

1

T136

1

T22

1

T43

1

auto[1]

len_upper

47

1

T22

1

T17

1

T162

1