Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3900963 1 T1 180 T2 10 T4 253
auto[1] 2129559 1 T1 152 T2 9 T4 504


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2109684 1 T1 255 T2 9 T4 377
auto[1] 3920838 1 T1 77 T2 10 T4 380


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2932472 1 T1 207 T2 14 T4 525
auto[1] 3098050 1 T1 125 T2 5 T4 232


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3874010 1 T1 111 T2 10 T4 239
auto[1] 2156512 1 T1 221 T2 9 T4 518


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 5454403 1 T1 331 T2 12 T4 604
fifo_depth[1] 97354 1 T1 1 T4 15 T5 11
fifo_depth[2] 72786 1 T2 2 T4 33 T5 8
fifo_depth[3] 58423 1 T4 5 T5 2 T9 2
fifo_depth[4] 53629 1 T2 1 T4 38 T5 3
fifo_depth[5] 42456 1 T2 1 T4 5 T32 28
fifo_depth[6] 34011 1 T2 1 T4 22 T32 16
fifo_depth[7] 22807 1 T4 3 T32 8 T6 1


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 576119 1 T1 1 T2 7 T4 153
auto[1] 5454403 1 T1 331 T2 12 T4 604


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6018663 1 T1 332 T2 19 T4 757
auto[1] 11859 1 T11 164 T29 19 T43 363


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 26105 1 T2 1 T4 11 T8 1
auto[0] auto[0] auto[0] auto[0] auto[1] 29745 1 T14 10 T16 1 T34 79
auto[0] auto[0] auto[0] auto[1] auto[0] 22088 1 T15 3 T14 46 T34 172
auto[0] auto[0] auto[0] auto[1] auto[1] 32704 1 T2 1 T4 43 T5 3
auto[0] auto[0] auto[1] auto[0] auto[0] 116624 1 T2 1 T14 54 T12 1
auto[0] auto[0] auto[1] auto[0] auto[1] 25522 1 T9 2 T15 2 T31 8
auto[0] auto[0] auto[1] auto[1] auto[0] 20172 1 T5 2 T6 3 T14 17
auto[0] auto[0] auto[1] auto[1] auto[1] 22645 1 T2 2 T4 78 T8 1
auto[0] auto[1] auto[0] auto[0] auto[0] 32382 1 T4 5 T9 3 T6 8
auto[0] auto[1] auto[0] auto[0] auto[1] 39679 1 T2 1 T4 14 T5 1
auto[0] auto[1] auto[0] auto[1] auto[0] 33845 1 T1 1 T5 1 T9 2
auto[0] auto[1] auto[0] auto[1] auto[1] 33411 1 T5 2 T9 1 T32 69
auto[0] auto[1] auto[1] auto[0] auto[0] 42583 1 T5 6 T32 150 T7 7
auto[0] auto[1] auto[1] auto[0] auto[1] 33907 1 T2 1 T31 22 T10 1
auto[0] auto[1] auto[1] auto[1] auto[0] 34994 1 T4 2 T5 2 T15 1
auto[0] auto[1] auto[1] auto[1] auto[1] 29713 1 T5 7 T9 6 T15 2
auto[1] auto[0] auto[0] auto[0] auto[0] 142041 1 T1 19 T2 2 T4 26
auto[1] auto[0] auto[0] auto[0] auto[1] 138296 1 T1 52 T9 44 T31 424
auto[1] auto[0] auto[0] auto[1] auto[0] 122015 1 T1 13 T2 1 T4 47
auto[1] auto[0] auto[0] auto[1] auto[1] 129533 1 T1 60 T2 1 T4 122
auto[1] auto[0] auto[1] auto[0] auto[0] 1707835 1 T2 1 T5 46 T15 28
auto[1] auto[0] auto[1] auto[0] auto[1] 135702 1 T1 43 T9 54 T15 118
auto[1] auto[0] auto[1] auto[1] auto[0] 136060 1 T1 20 T2 3 T5 112
auto[1] auto[0] auto[1] auto[1] auto[1] 125385 1 T2 1 T4 198 T5 46
auto[1] auto[1] auto[0] auto[0] auto[0] 322388 1 T4 81 T5 1 T9 113
auto[1] auto[1] auto[0] auto[0] auto[1] 350225 1 T1 65 T2 2 T4 28
auto[1] auto[1] auto[0] auto[1] auto[0] 327704 1 T1 45 T5 52 T9 29
auto[1] auto[1] auto[0] auto[1] auto[1] 327523 1 T5 30 T9 150 T32 281
auto[1] auto[1] auto[1] auto[0] auto[0] 407616 1 T2 1 T4 53 T5 94
auto[1] auto[1] auto[1] auto[0] auto[1] 350313 1 T1 1 T4 35 T9 59
auto[1] auto[1] auto[1] auto[1] auto[0] 379558 1 T1 13 T4 14 T5 76
auto[1] auto[1] auto[1] auto[1] auto[1] 352209 1 T5 117 T9 88 T15 58


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 167821 1 T1 19 T2 3 T4 37
auto[0] auto[0] auto[0] auto[0] auto[1] 166915 1 T1 52 T9 44 T31 424
auto[0] auto[0] auto[0] auto[1] auto[0] 141384 1 T1 13 T2 1 T4 47
auto[0] auto[0] auto[0] auto[1] auto[1] 161573 1 T1 60 T2 2 T4 165
auto[0] auto[0] auto[1] auto[0] auto[0] 1822219 1 T2 2 T5 46 T15 28
auto[0] auto[0] auto[1] auto[0] auto[1] 160524 1 T1 43 T9 56 T15 120
auto[0] auto[0] auto[1] auto[1] auto[0] 155988 1 T1 20 T2 3 T5 114
auto[0] auto[0] auto[1] auto[1] auto[1] 146942 1 T2 3 T4 276 T5 46
auto[0] auto[1] auto[0] auto[0] auto[0] 354257 1 T4 86 T5 1 T9 116
auto[0] auto[1] auto[0] auto[0] auto[1] 389679 1 T1 65 T2 3 T4 42
auto[0] auto[1] auto[0] auto[1] auto[0] 361485 1 T1 46 T5 53 T9 31
auto[0] auto[1] auto[0] auto[1] auto[1] 360482 1 T5 32 T9 151 T32 350
auto[0] auto[1] auto[1] auto[0] auto[0] 450032 1 T2 1 T4 53 T5 100
auto[0] auto[1] auto[1] auto[0] auto[1] 383552 1 T1 1 T2 1 T4 35
auto[0] auto[1] auto[1] auto[1] auto[0] 414057 1 T1 13 T4 16 T5 78
auto[0] auto[1] auto[1] auto[1] auto[1] 381753 1 T5 124 T9 94 T15 60
auto[1] auto[0] auto[0] auto[0] auto[0] 325 1 T29 1 T167 4 T168 4
auto[1] auto[0] auto[0] auto[0] auto[1] 1126 1 T43 52 T169 266 T19 6
auto[1] auto[0] auto[0] auto[1] auto[0] 2719 1 T169 1 T75 1 T170 498
auto[1] auto[0] auto[0] auto[1] auto[1] 664 1 T29 6 T43 51 T169 251
auto[1] auto[0] auto[1] auto[0] auto[0] 2240 1 T43 187 T171 1164 T172 32
auto[1] auto[0] auto[1] auto[0] auto[1] 700 1 T43 63 T19 11 T167 3
auto[1] auto[0] auto[1] auto[1] auto[0] 244 1 T19 4 T75 92 T170 5
auto[1] auto[0] auto[1] auto[1] auto[1] 1088 1 T43 9 T167 17 T173 35
auto[1] auto[1] auto[0] auto[0] auto[0] 513 1 T29 7 T19 8 T173 5
auto[1] auto[1] auto[0] auto[0] auto[1] 225 1 T75 4 T174 22 T175 4
auto[1] auto[1] auto[0] auto[1] auto[0] 64 1 T29 5 T173 19 T75 9
auto[1] auto[1] auto[0] auto[1] auto[1] 452 1 T11 164 T169 60 T167 3
auto[1] auto[1] auto[1] auto[0] auto[0] 167 1 T167 10 T173 1 T175 122
auto[1] auto[1] auto[1] auto[0] auto[1] 668 1 T168 12 T176 7 T177 20
auto[1] auto[1] auto[1] auto[1] auto[0] 495 1 T75 303 T178 1 T179 43
auto[1] auto[1] auto[1] auto[1] auto[1] 169 1 T43 1 T19 7 T75 14


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 142041 1 T1 19 T2 2 T4 26
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 138296 1 T1 52 T9 44 T31 424
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 122015 1 T1 13 T2 1 T4 47
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 129533 1 T1 60 T2 1 T4 122
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1707835 1 T2 1 T5 46 T15 28
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 135702 1 T1 43 T9 54 T15 118
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 136060 1 T1 20 T2 3 T5 112
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 125385 1 T2 1 T4 198 T5 46
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 322388 1 T4 81 T5 1 T9 113
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 350225 1 T1 65 T2 2 T4 28
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 327704 1 T1 45 T5 52 T9 29
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 327523 1 T5 30 T9 150 T32 281
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 407616 1 T2 1 T4 53 T5 94
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 350313 1 T1 1 T4 35 T9 59
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 379558 1 T1 13 T4 14 T5 76
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 352209 1 T5 117 T9 88 T15 58
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3031 1 T14 11 T33 3 T108 17
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3070 1 T34 10 T108 23 T136 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 2475 1 T15 2 T14 1 T34 24
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 2578 1 T4 9 T5 1 T6 1
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 36406 1 T14 13 T108 9 T41 3
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 2863 1 T9 1 T15 1 T31 6
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 2586 1 T5 2 T14 1 T13 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 2809 1 T4 5 T13 2 T34 19
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 4361 1 T9 1 T6 1 T7 2
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5564 1 T4 1 T5 1 T9 4
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5296 1 T1 1 T9 1 T15 2
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 4713 1 T9 1 T32 6 T11 2
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 7324 1 T5 2 T32 29 T7 3
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 4987 1 T31 17 T7 2 T33 13
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 4925 1 T15 1 T33 9 T164 25
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 4366 1 T5 5 T9 4 T15 2
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2511 1 T4 4 T29 6 T14 7
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2459 1 T14 2 T34 10 T108 16
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2003 1 T15 1 T14 16 T34 31
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2316 1 T2 1 T4 8 T5 2
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 20896 1 T14 9 T108 8 T41 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2268 1 T9 1 T15 1 T31 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2107 1 T14 5 T41 5 T43 3
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2480 1 T2 1 T4 14 T8 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 3740 1 T4 2 T9 1 T6 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5014 1 T4 5 T14 2 T33 2
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4574 1 T9 1 T6 2 T7 2
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4126 1 T5 2 T32 16 T11 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6044 1 T5 2 T32 27 T61 200
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4457 1 T31 5 T33 2 T108 7
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4028 1 T33 1 T17 1 T47 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 3763 1 T5 2 T9 1 T13 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2001 1 T14 7 T108 18 T22 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1933 1 T34 8 T108 24 T52 25
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1569 1 T14 1 T34 23 T108 5
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1675 1 T4 3 T6 1 T29 4
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 14635 1 T14 13 T108 8 T41 3
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1924 1 T33 2 T108 19 T43 77
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1621 1 T41 6 T43 3 T47 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1973 1 T13 1 T34 27 T43 6
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3332 1 T9 1 T7 1 T14 4
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4637 1 T4 2 T7 2 T143 48
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4033 1 T15 1 T6 1 T7 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3453 1 T32 11 T11 1 T7 2
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5009 1 T5 1 T32 31 T7 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3975 1 T33 1 T108 14 T136 4
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3495 1 T5 1 T164 2 T180 10
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3158 1 T9 1 T13 2 T136 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2057 1 T4 5 T29 5 T14 5
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1935 1 T14 5 T34 12 T108 22
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1580 1 T14 14 T34 25 T108 2
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1909 1 T4 9 T6 1 T29 5
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 10452 1 T14 9 T12 1 T108 6
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2110 1 T6 1 T108 18 T41 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1773 1 T6 2 T14 9 T41 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 1780 1 T4 19 T14 2 T34 17
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 3148 1 T7 1 T29 7 T14 7
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4387 1 T4 3 T14 4 T143 41
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3758 1 T5 1 T15 1 T7 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3296 1 T32 14 T11 12 T16 1
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5090 1 T5 1 T32 27 T7 2
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3735 1 T2 1 T108 12 T136 4
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3473 1 T4 2 T5 1 T165 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3146 1 T136 2 T43 96 T55 51
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1590 1 T29 20 T14 4 T108 13
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1516 1 T34 13 T108 18 T52 22
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1133 1 T34 23 T108 4 T43 2
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1479 1 T4 3 T6 1 T8 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 7265 1 T14 6 T108 3 T41 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1434 1 T108 21 T43 76 T180 6
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1198 1 T6 1 T14 1 T41 4
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1458 1 T2 1 T4 2 T34 20
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2721 1 T6 2 T7 1 T29 2
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3768 1 T7 2 T14 1 T143 30
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3108 1 T7 1 T108 17 T52 5
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 2837 1 T32 10 T11 8 T7 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4043 1 T32 18 T7 1 T61 103
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3153 1 T7 1 T16 1 T108 16
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 2891 1 T22 1 T180 7 T19 11
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2862 1 T13 1 T136 1 T43 95
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1335 1 T4 2 T29 4 T14 4
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1160 1 T34 12 T108 18 T136 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 938 1 T14 5 T34 14 T108 8
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1284 1 T4 6 T29 4 T55 5
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 4986 1 T2 1 T14 2 T16 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1218 1 T108 14 T41 2 T43 10
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 987 1 T41 1 T43 1 T52 7
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1068 1 T4 13 T12 1 T16 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2364 1 T6 2 T7 1 T29 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3091 1 T4 1 T14 2 T143 21
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2605 1 T108 16 T52 5 T55 44
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2252 1 T32 6 T11 41 T7 2
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3506 1 T32 10 T61 65 T56 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2622 1 T7 2 T108 12 T136 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2379 1 T180 4 T19 15 T162 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2216 1 T136 1 T43 55 T55 42
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 966 1 T29 19 T108 2 T43 9
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 817 1 T34 10 T108 10 T23 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 583 1 T34 15 T108 5 T43 3
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 883 1 T4 1 T29 5 T43 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 3309 1 T14 1 T108 2 T41 2
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 712 1 T108 6 T41 1 T43 72
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 593 1 T14 1 T41 1 T43 2
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 679 1 T4 2 T34 4 T43 13
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1728 1 T7 4 T14 4 T34 7
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2077 1 T143 6 T52 2 T137 5
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1750 1 T6 1 T7 1 T108 11
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1460 1 T32 4 T11 37 T7 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2177 1 T32 4 T61 17 T135 97
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1768 1 T7 1 T108 8 T41 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1655 1 T180 6 T19 7 T181 9
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1650 1 T43 90 T55 34 T182 8

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