Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15392469	1			T1	635		T2	5973		T4	622
all_pins[1]	15392469	1			T1	635		T2	5973		T4	622
all_pins[2]	15392469	1			T1	635		T2	5973		T4	622

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	39460782	1			T1	1631		T2	16316		T4	1718
values[0x1]	6716625	1			T1	274		T2	1603		T4	148
transitions[0x0=>0x1]	6716459	1			T1	274		T2	1603		T4	148
transitions[0x1=>0x0]	6716475	1			T1	274		T2	1603		T4	148

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15373747	1			T1	629		T2	5948		T4	605
all_pins[0]	values[0x1]	18722	1			T1	6		T2	25		T4	17
all_pins[0]	transitions[0x0=>0x1]	18645	1			T1	6		T2	25		T4	17
all_pins[0]	transitions[0x1=>0x0]	6697533	1			T1	268		T2	1578		T4	131
all_pins[1]	values[0x0]	15392160	1			T1	635		T2	5973		T4	622
all_pins[1]	values[0x1]	309	1			T11	1		T29	1		T22	1
all_pins[1]	transitions[0x0=>0x1]	263	1			T11	1		T29	1		T22	1
all_pins[1]	transitions[0x1=>0x0]	18676	1			T1	6		T2	25		T4	17
all_pins[2]	values[0x0]	8694875	1			T1	367		T2	4395		T4	491
all_pins[2]	values[0x1]	6697594	1			T1	268		T2	1578		T4	131
all_pins[2]	transitions[0x0=>0x1]	6697551	1			T1	268		T2	1578		T4	131
all_pins[2]	transitions[0x1=>0x0]	266	1			T11	1		T29	1		T22	1