Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 850 1 T69 14 T74 7 T75 4
all_values[1] 850 1 T69 14 T74 7 T75 4
all_values[2] 850 1 T69 14 T74 7 T75 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1269 1 T69 16 T74 6 T75 4
auto[1] 1281 1 T69 26 T74 15 T75 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 898 1 T69 15 T74 7 T75 9
auto[1] 1652 1 T69 27 T74 14 T75 3


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1456 1 T69 24 T74 11 T75 10
auto[1] 1094 1 T69 18 T74 10 T75 2


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 160 1 T69 1 T75 2 T144 2
all_values[0] auto[0] auto[0] auto[1] 81 1 T74 1 T142 2 T144 1
all_values[0] auto[0] auto[1] auto[0] 165 1 T69 8 T74 3 T75 1
all_values[0] auto[0] auto[1] auto[1] 86 1 T74 1 T142 2 T145 3
all_values[0] auto[1] auto[0] auto[1] 173 1 T69 1 T74 1 T75 1
all_values[0] auto[1] auto[1] auto[1] 185 1 T69 4 T74 1 T142 1
all_values[1] auto[0] auto[0] auto[0] 134 1 T69 1 T75 1 T144 1
all_values[1] auto[0] auto[0] auto[1] 105 1 T69 1 T144 2 T145 4
all_values[1] auto[0] auto[1] auto[0] 119 1 T74 1 T75 3 T142 1
all_values[1] auto[0] auto[1] auto[1] 109 1 T69 4 T74 1 T142 2
all_values[1] auto[1] auto[0] auto[1] 191 1 T69 5 T74 2 T142 4
all_values[1] auto[1] auto[1] auto[1] 192 1 T69 3 T74 3 T144 3
all_values[2] auto[0] auto[0] auto[0] 159 1 T69 3 T74 1 T142 2
all_values[2] auto[0] auto[0] auto[1] 94 1 T69 1 T144 1 T146 1
all_values[2] auto[0] auto[1] auto[0] 161 1 T69 2 T74 2 T75 2
all_values[2] auto[0] auto[1] auto[1] 83 1 T69 3 T74 1 T75 1
all_values[2] auto[1] auto[0] auto[1] 172 1 T69 3 T74 1 T144 2
all_values[2] auto[1] auto[1] auto[1] 181 1 T69 2 T74 2 T75 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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