Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3553	1			T1	6		T2	1		T4	2
sha2_none	3592	1			T2	4		T4	2		T5	5
sha2_512	6893	1			T1	4		T2	9		T4	5
sha2_384	6719	1			T1	1		T2	3		T4	6
sha2_256	5477	1			T1	2		T2	5		T4	4

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17012

1

T1

6

T2

11

T4

7

auto[1]

9543

1

T1

8

T2

11

T4

12

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9542

1

T1

10

T2

10

T4

9

auto[1]

17013

1

T1

4

T2

12

T4

10

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

13364

1

T1

6

T2

5

T4

8

disabled

13191

1

T1

8

T2

17

T4

11

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	3873	1			T1	8		T2	1		T4	8
key_none	7369	1			T1	1		T2	3		T4	1
key_1024	3926	1			T1	1		T2	2		T4	1
key_512	3231	1			T1	2		T2	2		T4	4
key_384	3048	1			T2	6		T5	3		T9	5
key_256	2560	1			T1	1		T2	4		T4	1
key_128	2484	1			T1	1		T2	4		T4	4

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17044

1

T1

6

T2

12

T4

7

auto[1]

9511

1

T1

8

T2

10

T4

12

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

26404

1

T1

14

T2

22

T4

19

disabled

151

1

T58

1

T59

2

T60

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1303

1

T4

2

T5

1

T9

3

enabled

auto[0]

auto[0]

auto[1]

1353

1

T1

2

T2

3

T4

1

enabled

auto[0]

auto[1]

auto[0]

1324

1

T1

2

T5

2

T9

2

enabled

auto[0]

auto[1]

auto[1]

1291

1

T5

3

T9

5

T32

1

enabled

auto[1]

auto[0]

auto[0]

4013

1

T2

1

T4

1

T5

6

enabled

auto[1]

auto[0]

auto[1]

1397

1

T1

1

T2

1

T4

2

enabled

auto[1]

auto[1]

auto[0]

1354

1

T1

1

T4

1

T5

3

enabled

auto[1]

auto[1]

auto[1]

1329

1

T4

1

T5

4

T9

3

disabled

auto[0]

auto[0]

auto[0]

1080

1

T1

1

T2

4

T4

1

disabled

auto[0]

auto[0]

auto[1]

1050

1

T1

1

T9

3

T31

1

disabled

auto[0]

auto[1]

auto[0]

1060

1

T1

1

T2

1

T4

1

disabled

auto[0]

auto[1]

auto[1]

1081

1

T1

3

T2

2

T4

4

disabled

auto[1]

auto[0]

auto[0]

5811

1

T2

2

T5

2

T15

2

disabled

auto[1]

auto[0]

auto[1]

1005

1

T1

1

T9

4

T15

4

disabled

auto[1]

auto[1]

auto[0]

1099

1

T1

1

T2

4

T4

1

disabled

auto[1]

auto[1]

auto[1]

1005

1

T2

4

T4

4

T5

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

13309

1

T1

6

T2

5

T4

8

enabled

disabled

55

1

T59

1

T156

1

T157

2

disabled

disabled

96

1

T58

1

T59

1

T60

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13095

1

T1

8

T2

17

T4

11

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	931	1			T1	3		T4	2		T5	3
key_invalid	sha2_none	711	1			T4	1		T15	1		T6	1
key_invalid	sha2_512	730	1			T1	2		T2	1		T4	2
key_invalid	sha2_384	744	1			T1	1		T4	1		T5	1
key_invalid	sha2_256	671	1			T1	1		T4	2		T5	2
key_none	sha2_invalid	469	1			T1	1		T5	1		T6	3
key_none	sha2_none	447	1			T2	1		T5	2		T32	1
key_none	sha2_512	2415	1			T4	1		T31	1		T6	1
key_none	sha2_384	2484	1			T5	1		T9	2		T15	1
key_none	sha2_256	1507	1			T2	2		T5	3		T9	1
key_1024	sha2_invalid	419	1			T15	1		T10	1		T8	2
key_1024	sha2_none	474	1			T4	1		T15	1		T11	1
key_1024	sha2_512	1653	1			T1	1		T2	1		T5	1
key_1024	sha2_384	847	1			T2	1		T5	1		T9	1
key_512	sha2_invalid	399	1			T9	1		T31	1		T7	3
key_512	sha2_none	442	1			T5	2		T10	1		T7	1
key_512	sha2_512	528	1			T1	1		T2	1		T4	1
key_512	sha2_384	1094	1			T4	2		T5	1		T9	1
key_512	sha2_256	731	1			T1	1		T2	1		T4	1
key_384	sha2_invalid	460	1			T9	1		T15	1		T31	1
key_384	sha2_none	533	1			T2	1		T5	1		T9	1
key_384	sha2_512	530	1			T2	2		T5	2		T9	2
key_384	sha2_384	500	1			T2	1		T9	1		T15	1
key_384	sha2_256	989	1			T2	2		T15	1		T6	1
key_256	sha2_invalid	428	1			T1	1		T9	2		T15	1
key_256	sha2_none	479	1			T2	2		T9	1		T6	1
key_256	sha2_512	530	1			T2	2		T5	1		T9	2
key_256	sha2_384	520	1			T4	1		T5	2		T9	1
key_256	sha2_256	568	1			T5	1		T32	1		T11	1
key_128	sha2_invalid	441	1			T1	1		T2	1		T5	2
key_128	sha2_none	494	1			T15	1		T6	1		T7	1
key_128	sha2_512	488	1			T2	2		T4	1		T5	1
key_128	sha2_384	515	1			T2	1		T4	2		T5	1
key_128	sha2_256	509	1			T4	1		T5	3		T9	3

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

491

1

T5

3

T9

2

T15

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	931	1			T1	3		T4	2		T5	3
key_invalid	sha2_none	711	1			T4	1		T15	1		T6	1
key_invalid	sha2_512	730	1			T1	2		T2	1		T4	2
key_invalid	sha2_384	744	1			T1	1		T4	1		T5	1
key_invalid	sha2_256	671	1			T1	1		T4	2		T5	2
key_none	sha2_invalid	469	1			T1	1		T5	1		T6	3
key_none	sha2_none	447	1			T2	1		T5	2		T32	1
key_none	sha2_512	2415	1			T4	1		T31	1		T6	1
key_none	sha2_384	2484	1			T5	1		T9	2		T15	1
key_none	sha2_256	1507	1			T2	2		T5	3		T9	1
key_1024	sha2_invalid	419	1			T15	1		T10	1		T8	2
key_1024	sha2_none	474	1			T4	1		T15	1		T11	1
key_1024	sha2_512	1653	1			T1	1		T2	1		T5	1
key_1024	sha2_384	847	1			T2	1		T5	1		T9	1
key_1024	sha2_256	491	1			T5	3		T9	2		T15	1
key_512	sha2_invalid	399	1			T9	1		T31	1		T7	3
key_512	sha2_none	442	1			T5	2		T10	1		T7	1
key_512	sha2_512	528	1			T1	1		T2	1		T4	1
key_512	sha2_384	1094	1			T4	2		T5	1		T9	1
key_512	sha2_256	731	1			T1	1		T2	1		T4	1
key_384	sha2_invalid	460	1			T9	1		T15	1		T31	1
key_384	sha2_none	533	1			T2	1		T5	1		T9	1
key_384	sha2_512	530	1			T2	2		T5	2		T9	2
key_384	sha2_384	500	1			T2	1		T9	1		T15	1
key_384	sha2_256	989	1			T2	2		T15	1		T6	1
key_256	sha2_invalid	428	1			T1	1		T9	2		T15	1
key_256	sha2_none	479	1			T2	2		T9	1		T6	1
key_256	sha2_512	530	1			T2	2		T5	1		T9	2
key_256	sha2_384	520	1			T4	1		T5	2		T9	1
key_256	sha2_256	568	1			T5	1		T32	1		T11	1
key_128	sha2_invalid	441	1			T1	1		T2	1		T5	2
key_128	sha2_none	494	1			T15	1		T6	1		T7	1
key_128	sha2_512	488	1			T2	2		T4	1		T5	1
key_128	sha2_384	515	1			T2	1		T4	2		T5	1
key_128	sha2_256	509	1			T4	1		T5	3		T9	3