Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 95.40 97.17 100.00 94.12 98.27 98.48 99.85


Total test records in report: 642
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T117 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2490454147 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:18 PM UTC 24 1063697362 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.1293117621 Sep 11 01:11:16 PM UTC 24 Sep 11 01:11:19 PM UTC 24 78345238 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.3302791625 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:19 PM UTC 24 1610183490 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2816507575 Sep 11 01:11:16 PM UTC 24 Sep 11 01:11:19 PM UTC 24 31761573 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3656026745 Sep 11 01:11:05 PM UTC 24 Sep 11 01:11:19 PM UTC 24 20523372 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3434513182 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:20 PM UTC 24 14753655 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1931574854 Sep 11 01:11:05 PM UTC 24 Sep 11 01:11:20 PM UTC 24 144777184 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4131184819 Sep 11 01:11:05 PM UTC 24 Sep 11 01:11:20 PM UTC 24 221026355 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1651764709 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:20 PM UTC 24 164069023 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1858845035 Sep 11 01:11:18 PM UTC 24 Sep 11 01:11:20 PM UTC 24 240792854 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1891583710 Sep 11 01:11:05 PM UTC 24 Sep 11 01:11:20 PM UTC 24 26674765 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3015900983 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:20 PM UTC 24 25651230 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1143602218 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:35 PM UTC 24 216890027 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1793899887 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:20 PM UTC 24 17983438 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2223649384 Sep 11 01:11:18 PM UTC 24 Sep 11 01:11:20 PM UTC 24 219653540 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1022512280 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:21 PM UTC 24 149746689 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.2727335029 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:21 PM UTC 24 146701100 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.482106668 Sep 11 01:11:19 PM UTC 24 Sep 11 01:11:21 PM UTC 24 167975462 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2027487121 Sep 11 01:11:20 PM UTC 24 Sep 11 01:11:21 PM UTC 24 13922424 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1654732546 Sep 11 01:11:09 PM UTC 24 Sep 11 01:11:22 PM UTC 24 90976650 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1191055055 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:22 PM UTC 24 42570086 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.257668841 Sep 11 01:11:06 PM UTC 24 Sep 11 01:11:22 PM UTC 24 138909550 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.4284027139 Sep 11 01:11:20 PM UTC 24 Sep 11 01:11:22 PM UTC 24 95668216 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2941981907 Sep 11 01:11:06 PM UTC 24 Sep 11 01:11:22 PM UTC 24 29289502 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1975889988 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:22 PM UTC 24 43866331 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4170657161 Sep 11 01:11:20 PM UTC 24 Sep 11 01:11:22 PM UTC 24 292549759 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.3440165546 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:23 PM UTC 24 41386460 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.416584305 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:23 PM UTC 24 382767245 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.3513983456 Sep 11 01:11:06 PM UTC 24 Sep 11 01:11:23 PM UTC 24 618710807 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3595518428 Sep 11 01:11:20 PM UTC 24 Sep 11 01:11:23 PM UTC 24 297418116 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.1356358169 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:23 PM UTC 24 57621803 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.275747073 Sep 11 01:11:19 PM UTC 24 Sep 11 01:11:23 PM UTC 24 751873984 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1522190630 Sep 11 01:11:13 PM UTC 24 Sep 11 01:11:23 PM UTC 24 86807679 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.3768208811 Sep 11 01:11:05 PM UTC 24 Sep 11 01:11:23 PM UTC 24 1106052335 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.2567485458 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:23 PM UTC 24 3387827597 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3656236217 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:24 PM UTC 24 309854698 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3902918125 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:24 PM UTC 24 73513478 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.902859651 Sep 11 01:11:12 PM UTC 24 Sep 11 01:11:24 PM UTC 24 647516408 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1260959461 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:24 PM UTC 24 29569085 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.4058324137 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:24 PM UTC 24 42069774 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.2891313335 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:24 PM UTC 24 37547726 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3853073330 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:24 PM UTC 24 92883702 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.392494235 Sep 11 01:11:37 PM UTC 24 Sep 11 01:11:39 PM UTC 24 48266751 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.3655390872 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:24 PM UTC 24 37876534 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3232643992 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:24 PM UTC 24 401556828 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3778068340 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:25 PM UTC 24 72111096 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.880624674 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:25 PM UTC 24 75990301 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.3644872751 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:25 PM UTC 24 57452452 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.235015444 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:25 PM UTC 24 145717346 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.3747782754 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:25 PM UTC 24 137096608 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2797835546 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:25 PM UTC 24 140683566 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2414363152 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:25 PM UTC 24 103071120 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2162699641 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:25 PM UTC 24 546907815 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3923439080 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:25 PM UTC 24 26291877 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.754566975 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:26 PM UTC 24 327785405 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1273312133 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:26 PM UTC 24 269881851 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.300315167 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:26 PM UTC 24 166237942 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1293727273 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:26 PM UTC 24 53460900 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.4061322919 Sep 11 01:10:56 PM UTC 24 Sep 11 01:11:27 PM UTC 24 363334198 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1011859997 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:27 PM UTC 24 302126711 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.2901873765 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:27 PM UTC 24 7341216013 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3042096658 Sep 11 01:11:21 PM UTC 24 Sep 11 01:11:27 PM UTC 24 1458742831 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1477512613 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:27 PM UTC 24 816382864 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.3544038185 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:28 PM UTC 24 759177794 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3060022625 Sep 11 01:11:23 PM UTC 24 Sep 11 01:11:28 PM UTC 24 1127173496 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3241002133 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:29 PM UTC 24 18311205 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2560347224 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:29 PM UTC 24 25536849 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.728225949 Sep 11 01:11:01 PM UTC 24 Sep 11 01:11:30 PM UTC 24 4383437019 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2219330081 Sep 11 01:11:06 PM UTC 24 Sep 11 01:11:31 PM UTC 24 8779534628 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.79202680 Sep 11 01:11:25 PM UTC 24 Sep 11 01:11:32 PM UTC 24 194802715 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1200148871 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:34 PM UTC 24 13119980 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2990521730 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:35 PM UTC 24 22920235 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2340147663 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:35 PM UTC 24 33918069 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1697711581 Sep 11 01:11:30 PM UTC 24 Sep 11 01:11:35 PM UTC 24 53048264 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1349704208 Sep 11 01:11:30 PM UTC 24 Sep 11 01:11:35 PM UTC 24 56209265 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3731541673 Sep 11 01:11:29 PM UTC 24 Sep 11 01:11:35 PM UTC 24 167833673 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3970322776 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:36 PM UTC 24 574421106 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2726289879 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:36 PM UTC 24 1166485876 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1030064373 Sep 11 01:11:26 PM UTC 24 Sep 11 01:11:37 PM UTC 24 756760588 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3172199663 Sep 11 01:11:37 PM UTC 24 Sep 11 01:11:39 PM UTC 24 71286044 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2978990473 Sep 11 01:11:36 PM UTC 24 Sep 11 01:11:39 PM UTC 24 12647280 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.501206709 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:39 PM UTC 24 19725350 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.203707499 Sep 11 01:11:27 PM UTC 24 Sep 11 01:11:39 PM UTC 24 17696660 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1788430353 Sep 11 01:11:27 PM UTC 24 Sep 11 01:11:39 PM UTC 24 54790510 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.877625195 Sep 11 01:11:37 PM UTC 24 Sep 11 01:11:39 PM UTC 24 14095191 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.162801841 Sep 11 01:11:37 PM UTC 24 Sep 11 01:11:39 PM UTC 24 50220756 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.2572910287 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:39 PM UTC 24 25237735 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2839271138 Sep 11 01:11:38 PM UTC 24 Sep 11 01:11:39 PM UTC 24 32132086 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1013852657 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:40 PM UTC 24 39304593 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.477816894 Sep 11 01:11:25 PM UTC 24 Sep 11 01:11:40 PM UTC 24 38285895 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2553994417 Sep 11 01:11:27 PM UTC 24 Sep 11 01:11:40 PM UTC 24 48631681 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1187462527 Sep 11 01:11:25 PM UTC 24 Sep 11 01:11:40 PM UTC 24 105621091 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2777984129 Sep 11 01:11:28 PM UTC 24 Sep 11 01:11:40 PM UTC 24 118378066 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2302401978 Sep 11 01:11:25 PM UTC 24 Sep 11 01:11:41 PM UTC 24 78822547 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.100521279 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:41 PM UTC 24 161740222 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.319489854 Sep 11 01:11:28 PM UTC 24 Sep 11 01:11:41 PM UTC 24 200949114 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.768994977 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:41 PM UTC 24 632250266 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1231525753 Sep 11 01:11:27 PM UTC 24 Sep 11 01:11:41 PM UTC 24 44069099 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.2835200694 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:41 PM UTC 24 177531244 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.2970913930 Sep 11 01:11:28 PM UTC 24 Sep 11 01:11:42 PM UTC 24 116206416 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3887343174 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:42 PM UTC 24 231030945 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.3734894923 Sep 11 01:11:27 PM UTC 24 Sep 11 01:11:42 PM UTC 24 572341849 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3357693541 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:42 PM UTC 24 1303483890 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1278678116 Sep 11 01:11:24 PM UTC 24 Sep 11 01:11:43 PM UTC 24 962251362 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1270084557 Sep 11 01:11:42 PM UTC 24 Sep 11 01:11:44 PM UTC 24 36558107 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3017427901 Sep 11 01:11:42 PM UTC 24 Sep 11 01:11:44 PM UTC 24 19379261 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.941287403 Sep 11 01:11:35 PM UTC 24 Sep 11 01:11:44 PM UTC 24 18109254 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.792540043 Sep 11 01:11:35 PM UTC 24 Sep 11 01:11:44 PM UTC 24 63920839 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2637062582 Sep 11 01:11:35 PM UTC 24 Sep 11 01:11:44 PM UTC 24 60529112 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.1325172838 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:44 PM UTC 24 49234464 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.494685246 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:44 PM UTC 24 12044862 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3937548253 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:44 PM UTC 24 12090495 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.4089861973 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:44 PM UTC 24 16044060 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.889743564 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:45 PM UTC 24 179214127 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2453363043 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:45 PM UTC 24 16739918 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1218150326 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:45 PM UTC 24 41432647 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.3741132703 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:45 PM UTC 24 19175544 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.638126369 Sep 11 01:11:40 PM UTC 24 Sep 11 01:11:45 PM UTC 24 15959244 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1055966408 Sep 11 01:11:35 PM UTC 24 Sep 11 01:11:45 PM UTC 24 290116123 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.3399908155 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 48858775 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2715680789 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 74718645 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.2296277636 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 56278012 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3491806918 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 84717748 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3943629854 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 26216970 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.176053923 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 14630579 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.872681784 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 26211566 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.3889029368 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 45902045 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1009162433 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 14904182 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.374674345 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 19276430 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3064434886 Sep 11 01:11:41 PM UTC 24 Sep 11 01:11:50 PM UTC 24 15152535 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.1866345156 Sep 11 01:11:29 PM UTC 24 Sep 11 01:11:53 PM UTC 24 76162168 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.198341866 Sep 11 01:11:29 PM UTC 24 Sep 11 01:11:54 PM UTC 24 18637034 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.1002095663 Sep 11 01:11:29 PM UTC 24 Sep 11 01:11:54 PM UTC 24 72370644 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2125201203 Sep 11 01:11:29 PM UTC 24 Sep 11 01:11:55 PM UTC 24 76953985 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.825206413 Sep 11 01:11:29 PM UTC 24 Sep 11 01:11:55 PM UTC 24 722582375 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.699174334 Sep 11 01:11:10 PM UTC 24 Sep 11 01:13:43 PM UTC 24 60947241365 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1549990062 Sep 11 01:11:26 PM UTC 24 Sep 11 01:13:43 PM UTC 24 69447406994 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1436542177 Sep 11 01:11:26 PM UTC 24 Sep 11 01:14:06 PM UTC 24 87318128145 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1294654249 Sep 11 01:11:25 PM UTC 24 Sep 11 01:20:30 PM UTC 24 226233760006 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4186451784 Sep 11 01:11:31 PM UTC 24 Sep 11 01:21:55 PM UTC 24 141432151024 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3354037723 Sep 11 01:11:35 PM UTC 24 Sep 11 01:24:39 PM UTC 24 86721738606 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1359334660 Sep 11 01:11:24 PM UTC 24 Sep 11 01:27:05 PM UTC 24 107671452352 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_smoke.1119846471
Short name T5
Test name
Test status
Simulation time 2974353703 ps
CPU time 10.96 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:31:08 PM UTC 24
Peak memory 207288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119846471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1119846471
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_smoke.1860476507
Short name T7
Test name
Test status
Simulation time 697143277 ps
CPU time 10.82 seconds
Started Sep 11 01:31:16 PM UTC 24
Finished Sep 11 01:31:28 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860476507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1860476507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.3221643730
Short name T19
Test name
Test status
Simulation time 2737861501 ps
CPU time 141.4 seconds
Started Sep 11 01:32:41 PM UTC 24
Finished Sep 11 01:35:05 PM UTC 24
Peak memory 215036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32216437
30 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3221643730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.2729436092
Short name T108
Test name
Test status
Simulation time 3381299353 ps
CPU time 75.07 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:32:13 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729436092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2729436092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_stress_all.3455243014
Short name T90
Test name
Test status
Simulation time 42770302348 ps
CPU time 572.19 seconds
Started Sep 11 01:36:55 PM UTC 24
Finished Sep 11 01:46:34 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455243014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3455243014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.1948418425
Short name T43
Test name
Test status
Simulation time 4824103212 ps
CPU time 85.78 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:32:23 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948418425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1948418425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.3768208811
Short name T148
Test name
Test status
Simulation time 1106052335 ps
CPU time 4.25 seconds
Started Sep 11 01:11:05 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 207660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768208811 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3768208811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.2354616417
Short name T3
Test name
Test status
Simulation time 201678358 ps
CPU time 0.8 seconds
Started Sep 11 01:30:53 PM UTC 24
Finished Sep 11 01:30:55 PM UTC 24
Peak memory 235556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354616417 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2354616417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_stress_all.1117931438
Short name T23
Test name
Test status
Simulation time 1311861200 ps
CPU time 81.26 seconds
Started Sep 11 01:31:14 PM UTC 24
Finished Sep 11 01:32:37 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117931438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1117931438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.331949648
Short name T4
Test name
Test status
Simulation time 1666945573 ps
CPU time 14.22 seconds
Started Sep 11 01:30:48 PM UTC 24
Finished Sep 11 01:31:03 PM UTC 24
Peak memory 207172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331949648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.331949648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1793899887
Short name T121
Test name
Test status
Simulation time 17983438 ps
CPU time 0.84 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793899887 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1793899887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_error.1591422391
Short name T58
Test name
Test status
Simulation time 2152446832 ps
CPU time 117.15 seconds
Started Sep 11 01:31:09 PM UTC 24
Finished Sep 11 01:33:08 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591422391 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1591422391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_stress_all.2811944075
Short name T75
Test name
Test status
Simulation time 126160463018 ps
CPU time 421.58 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:38:11 PM UTC 24
Peak memory 218008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811944075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2811944075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_smoke.843862767
Short name T196
Test name
Test status
Simulation time 644942063 ps
CPU time 3.2 seconds
Started Sep 11 01:33:13 PM UTC 24
Finished Sep 11 01:33:18 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843862767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.843862767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_alert_test.385502739
Short name T183
Test name
Test status
Simulation time 35319212 ps
CPU time 0.87 seconds
Started Sep 11 01:31:16 PM UTC 24
Finished Sep 11 01:31:17 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385502739 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.385502739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_long_msg.2400496322
Short name T158
Test name
Test status
Simulation time 10380463482 ps
CPU time 142.09 seconds
Started Sep 11 01:31:16 PM UTC 24
Finished Sep 11 01:33:40 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400496322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2400496322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.1030064373
Short name T153
Test name
Test status
Simulation time 756760588 ps
CPU time 2.85 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:37 PM UTC 24
Peak memory 207852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030064373 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1030064373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_stress_all.4065250591
Short name T512
Test name
Test status
Simulation time 17852370927 ps
CPU time 1348.52 seconds
Started Sep 11 01:42:00 PM UTC 24
Finished Sep 11 02:04:43 PM UTC 24
Peak memory 737504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065250591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4065250591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.1242668038
Short name T22
Test name
Test status
Simulation time 2886984195 ps
CPU time 80.98 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:32:19 PM UTC 24
Peak memory 207300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242668038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1242668038
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.212367473
Short name T61
Test name
Test status
Simulation time 6189858183 ps
CPU time 41.36 seconds
Started Sep 11 01:30:52 PM UTC 24
Finished Sep 11 01:31:35 PM UTC 24
Peak memory 207460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212367473 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.212367473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2553994417
Short name T155
Test name
Test status
Simulation time 48631681 ps
CPU time 1.58 seconds
Started Sep 11 01:11:27 PM UTC 24
Finished Sep 11 01:11:40 PM UTC 24
Peak memory 206600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553994417 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2553994417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_smoke.64942736
Short name T1
Test name
Test status
Simulation time 401946753 ps
CPU time 4.92 seconds
Started Sep 11 01:30:47 PM UTC 24
Finished Sep 11 01:30:53 PM UTC 24
Peak memory 205076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64942736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.hmac_smoke.64942736
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_error.739179274
Short name T240
Test name
Test status
Simulation time 27468728149 ps
CPU time 151.45 seconds
Started Sep 11 01:33:42 PM UTC 24
Finished Sep 11 01:36:16 PM UTC 24
Peak memory 207368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739179274 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.739179274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2890590506
Short name T16
Test name
Test status
Simulation time 5519810731 ps
CPU time 75.24 seconds
Started Sep 11 01:30:48 PM UTC 24
Finished Sep 11 01:32:05 PM UTC 24
Peak memory 207300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890590506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2890590506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.320963396
Short name T67
Test name
Test status
Simulation time 120678818 ps
CPU time 1.73 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:15 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320963396 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.320963396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.4061322919
Short name T563
Test name
Test status
Simulation time 363334198 ps
CPU time 5.35 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:27 PM UTC 24
Peak memory 207552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061322919 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4061322919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.3302791625
Short name T118
Test name
Test status
Simulation time 1610183490 ps
CPU time 14.5 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:19 PM UTC 24
Peak memory 207592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302791625 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3302791625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.1914155878
Short name T114
Test name
Test status
Simulation time 19076861 ps
CPU time 0.75 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:05 PM UTC 24
Peak memory 206544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914155878 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1914155878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1350209711
Short name T63
Test name
Test status
Simulation time 38914029 ps
CPU time 1.13 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:05 PM UTC 24
Peak memory 206660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1350209711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.1350209711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.4111427581
Short name T98
Test name
Test status
Simulation time 30032973 ps
CPU time 0.76 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:05 PM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111427581 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4111427581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.1977110210
Short name T97
Test name
Test status
Simulation time 58767994 ps
CPU time 0.55 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:05 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977110210 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1977110210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3656236217
Short name T133
Test name
Test status
Simulation time 309854698 ps
CPU time 2.3 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 207856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656236217 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.3656236217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.1356358169
Short name T543
Test name
Test status
Simulation time 57621803 ps
CPU time 1.44 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 204748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356358169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1356358169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3317289048
Short name T66
Test name
Test status
Simulation time 1144134236 ps
CPU time 3.94 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:08 PM UTC 24
Peak memory 206068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317289048 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3317289048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.2901873765
Short name T565
Test name
Test status
Simulation time 7341216013 ps
CPU time 7.83 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:27 PM UTC 24
Peak memory 207784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901873765 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2901873765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2409589556
Short name T116
Test name
Test status
Simulation time 1521432418 ps
CPU time 9.57 seconds
Started Sep 11 01:10:59 PM UTC 24
Finished Sep 11 01:11:13 PM UTC 24
Peak memory 207856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409589556 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2409589556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.3440165546
Short name T123
Test name
Test status
Simulation time 41386460 ps
CPU time 0.95 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 206720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440165546 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3440165546
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1022512280
Short name T72
Test name
Test status
Simulation time 149746689 ps
CPU time 1.56 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:21 PM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1022512280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.1022512280
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1216972560
Short name T535
Test name
Test status
Simulation time 35833405 ps
CPU time 0.59 seconds
Started Sep 11 01:10:59 PM UTC 24
Finished Sep 11 01:11:04 PM UTC 24
Peak memory 206456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216972560 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1216972560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1975889988
Short name T541
Test name
Test status
Simulation time 43866331 ps
CPU time 0.55 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975889988 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1975889988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3015900983
Short name T128
Test name
Test status
Simulation time 25651230 ps
CPU time 1.03 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015900983 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.3015900983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.3778068340
Short name T551
Test name
Test status
Simulation time 72111096 ps
CPU time 3.1 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 207792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778068340 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3778068340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3853073330
Short name T154
Test name
Test status
Simulation time 92883702 ps
CPU time 2.51 seconds
Started Sep 11 01:10:56 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 207672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853073330 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3853073330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1359334660
Short name T642
Test name
Test status
Simulation time 107671452352 ps
CPU time 917.42 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:27:05 PM UTC 24
Peak memory 235396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1359334660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.1359334660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.3747782754
Short name T555
Test name
Test status
Simulation time 137096608 ps
CPU time 0.87 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747782754 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3747782754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.880624674
Short name T552
Test name
Test status
Simulation time 75990301 ps
CPU time 0.53 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880624674 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.880624674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.768994977
Short name T597
Test name
Test status
Simulation time 632250266 ps
CPU time 2.3 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:41 PM UTC 24
Peak memory 207920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768994977 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.768994977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.3544038185
Short name T567
Test name
Test status
Simulation time 759177794 ps
CPU time 3.52 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:28 PM UTC 24
Peak memory 207788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544038185 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3544038185
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3060022625
Short name T152
Test name
Test status
Simulation time 1127173496 ps
CPU time 3.88 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:28 PM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060022625 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3060022625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.100521279
Short name T595
Test name
Test status
Simulation time 161740222 ps
CPU time 1.98 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:41 PM UTC 24
Peak memory 206660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=100521279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_r
eset.100521279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2560347224
Short name T569
Test name
Test status
Simulation time 25536849 ps
CPU time 0.76 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:29 PM UTC 24
Peak memory 206660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560347224 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2560347224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.501206709
Short name T583
Test name
Test status
Simulation time 19725350 ps
CPU time 0.61 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501206709 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.501206709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1013852657
Short name T590
Test name
Test status
Simulation time 39304593 ps
CPU time 1.06 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:40 PM UTC 24
Peak memory 206904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013852657 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.1013852657
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3887343174
Short name T601
Test name
Test status
Simulation time 231030945 ps
CPU time 3.41 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:42 PM UTC 24
Peak memory 207712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887343174 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3887343174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.2835200694
Short name T599
Test name
Test status
Simulation time 177531244 ps
CPU time 2.5 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:41 PM UTC 24
Peak memory 207652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835200694 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2835200694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1294654249
Short name T639
Test name
Test status
Simulation time 226233760006 ps
CPU time 525.75 seconds
Started Sep 11 01:11:25 PM UTC 24
Finished Sep 11 01:20:30 PM UTC 24
Peak memory 218088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1294654249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.1294654249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.477816894
Short name T591
Test name
Test status
Simulation time 38285895 ps
CPU time 0.91 seconds
Started Sep 11 01:11:25 PM UTC 24
Finished Sep 11 01:11:40 PM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477816894 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.477816894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.2572910287
Short name T588
Test name
Test status
Simulation time 25237735 ps
CPU time 0.64 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572910287 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2572910287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2302401978
Short name T594
Test name
Test status
Simulation time 78822547 ps
CPU time 1.59 seconds
Started Sep 11 01:11:25 PM UTC 24
Finished Sep 11 01:11:41 PM UTC 24
Peak memory 206780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302401978 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.2302401978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3357693541
Short name T603
Test name
Test status
Simulation time 1303483890 ps
CPU time 3.37 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:42 PM UTC 24
Peak memory 207980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357693541 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3357693541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1278678116
Short name T604
Test name
Test status
Simulation time 962251362 ps
CPU time 4.15 seconds
Started Sep 11 01:11:24 PM UTC 24
Finished Sep 11 01:11:43 PM UTC 24
Peak memory 207912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278678116 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1278678116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1436542177
Short name T638
Test name
Test status
Simulation time 87318128145 ps
CPU time 150.34 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:14:06 PM UTC 24
Peak memory 224408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1436542177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.1436542177
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2340147663
Short name T575
Test name
Test status
Simulation time 33918069 ps
CPU time 0.79 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:35 PM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340147663 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2340147663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1200148871
Short name T573
Test name
Test status
Simulation time 13119980 ps
CPU time 0.52 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:34 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200148871 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1200148871
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2726289879
Short name T580
Test name
Test status
Simulation time 1166485876 ps
CPU time 2.17 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:36 PM UTC 24
Peak memory 207732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726289879 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.2726289879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1187462527
Short name T592
Test name
Test status
Simulation time 105621091 ps
CPU time 1.46 seconds
Started Sep 11 01:11:25 PM UTC 24
Finished Sep 11 01:11:40 PM UTC 24
Peak memory 206600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187462527 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1187462527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.79202680
Short name T572
Test name
Test status
Simulation time 194802715 ps
CPU time 2.79 seconds
Started Sep 11 01:11:25 PM UTC 24
Finished Sep 11 01:11:32 PM UTC 24
Peak memory 207712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79202680 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.79202680
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1549990062
Short name T637
Test name
Test status
Simulation time 69447406994 ps
CPU time 127.85 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:13:43 PM UTC 24
Peak memory 218096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1549990062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.1549990062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2990521730
Short name T574
Test name
Test status
Simulation time 22920235 ps
CPU time 0.56 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:35 PM UTC 24
Peak memory 203512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990521730 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2990521730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3970322776
Short name T579
Test name
Test status
Simulation time 574421106 ps
CPU time 1.47 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:36 PM UTC 24
Peak memory 206804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970322776 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.3970322776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1143602218
Short name T80
Test name
Test status
Simulation time 216890027 ps
CPU time 1.21 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:35 PM UTC 24
Peak memory 206600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143602218 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1143602218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3241002133
Short name T568
Test name
Test status
Simulation time 18311205 ps
CPU time 0.7 seconds
Started Sep 11 01:11:26 PM UTC 24
Finished Sep 11 01:11:29 PM UTC 24
Peak memory 206712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241002133 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3241002133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2777984129
Short name T593
Test name
Test status
Simulation time 118378066 ps
CPU time 1.51 seconds
Started Sep 11 01:11:28 PM UTC 24
Finished Sep 11 01:11:40 PM UTC 24
Peak memory 206660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2777984129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.2777984129
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1788430353
Short name T585
Test name
Test status
Simulation time 54790510 ps
CPU time 0.63 seconds
Started Sep 11 01:11:27 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 206888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788430353 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1788430353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.203707499
Short name T584
Test name
Test status
Simulation time 17696660 ps
CPU time 0.61 seconds
Started Sep 11 01:11:27 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203707499 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.203707499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1231525753
Short name T598
Test name
Test status
Simulation time 44069099 ps
CPU time 1.92 seconds
Started Sep 11 01:11:27 PM UTC 24
Finished Sep 11 01:11:41 PM UTC 24
Peak memory 206544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231525753 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1231525753
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.3734894923
Short name T602
Test name
Test status
Simulation time 572341849 ps
CPU time 3.41 seconds
Started Sep 11 01:11:27 PM UTC 24
Finished Sep 11 01:11:42 PM UTC 24
Peak memory 207696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734894923 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3734894923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3731541673
Short name T578
Test name
Test status
Simulation time 167833673 ps
CPU time 2.28 seconds
Started Sep 11 01:11:29 PM UTC 24
Finished Sep 11 01:11:35 PM UTC 24
Peak memory 217964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3731541673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.3731541673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.198341866
Short name T632
Test name
Test status
Simulation time 18637034 ps
CPU time 0.82 seconds
Started Sep 11 01:11:29 PM UTC 24
Finished Sep 11 01:11:54 PM UTC 24
Peak memory 206536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198341866 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.198341866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.1866345156
Short name T631
Test name
Test status
Simulation time 76162168 ps
CPU time 0.53 seconds
Started Sep 11 01:11:29 PM UTC 24
Finished Sep 11 01:11:53 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866345156 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1866345156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2125201203
Short name T634
Test name
Test status
Simulation time 76953985 ps
CPU time 1.52 seconds
Started Sep 11 01:11:29 PM UTC 24
Finished Sep 11 01:11:55 PM UTC 24
Peak memory 206728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125201203 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.2125201203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.2970913930
Short name T600
Test name
Test status
Simulation time 116206416 ps
CPU time 2.88 seconds
Started Sep 11 01:11:28 PM UTC 24
Finished Sep 11 01:11:42 PM UTC 24
Peak memory 208112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970913930 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2970913930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.319489854
Short name T596
Test name
Test status
Simulation time 200949114 ps
CPU time 1.8 seconds
Started Sep 11 01:11:28 PM UTC 24
Finished Sep 11 01:11:41 PM UTC 24
Peak memory 206672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319489854 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.319489854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4186451784
Short name T640
Test name
Test status
Simulation time 141432151024 ps
CPU time 599.9 seconds
Started Sep 11 01:11:31 PM UTC 24
Finished Sep 11 01:21:55 PM UTC 24
Peak memory 218100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4186451784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.4186451784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1697711581
Short name T576
Test name
Test status
Simulation time 53048264 ps
CPU time 0.61 seconds
Started Sep 11 01:11:30 PM UTC 24
Finished Sep 11 01:11:35 PM UTC 24
Peak memory 206184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697711581 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1697711581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1349704208
Short name T577
Test name
Test status
Simulation time 56209265 ps
CPU time 1.03 seconds
Started Sep 11 01:11:30 PM UTC 24
Finished Sep 11 01:11:35 PM UTC 24
Peak memory 206724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349704208 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.1349704208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.1002095663
Short name T633
Test name
Test status
Simulation time 72370644 ps
CPU time 1.06 seconds
Started Sep 11 01:11:29 PM UTC 24
Finished Sep 11 01:11:54 PM UTC 24
Peak memory 206600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002095663 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1002095663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.825206413
Short name T635
Test name
Test status
Simulation time 722582375 ps
CPU time 1.62 seconds
Started Sep 11 01:11:29 PM UTC 24
Finished Sep 11 01:11:55 PM UTC 24
Peak memory 206600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825206413 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.825206413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3354037723
Short name T641
Test name
Test status
Simulation time 86721738606 ps
CPU time 767.61 seconds
Started Sep 11 01:11:35 PM UTC 24
Finished Sep 11 01:24:39 PM UTC 24
Peak memory 224492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3354037723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.3354037723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2637062582
Short name T609
Test name
Test status
Simulation time 60529112 ps
CPU time 0.62 seconds
Started Sep 11 01:11:35 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 206192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637062582 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2637062582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.941287403
Short name T607
Test name
Test status
Simulation time 18109254 ps
CPU time 0.55 seconds
Started Sep 11 01:11:35 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941287403 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.941287403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1055966408
Short name T619
Test name
Test status
Simulation time 290116123 ps
CPU time 1.49 seconds
Started Sep 11 01:11:35 PM UTC 24
Finished Sep 11 01:11:45 PM UTC 24
Peak memory 206796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055966408 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.1055966408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3232643992
Short name T550
Test name
Test status
Simulation time 401556828 ps
CPU time 5.01 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 207740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232643992 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3232643992
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.728225949
Short name T570
Test name
Test status
Simulation time 4383437019 ps
CPU time 10.5 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:30 PM UTC 24
Peak memory 207732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728225949 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.728225949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1651764709
Short name T120
Test name
Test status
Simulation time 164069023 ps
CPU time 0.73 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651764709 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1651764709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1191055055
Short name T73
Test name
Test status
Simulation time 42570086 ps
CPU time 2.2 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 218164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1191055055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.1191055055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3434513182
Short name T538
Test name
Test status
Simulation time 14753655 ps
CPU time 0.58 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434513182 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3434513182
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1704905102
Short name T126
Test name
Test status
Simulation time 361824728 ps
CPU time 2.18 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:15 PM UTC 24
Peak memory 207908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704905102 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.1704905102
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.416584305
Short name T79
Test name
Test status
Simulation time 382767245 ps
CPU time 3.43 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416584305 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.416584305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.2567485458
Short name T147
Test name
Test status
Simulation time 3387827597 ps
CPU time 4.08 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 208060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567485458 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2567485458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.792540043
Short name T608
Test name
Test status
Simulation time 63920839 ps
CPU time 0.54 seconds
Started Sep 11 01:11:35 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792540043 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.792540043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.2978990473
Short name T582
Test name
Test status
Simulation time 12647280 ps
CPU time 0.54 seconds
Started Sep 11 01:11:36 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978990473 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2978990473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3172199663
Short name T581
Test name
Test status
Simulation time 71286044 ps
CPU time 0.54 seconds
Started Sep 11 01:11:37 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172199663 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3172199663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.392494235
Short name T548
Test name
Test status
Simulation time 48266751 ps
CPU time 0.54 seconds
Started Sep 11 01:11:37 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392494235 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.392494235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.877625195
Short name T586
Test name
Test status
Simulation time 14095191 ps
CPU time 0.6 seconds
Started Sep 11 01:11:37 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877625195 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.877625195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.162801841
Short name T587
Test name
Test status
Simulation time 50220756 ps
CPU time 0.61 seconds
Started Sep 11 01:11:37 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162801841 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.162801841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2839271138
Short name T589
Test name
Test status
Simulation time 32132086 ps
CPU time 0.55 seconds
Started Sep 11 01:11:38 PM UTC 24
Finished Sep 11 01:11:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839271138 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2839271138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.4089861973
Short name T613
Test name
Test status
Simulation time 16044060 ps
CPU time 0.63 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089861973 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4089861973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3937548253
Short name T612
Test name
Test status
Simulation time 12090495 ps
CPU time 0.57 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937548253 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3937548253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.494685246
Short name T611
Test name
Test status
Simulation time 12044862 ps
CPU time 0.52 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494685246 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.494685246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.3711504087
Short name T115
Test name
Test status
Simulation time 626124734 ps
CPU time 5.5 seconds
Started Sep 11 01:11:03 PM UTC 24
Finished Sep 11 01:11:09 PM UTC 24
Peak memory 207612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711504087 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3711504087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2490454147
Short name T117
Test name
Test status
Simulation time 1063697362 ps
CPU time 14.61 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:18 PM UTC 24
Peak memory 207752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490454147 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2490454147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.4220276360
Short name T113
Test name
Test status
Simulation time 136006492 ps
CPU time 0.76 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:04 PM UTC 24
Peak memory 206716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220276360 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4220276360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1931574854
Short name T70
Test name
Test status
Simulation time 144777184 ps
CPU time 0.97 seconds
Started Sep 11 01:11:05 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1931574854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.1931574854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3433289932
Short name T96
Test name
Test status
Simulation time 57565984 ps
CPU time 0.59 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:04 PM UTC 24
Peak memory 206516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433289932 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3433289932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.149140825
Short name T95
Test name
Test status
Simulation time 44928138 ps
CPU time 0.53 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:04 PM UTC 24
Peak memory 204576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149140825 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.149140825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4131184819
Short name T127
Test name
Test status
Simulation time 221026355 ps
CPU time 1.02 seconds
Started Sep 11 01:11:05 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131184819 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.4131184819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.2727335029
Short name T76
Test name
Test status
Simulation time 146701100 ps
CPU time 1.75 seconds
Started Sep 11 01:11:01 PM UTC 24
Finished Sep 11 01:11:21 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727335029 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2727335029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.1325172838
Short name T610
Test name
Test status
Simulation time 49234464 ps
CPU time 0.51 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325172838 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1325172838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2453363043
Short name T615
Test name
Test status
Simulation time 16739918 ps
CPU time 0.58 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:45 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453363043 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2453363043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.3741132703
Short name T617
Test name
Test status
Simulation time 19175544 ps
CPU time 0.58 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:45 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741132703 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3741132703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.889743564
Short name T614
Test name
Test status
Simulation time 179214127 ps
CPU time 0.54 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:45 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889743564 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.889743564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1218150326
Short name T616
Test name
Test status
Simulation time 41432647 ps
CPU time 0.53 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:45 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218150326 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1218150326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.638126369
Short name T618
Test name
Test status
Simulation time 15959244 ps
CPU time 0.58 seconds
Started Sep 11 01:11:40 PM UTC 24
Finished Sep 11 01:11:45 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638126369 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.638126369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2715680789
Short name T621
Test name
Test status
Simulation time 74718645 ps
CPU time 0.58 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715680789 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2715680789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.3399908155
Short name T620
Test name
Test status
Simulation time 48858775 ps
CPU time 0.54 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399908155 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3399908155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.2296277636
Short name T622
Test name
Test status
Simulation time 56278012 ps
CPU time 0.54 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296277636 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2296277636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.3513983456
Short name T124
Test name
Test status
Simulation time 618710807 ps
CPU time 2.69 seconds
Started Sep 11 01:11:06 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 207592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513983456 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3513983456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2219330081
Short name T571
Test name
Test status
Simulation time 8779534628 ps
CPU time 9.71 seconds
Started Sep 11 01:11:06 PM UTC 24
Finished Sep 11 01:11:31 PM UTC 24
Peak memory 207732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219330081 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2219330081
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2941981907
Short name T540
Test name
Test status
Simulation time 29289502 ps
CPU time 0.82 seconds
Started Sep 11 01:11:06 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 206716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941981907 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2941981907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.699174334
Short name T636
Test name
Test status
Simulation time 60947241365 ps
CPU time 140.29 seconds
Started Sep 11 01:11:10 PM UTC 24
Finished Sep 11 01:13:43 PM UTC 24
Peak memory 224168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=699174334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_re
set.699174334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.257668841
Short name T131
Test name
Test status
Simulation time 138909550 ps
CPU time 0.59 seconds
Started Sep 11 01:11:06 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 206248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257668841 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.257668841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3656026745
Short name T537
Test name
Test status
Simulation time 20523372 ps
CPU time 0.49 seconds
Started Sep 11 01:11:05 PM UTC 24
Finished Sep 11 01:11:19 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656026745 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3656026745
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1654732546
Short name T130
Test name
Test status
Simulation time 90976650 ps
CPU time 1.64 seconds
Started Sep 11 01:11:09 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 206720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654732546 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.1654732546
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1891583710
Short name T77
Test name
Test status
Simulation time 26674765 ps
CPU time 1.23 seconds
Started Sep 11 01:11:05 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891583710 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1891583710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3491806918
Short name T623
Test name
Test status
Simulation time 84717748 ps
CPU time 0.53 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491806918 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3491806918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.176053923
Short name T625
Test name
Test status
Simulation time 14630579 ps
CPU time 0.54 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176053923 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.176053923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3943629854
Short name T624
Test name
Test status
Simulation time 26216970 ps
CPU time 0.57 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943629854 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3943629854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.3889029368
Short name T627
Test name
Test status
Simulation time 45902045 ps
CPU time 0.55 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889029368 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3889029368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.872681784
Short name T626
Test name
Test status
Simulation time 26211566 ps
CPU time 0.59 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872681784 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.872681784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1009162433
Short name T628
Test name
Test status
Simulation time 14904182 ps
CPU time 0.58 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009162433 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1009162433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.374674345
Short name T629
Test name
Test status
Simulation time 19276430 ps
CPU time 0.55 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374674345 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.374674345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3064434886
Short name T630
Test name
Test status
Simulation time 15152535 ps
CPU time 0.54 seconds
Started Sep 11 01:11:41 PM UTC 24
Finished Sep 11 01:11:50 PM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064434886 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3064434886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3017427901
Short name T606
Test name
Test status
Simulation time 19379261 ps
CPU time 0.58 seconds
Started Sep 11 01:11:42 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017427901 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3017427901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1270084557
Short name T605
Test name
Test status
Simulation time 36558107 ps
CPU time 0.55 seconds
Started Sep 11 01:11:42 PM UTC 24
Finished Sep 11 01:11:44 PM UTC 24
Peak memory 203400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270084557 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1270084557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1858845035
Short name T71
Test name
Test status
Simulation time 240792854 ps
CPU time 1.5 seconds
Started Sep 11 01:11:18 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1858845035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.1858845035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.2816507575
Short name T119
Test name
Test status
Simulation time 31761573 ps
CPU time 0.75 seconds
Started Sep 11 01:11:16 PM UTC 24
Finished Sep 11 01:11:19 PM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816507575 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2816507575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.1293117621
Short name T536
Test name
Test status
Simulation time 78345238 ps
CPU time 0.54 seconds
Started Sep 11 01:11:16 PM UTC 24
Finished Sep 11 01:11:19 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293117621 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1293117621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2223649384
Short name T129
Test name
Test status
Simulation time 219653540 ps
CPU time 1.95 seconds
Started Sep 11 01:11:18 PM UTC 24
Finished Sep 11 01:11:20 PM UTC 24
Peak memory 206724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223649384 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.2223649384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.902859651
Short name T545
Test name
Test status
Simulation time 647516408 ps
CPU time 3.5 seconds
Started Sep 11 01:11:12 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 207724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902859651 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.902859651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1522190630
Short name T151
Test name
Test status
Simulation time 86807679 ps
CPU time 1.62 seconds
Started Sep 11 01:11:13 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522190630 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1522190630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3595518428
Short name T542
Test name
Test status
Simulation time 297418116 ps
CPU time 1.83 seconds
Started Sep 11 01:11:20 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3595518428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.3595518428
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.4284027139
Short name T122
Test name
Test status
Simulation time 95668216 ps
CPU time 0.85 seconds
Started Sep 11 01:11:20 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 206528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284027139 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4284027139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2027487121
Short name T539
Test name
Test status
Simulation time 13922424 ps
CPU time 0.58 seconds
Started Sep 11 01:11:20 PM UTC 24
Finished Sep 11 01:11:21 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027487121 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2027487121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4170657161
Short name T132
Test name
Test status
Simulation time 292549759 ps
CPU time 1.52 seconds
Started Sep 11 01:11:20 PM UTC 24
Finished Sep 11 01:11:22 PM UTC 24
Peak memory 206708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170657161 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.4170657161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.275747073
Short name T78
Test name
Test status
Simulation time 751873984 ps
CPU time 3.14 seconds
Started Sep 11 01:11:19 PM UTC 24
Finished Sep 11 01:11:23 PM UTC 24
Peak memory 207732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275747073 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.275747073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.482106668
Short name T68
Test name
Test status
Simulation time 167975462 ps
CPU time 1.49 seconds
Started Sep 11 01:11:19 PM UTC 24
Finished Sep 11 01:11:21 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482106668 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.482106668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1293727273
Short name T562
Test name
Test status
Simulation time 53460900 ps
CPU time 2.96 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:26 PM UTC 24
Peak memory 217960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1293727273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.1293727273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.4058324137
Short name T125
Test name
Test status
Simulation time 42069774 ps
CPU time 0.71 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 206712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058324137 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4058324137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.3902918125
Short name T544
Test name
Test status
Simulation time 73513478 ps
CPU time 0.65 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902918125 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3902918125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2162699641
Short name T558
Test name
Test status
Simulation time 546907815 ps
CPU time 1.99 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162699641 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.2162699641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.300315167
Short name T561
Test name
Test status
Simulation time 166237942 ps
CPU time 3.1 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:26 PM UTC 24
Peak memory 207788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300315167 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.300315167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.1273312133
Short name T149
Test name
Test status
Simulation time 269881851 ps
CPU time 2.63 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:26 PM UTC 24
Peak memory 207656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273312133 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1273312133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1011859997
Short name T564
Test name
Test status
Simulation time 302126711 ps
CPU time 2.87 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:27 PM UTC 24
Peak memory 223624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1011859997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.1011859997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.2891313335
Short name T547
Test name
Test status
Simulation time 37547726 ps
CPU time 0.64 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 206712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891313335 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2891313335
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1260959461
Short name T546
Test name
Test status
Simulation time 29569085 ps
CPU time 0.57 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260959461 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1260959461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.235015444
Short name T554
Test name
Test status
Simulation time 145717346 ps
CPU time 1.13 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235015444 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.235015444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2414363152
Short name T557
Test name
Test status
Simulation time 103071120 ps
CPU time 1.92 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414363152 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2414363152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3042096658
Short name T150
Test name
Test status
Simulation time 1458742831 ps
CPU time 3.7 seconds
Started Sep 11 01:11:21 PM UTC 24
Finished Sep 11 01:11:27 PM UTC 24
Peak memory 207656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042096658 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3042096658
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3923439080
Short name T559
Test name
Test status
Simulation time 26291877 ps
CPU time 1.48 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3923439080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3923439080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.3644872751
Short name T553
Test name
Test status
Simulation time 57452452 ps
CPU time 0.91 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644872751 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3644872751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.3655390872
Short name T549
Test name
Test status
Simulation time 37876534 ps
CPU time 0.51 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:24 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655390872 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3655390872
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2797835546
Short name T556
Test name
Test status
Simulation time 140683566 ps
CPU time 1.11 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:25 PM UTC 24
Peak memory 206792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797835546 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.2797835546
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1477512613
Short name T566
Test name
Test status
Simulation time 816382864 ps
CPU time 3.55 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:27 PM UTC 24
Peak memory 207984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477512613 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1477512613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.754566975
Short name T560
Test name
Test status
Simulation time 327785405 ps
CPU time 1.74 seconds
Started Sep 11 01:11:23 PM UTC 24
Finished Sep 11 01:11:26 PM UTC 24
Peak memory 206604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754566975 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.754566975
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_alert_test.1374045199
Short name T21
Test name
Test status
Simulation time 31853886 ps
CPU time 0.56 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:30:57 PM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374045199 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1374045199
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.4079190267
Short name T357
Test name
Test status
Simulation time 8433952584 ps
CPU time 797.23 seconds
Started Sep 11 01:30:48 PM UTC 24
Finished Sep 11 01:44:14 PM UTC 24
Peak memory 753940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079190267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4079190267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_error.1790837783
Short name T86
Test name
Test status
Simulation time 46385211705 ps
CPU time 197.64 seconds
Started Sep 11 01:30:48 PM UTC 24
Finished Sep 11 01:34:09 PM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790837783 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1790837783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_long_msg.1072720354
Short name T164
Test name
Test status
Simulation time 14556071254 ps
CPU time 138.52 seconds
Started Sep 11 01:30:47 PM UTC 24
Finished Sep 11 01:33:08 PM UTC 24
Peak memory 213356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072720354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1072720354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_stress_all.706703996
Short name T146
Test name
Test status
Simulation time 19530832268 ps
CPU time 706.12 seconds
Started Sep 11 01:30:53 PM UTC 24
Finished Sep 11 01:42:48 PM UTC 24
Peak memory 491740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706703996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.706703996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.3784373917
Short name T134
Test name
Test status
Simulation time 6292902665 ps
CPU time 70.91 seconds
Started Sep 11 01:30:53 PM UTC 24
Finished Sep 11 01:32:06 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784373917 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3784373917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.2015500309
Short name T193
Test name
Test status
Simulation time 25717234647 ps
CPU time 136.03 seconds
Started Sep 11 01:30:53 PM UTC 24
Finished Sep 11 01:33:12 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015500309 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2015500309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.2700041207
Short name T312
Test name
Test status
Simulation time 122578969145 ps
CPU time 627.11 seconds
Started Sep 11 01:30:50 PM UTC 24
Finished Sep 11 01:41:25 PM UTC 24
Peak memory 206936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700041207 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2700041207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.1961141112
Short name T526
Test name
Test status
Simulation time 804698400628 ps
CPU time 2728.14 seconds
Started Sep 11 01:30:50 PM UTC 24
Finished Sep 11 02:16:50 PM UTC 24
Peak memory 227060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961141112 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1961141112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.253748388
Short name T532
Test name
Test status
Simulation time 513870600990 ps
CPU time 2999.13 seconds
Started Sep 11 01:30:50 PM UTC 24
Finished Sep 11 02:21:25 PM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253748388 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.253748388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3679131382
Short name T33
Test name
Test status
Simulation time 5043004167 ps
CPU time 60.55 seconds
Started Sep 11 01:30:49 PM UTC 24
Finished Sep 11 01:31:51 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679131382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3679131382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_alert_test.2245202602
Short name T25
Test name
Test status
Simulation time 11510061 ps
CPU time 0.67 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:31:00 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245202602 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2245202602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.754276213
Short name T369
Test name
Test status
Simulation time 9458637545 ps
CPU time 903.27 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:46:10 PM UTC 24
Peak memory 706784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754276213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.754276213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_error.3741405951
Short name T32
Test name
Test status
Simulation time 1242555452 ps
CPU time 16.26 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:31:13 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741405951 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3741405951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2778420558
Short name T84
Test name
Test status
Simulation time 63519403729 ps
CPU time 185.52 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:34:04 PM UTC 24
Peak memory 207420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778420558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2778420558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.4120998026
Short name T26
Test name
Test status
Simulation time 131646123 ps
CPU time 0.83 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:31:00 PM UTC 24
Peak memory 235560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120998026 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4120998026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_stress_all.2055184530
Short name T38
Test name
Test status
Simulation time 15415883515 ps
CPU time 1652.08 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:58:48 PM UTC 24
Peak memory 769952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055184530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2055184530
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.1837455360
Short name T56
Test name
Test status
Simulation time 1734302372 ps
CPU time 61.05 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:32:01 PM UTC 24
Peak memory 207364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837455360 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1837455360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2668694944
Short name T185
Test name
Test status
Simulation time 21717521268 ps
CPU time 57.97 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:31:58 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668694944 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2668694944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.4056318396
Short name T45
Test name
Test status
Simulation time 29855602510 ps
CPU time 88.31 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:32:29 PM UTC 24
Peak memory 207320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056318396 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.4056318396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.3351217532
Short name T160
Test name
Test status
Simulation time 52657618725 ps
CPU time 713.52 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 01:42:58 PM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351217532 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3351217532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.947569432
Short name T518
Test name
Test status
Simulation time 79483236914 ps
CPU time 2300.53 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 02:09:43 PM UTC 24
Peak memory 221036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947569432 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.947569432
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.3970452940
Short name T522
Test name
Test status
Simulation time 773238646726 ps
CPU time 2608.29 seconds
Started Sep 11 01:30:56 PM UTC 24
Finished Sep 11 02:14:55 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970452940 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3970452940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_alert_test.2942807784
Short name T198
Test name
Test status
Simulation time 17092161 ps
CPU time 0.9 seconds
Started Sep 11 01:33:29 PM UTC 24
Finished Sep 11 01:33:31 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942807784 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2942807784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.2232762392
Short name T30
Test name
Test status
Simulation time 5554930330 ps
CPU time 88.21 seconds
Started Sep 11 01:33:15 PM UTC 24
Finished Sep 11 01:34:45 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232762392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2232762392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.2702349831
Short name T169
Test name
Test status
Simulation time 2167915756 ps
CPU time 26.21 seconds
Started Sep 11 01:33:17 PM UTC 24
Finished Sep 11 01:33:45 PM UTC 24
Peak memory 207572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702349831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2702349831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.106378406
Short name T450
Test name
Test status
Simulation time 6483689859 ps
CPU time 1145.62 seconds
Started Sep 11 01:33:16 PM UTC 24
Finished Sep 11 01:52:34 PM UTC 24
Peak memory 725244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106378406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.106378406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_error.229939414
Short name T222
Test name
Test status
Simulation time 20443815705 ps
CPU time 129.75 seconds
Started Sep 11 01:33:18 PM UTC 24
Finished Sep 11 01:35:31 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229939414 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.229939414
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_long_msg.2049331686
Short name T181
Test name
Test status
Simulation time 2126595125 ps
CPU time 117.26 seconds
Started Sep 11 01:33:14 PM UTC 24
Finished Sep 11 01:35:13 PM UTC 24
Peak memory 207392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049331686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2049331686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_stress_all.2243977399
Short name T69
Test name
Test status
Simulation time 824463129 ps
CPU time 9.86 seconds
Started Sep 11 01:33:29 PM UTC 24
Finished Sep 11 01:33:40 PM UTC 24
Peak memory 207372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243977399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2243977399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.148928899
Short name T221
Test name
Test status
Simulation time 12480299185 ps
CPU time 119.76 seconds
Started Sep 11 01:33:26 PM UTC 24
Finished Sep 11 01:35:29 PM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148928899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.148928899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_alert_test.3338250736
Short name T203
Test name
Test status
Simulation time 17593651 ps
CPU time 0.91 seconds
Started Sep 11 01:33:45 PM UTC 24
Finished Sep 11 01:33:48 PM UTC 24
Peak memory 203628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338250736 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3338250736
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.1450081925
Short name T162
Test name
Test status
Simulation time 3209194729 ps
CPU time 89.98 seconds
Started Sep 11 01:33:37 PM UTC 24
Finished Sep 11 01:35:09 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450081925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1450081925
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.1200579218
Short name T82
Test name
Test status
Simulation time 460630069 ps
CPU time 9.55 seconds
Started Sep 11 01:33:42 PM UTC 24
Finished Sep 11 01:33:53 PM UTC 24
Peak memory 207388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200579218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1200579218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.3524629116
Short name T305
Test name
Test status
Simulation time 2433558475 ps
CPU time 421 seconds
Started Sep 11 01:33:40 PM UTC 24
Finished Sep 11 01:40:46 PM UTC 24
Peak memory 694488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524629116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3524629116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_long_msg.2402803208
Short name T228
Test name
Test status
Simulation time 9783672360 ps
CPU time 131.67 seconds
Started Sep 11 01:33:35 PM UTC 24
Finished Sep 11 01:35:49 PM UTC 24
Peak memory 215684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402803208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2402803208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_smoke.3361061486
Short name T204
Test name
Test status
Simulation time 926274343 ps
CPU time 14.65 seconds
Started Sep 11 01:33:32 PM UTC 24
Finished Sep 11 01:33:48 PM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361061486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3361061486
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3483795056
Short name T515
Test name
Test status
Simulation time 12780373184 ps
CPU time 2028.05 seconds
Started Sep 11 01:33:42 PM UTC 24
Finished Sep 11 02:07:51 PM UTC 24
Peak memory 807448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483795056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3483795056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.3353359429
Short name T88
Test name
Test status
Simulation time 3876904750 ps
CPU time 33.8 seconds
Started Sep 11 01:33:42 PM UTC 24
Finished Sep 11 01:34:17 PM UTC 24
Peak memory 207380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353359429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3353359429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_alert_test.3644797826
Short name T85
Test name
Test status
Simulation time 30300135 ps
CPU time 0.94 seconds
Started Sep 11 01:34:03 PM UTC 24
Finished Sep 11 01:34:05 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644797826 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3644797826
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.3745596608
Short name T217
Test name
Test status
Simulation time 1209616432 ps
CPU time 89.28 seconds
Started Sep 11 01:33:49 PM UTC 24
Finished Sep 11 01:35:20 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745596608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3745596608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.886095658
Short name T207
Test name
Test status
Simulation time 5633720270 ps
CPU time 38.62 seconds
Started Sep 11 01:33:55 PM UTC 24
Finished Sep 11 01:34:35 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886095658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.886095658
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.115777810
Short name T292
Test name
Test status
Simulation time 7734225742 ps
CPU time 368.31 seconds
Started Sep 11 01:33:51 PM UTC 24
Finished Sep 11 01:40:04 PM UTC 24
Peak memory 676132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115777810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.115777810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_error.425287812
Short name T211
Test name
Test status
Simulation time 15054406303 ps
CPU time 56.08 seconds
Started Sep 11 01:33:55 PM UTC 24
Finished Sep 11 01:34:52 PM UTC 24
Peak memory 207368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425287812 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.425287812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_long_msg.3582691283
Short name T216
Test name
Test status
Simulation time 4982624631 ps
CPU time 87.95 seconds
Started Sep 11 01:33:49 PM UTC 24
Finished Sep 11 01:35:19 PM UTC 24
Peak memory 207380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582691283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3582691283
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_smoke.3876431501
Short name T83
Test name
Test status
Simulation time 1356704267 ps
CPU time 14.9 seconds
Started Sep 11 01:33:46 PM UTC 24
Finished Sep 11 01:34:02 PM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876431501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3876431501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_stress_all.4265985539
Short name T145
Test name
Test status
Simulation time 41767050119 ps
CPU time 437.91 seconds
Started Sep 11 01:33:57 PM UTC 24
Finished Sep 11 01:41:21 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265985539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4265985539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3862390406
Short name T229
Test name
Test status
Simulation time 16979291246 ps
CPU time 115.52 seconds
Started Sep 11 01:33:55 PM UTC 24
Finished Sep 11 01:35:53 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862390406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3862390406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_alert_test.3856208376
Short name T209
Test name
Test status
Simulation time 29838162 ps
CPU time 0.87 seconds
Started Sep 11 01:34:43 PM UTC 24
Finished Sep 11 01:34:45 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856208376 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3856208376
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.395024465
Short name T208
Test name
Test status
Simulation time 1418188230 ps
CPU time 24.2 seconds
Started Sep 11 01:34:10 PM UTC 24
Finished Sep 11 01:34:36 PM UTC 24
Peak memory 207260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395024465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.395024465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.404280426
Short name T225
Test name
Test status
Simulation time 10743332478 ps
CPU time 81.35 seconds
Started Sep 11 01:34:19 PM UTC 24
Finished Sep 11 01:35:42 PM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404280426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.404280426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.59531763
Short name T482
Test name
Test status
Simulation time 24032084569 ps
CPU time 1221.01 seconds
Started Sep 11 01:34:16 PM UTC 24
Finished Sep 11 01:54:51 PM UTC 24
Peak memory 753964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59531763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.59531763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_error.3050450719
Short name T249
Test name
Test status
Simulation time 10986217738 ps
CPU time 137.01 seconds
Started Sep 11 01:34:26 PM UTC 24
Finished Sep 11 01:36:45 PM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050450719 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3050450719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_long_msg.2129665314
Short name T87
Test name
Test status
Simulation time 1929103918 ps
CPU time 8.45 seconds
Started Sep 11 01:34:06 PM UTC 24
Finished Sep 11 01:34:16 PM UTC 24
Peak memory 207324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129665314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2129665314
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_smoke.3715230651
Short name T206
Test name
Test status
Simulation time 606127126 ps
CPU time 17.62 seconds
Started Sep 11 01:34:06 PM UTC 24
Finished Sep 11 01:34:25 PM UTC 24
Peak memory 207316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715230651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3715230651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_stress_all.3767243777
Short name T74
Test name
Test status
Simulation time 5459254617 ps
CPU time 116.58 seconds
Started Sep 11 01:34:37 PM UTC 24
Finished Sep 11 01:36:36 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767243777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3767243777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.435030467
Short name T210
Test name
Test status
Simulation time 186778815 ps
CPU time 13.29 seconds
Started Sep 11 01:34:36 PM UTC 24
Finished Sep 11 01:34:50 PM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435030467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.435030467
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_alert_test.501274513
Short name T215
Test name
Test status
Simulation time 27290652 ps
CPU time 0.9 seconds
Started Sep 11 01:35:11 PM UTC 24
Finished Sep 11 01:35:14 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501274513 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.501274513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.2607703609
Short name T232
Test name
Test status
Simulation time 2530242099 ps
CPU time 69.53 seconds
Started Sep 11 01:34:47 PM UTC 24
Finished Sep 11 01:35:59 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607703609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2607703609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.3237662591
Short name T214
Test name
Test status
Simulation time 728210173 ps
CPU time 17.08 seconds
Started Sep 11 01:34:54 PM UTC 24
Finished Sep 11 01:35:12 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237662591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3237662591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.523969765
Short name T159
Test name
Test status
Simulation time 2432594992 ps
CPU time 100.79 seconds
Started Sep 11 01:34:52 PM UTC 24
Finished Sep 11 01:36:34 PM UTC 24
Peak memory 377052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523969765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.523969765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_error.1607740635
Short name T227
Test name
Test status
Simulation time 805091752 ps
CPU time 48.71 seconds
Started Sep 11 01:34:58 PM UTC 24
Finished Sep 11 01:35:48 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607740635 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1607740635
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_long_msg.2777665518
Short name T239
Test name
Test status
Simulation time 4642397264 ps
CPU time 83.77 seconds
Started Sep 11 01:34:47 PM UTC 24
Finished Sep 11 01:36:13 PM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777665518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2777665518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_smoke.2509535612
Short name T213
Test name
Test status
Simulation time 421696289 ps
CPU time 10.11 seconds
Started Sep 11 01:34:47 PM UTC 24
Finished Sep 11 01:34:59 PM UTC 24
Peak memory 207260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509535612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2509535612
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_stress_all.3535617205
Short name T89
Test name
Test status
Simulation time 292993675706 ps
CPU time 592.82 seconds
Started Sep 11 01:35:06 PM UTC 24
Finished Sep 11 01:45:07 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535617205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3535617205
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.4192933956
Short name T223
Test name
Test status
Simulation time 1913818658 ps
CPU time 34.74 seconds
Started Sep 11 01:35:00 PM UTC 24
Finished Sep 11 01:35:37 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192933956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4192933956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_alert_test.4225670105
Short name T220
Test name
Test status
Simulation time 41781161 ps
CPU time 0.9 seconds
Started Sep 11 01:35:26 PM UTC 24
Finished Sep 11 01:35:28 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225670105 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4225670105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.1286972561
Short name T251
Test name
Test status
Simulation time 6715255503 ps
CPU time 94.84 seconds
Started Sep 11 01:35:15 PM UTC 24
Finished Sep 11 01:36:52 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286972561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1286972561
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.1289864834
Short name T234
Test name
Test status
Simulation time 3638376639 ps
CPU time 40.59 seconds
Started Sep 11 01:35:21 PM UTC 24
Finished Sep 11 01:36:03 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289864834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1289864834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.1298391305
Short name T445
Test name
Test status
Simulation time 5285387938 ps
CPU time 1000.46 seconds
Started Sep 11 01:35:20 PM UTC 24
Finished Sep 11 01:52:11 PM UTC 24
Peak memory 686504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298391305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1298391305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_error.39693039
Short name T253
Test name
Test status
Simulation time 4657055568 ps
CPU time 87.17 seconds
Started Sep 11 01:35:26 PM UTC 24
Finished Sep 11 01:36:55 PM UTC 24
Peak memory 207320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39693039 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.39693039
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_long_msg.1796829222
Short name T235
Test name
Test status
Simulation time 626211118 ps
CPU time 47.03 seconds
Started Sep 11 01:35:15 PM UTC 24
Finished Sep 11 01:36:04 PM UTC 24
Peak memory 207072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796829222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1796829222
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_smoke.1688998446
Short name T218
Test name
Test status
Simulation time 126167139 ps
CPU time 8 seconds
Started Sep 11 01:35:13 PM UTC 24
Finished Sep 11 01:35:22 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688998446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1688998446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_stress_all.1161165402
Short name T142
Test name
Test status
Simulation time 4230380155 ps
CPU time 202.97 seconds
Started Sep 11 01:35:26 PM UTC 24
Finished Sep 11 01:38:52 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161165402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1161165402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.1031474772
Short name T273
Test name
Test status
Simulation time 31813608066 ps
CPU time 173.51 seconds
Started Sep 11 01:35:26 PM UTC 24
Finished Sep 11 01:38:23 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031474772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1031474772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_alert_test.1556572852
Short name T230
Test name
Test status
Simulation time 32970569 ps
CPU time 0.88 seconds
Started Sep 11 01:35:51 PM UTC 24
Finished Sep 11 01:35:53 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556572852 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1556572852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1409755889
Short name T24
Test name
Test status
Simulation time 1164132674 ps
CPU time 65.32 seconds
Started Sep 11 01:35:32 PM UTC 24
Finished Sep 11 01:36:39 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409755889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1409755889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.181117618
Short name T236
Test name
Test status
Simulation time 2390529836 ps
CPU time 23.52 seconds
Started Sep 11 01:35:43 PM UTC 24
Finished Sep 11 01:36:08 PM UTC 24
Peak memory 207228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181117618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.181117618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.2881249617
Short name T370
Test name
Test status
Simulation time 16849107115 ps
CPU time 627.39 seconds
Started Sep 11 01:35:38 PM UTC 24
Finished Sep 11 01:46:13 PM UTC 24
Peak memory 610604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881249617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2881249617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_error.2805248776
Short name T274
Test name
Test status
Simulation time 2720810980 ps
CPU time 158.23 seconds
Started Sep 11 01:35:43 PM UTC 24
Finished Sep 11 01:38:24 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805248776 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2805248776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_long_msg.3187794423
Short name T233
Test name
Test status
Simulation time 472395904 ps
CPU time 31.3 seconds
Started Sep 11 01:35:30 PM UTC 24
Finished Sep 11 01:36:03 PM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187794423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3187794423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_smoke.2606725263
Short name T226
Test name
Test status
Simulation time 2749515526 ps
CPU time 13.78 seconds
Started Sep 11 01:35:30 PM UTC 24
Finished Sep 11 01:35:45 PM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606725263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2606725263
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_stress_all.4127375819
Short name T275
Test name
Test status
Simulation time 22355676473 ps
CPU time 156.02 seconds
Started Sep 11 01:35:51 PM UTC 24
Finished Sep 11 01:38:30 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127375819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4127375819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2968195581
Short name T140
Test name
Test status
Simulation time 11861844995 ps
CPU time 80.07 seconds
Started Sep 11 01:35:46 PM UTC 24
Finished Sep 11 01:37:08 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968195581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2968195581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_alert_test.285045344
Short name T238
Test name
Test status
Simulation time 11299674 ps
CPU time 0.85 seconds
Started Sep 11 01:36:10 PM UTC 24
Finished Sep 11 01:36:12 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285045344 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.285045344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.252189306
Short name T250
Test name
Test status
Simulation time 2551662454 ps
CPU time 47.55 seconds
Started Sep 11 01:36:00 PM UTC 24
Finished Sep 11 01:36:49 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252189306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.252189306
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.3069473259
Short name T244
Test name
Test status
Simulation time 1059572372 ps
CPU time 18.72 seconds
Started Sep 11 01:36:04 PM UTC 24
Finished Sep 11 01:36:24 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069473259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3069473259
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.4223367572
Short name T308
Test name
Test status
Simulation time 9762477222 ps
CPU time 309.53 seconds
Started Sep 11 01:36:00 PM UTC 24
Finished Sep 11 01:41:13 PM UTC 24
Peak memory 719380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223367572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4223367572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_error.2940072766
Short name T279
Test name
Test status
Simulation time 11405701963 ps
CPU time 160.3 seconds
Started Sep 11 01:36:04 PM UTC 24
Finished Sep 11 01:38:47 PM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940072766 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2940072766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_long_msg.1856838391
Short name T246
Test name
Test status
Simulation time 21565356535 ps
CPU time 42.11 seconds
Started Sep 11 01:35:55 PM UTC 24
Finished Sep 11 01:36:38 PM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856838391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1856838391
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_smoke.1014744669
Short name T237
Test name
Test status
Simulation time 1086081690 ps
CPU time 12.56 seconds
Started Sep 11 01:35:55 PM UTC 24
Finished Sep 11 01:36:08 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014744669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1014744669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_stress_all.1284787893
Short name T252
Test name
Test status
Simulation time 9012441978 ps
CPU time 44.04 seconds
Started Sep 11 01:36:09 PM UTC 24
Finished Sep 11 01:36:54 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284787893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1284787893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.3267672744
Short name T139
Test name
Test status
Simulation time 13018713670 ps
CPU time 52.98 seconds
Started Sep 11 01:36:06 PM UTC 24
Finished Sep 11 01:37:00 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267672744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3267672744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_alert_test.1891096601
Short name T247
Test name
Test status
Simulation time 124996093 ps
CPU time 0.97 seconds
Started Sep 11 01:36:37 PM UTC 24
Finished Sep 11 01:36:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891096601 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1891096601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.4257848250
Short name T263
Test name
Test status
Simulation time 3960587321 ps
CPU time 55.18 seconds
Started Sep 11 01:36:18 PM UTC 24
Finished Sep 11 01:37:15 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257848250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4257848250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.2142513381
Short name T245
Test name
Test status
Simulation time 295263477 ps
CPU time 7.35 seconds
Started Sep 11 01:36:21 PM UTC 24
Finished Sep 11 01:36:30 PM UTC 24
Peak memory 207324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142513381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2142513381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.590773392
Short name T331
Test name
Test status
Simulation time 7068407490 ps
CPU time 358.61 seconds
Started Sep 11 01:36:19 PM UTC 24
Finished Sep 11 01:42:22 PM UTC 24
Peak memory 713124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590773392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.590773392
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_error.477789888
Short name T259
Test name
Test status
Simulation time 9744508214 ps
CPU time 42.56 seconds
Started Sep 11 01:36:25 PM UTC 24
Finished Sep 11 01:37:09 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477789888 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.477789888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_long_msg.2535235243
Short name T287
Test name
Test status
Simulation time 9834317330 ps
CPU time 175.97 seconds
Started Sep 11 01:36:14 PM UTC 24
Finished Sep 11 01:39:13 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535235243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2535235243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_smoke.253065549
Short name T241
Test name
Test status
Simulation time 3189908992 ps
CPU time 5.9 seconds
Started Sep 11 01:36:12 PM UTC 24
Finished Sep 11 01:36:19 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253065549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.253065549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_stress_all.1720789168
Short name T168
Test name
Test status
Simulation time 9289858042 ps
CPU time 125.84 seconds
Started Sep 11 01:36:36 PM UTC 24
Finished Sep 11 01:38:44 PM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720789168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1720789168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.3295210143
Short name T264
Test name
Test status
Simulation time 13625091799 ps
CPU time 48.68 seconds
Started Sep 11 01:36:30 PM UTC 24
Finished Sep 11 01:37:21 PM UTC 24
Peak memory 207508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295210143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3295210143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_alert_test.4008033634
Short name T254
Test name
Test status
Simulation time 33132350 ps
CPU time 0.87 seconds
Started Sep 11 01:36:57 PM UTC 24
Finished Sep 11 01:36:58 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008033634 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4008033634
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.3332902359
Short name T255
Test name
Test status
Simulation time 238602966 ps
CPU time 17.58 seconds
Started Sep 11 01:36:41 PM UTC 24
Finished Sep 11 01:37:00 PM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332902359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3332902359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.3227618701
Short name T167
Test name
Test status
Simulation time 4473734823 ps
CPU time 36.3 seconds
Started Sep 11 01:36:47 PM UTC 24
Finished Sep 11 01:37:25 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227618701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3227618701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3586180396
Short name T495
Test name
Test status
Simulation time 14325435484 ps
CPU time 1203.98 seconds
Started Sep 11 01:36:45 PM UTC 24
Finished Sep 11 01:57:01 PM UTC 24
Peak memory 784736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586180396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3586180396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_error.691952966
Short name T269
Test name
Test status
Simulation time 1604208127 ps
CPU time 54.69 seconds
Started Sep 11 01:36:50 PM UTC 24
Finished Sep 11 01:37:47 PM UTC 24
Peak memory 207048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691952966 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.691952966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_long_msg.303360011
Short name T271
Test name
Test status
Simulation time 2777838054 ps
CPU time 84.49 seconds
Started Sep 11 01:36:39 PM UTC 24
Finished Sep 11 01:38:06 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303360011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.303360011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_smoke.872529573
Short name T248
Test name
Test status
Simulation time 207128224 ps
CPU time 4.1 seconds
Started Sep 11 01:36:39 PM UTC 24
Finished Sep 11 01:36:44 PM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872529573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.872529573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.664905573
Short name T261
Test name
Test status
Simulation time 350609281 ps
CPU time 18.5 seconds
Started Sep 11 01:36:54 PM UTC 24
Finished Sep 11 01:37:13 PM UTC 24
Peak memory 207048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664905573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.664905573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2322785111
Short name T27
Test name
Test status
Simulation time 17230698 ps
CPU time 0.73 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:31:05 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322785111 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2322785111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.1806452405
Short name T10
Test name
Test status
Simulation time 2502146629 ps
CPU time 20.05 seconds
Started Sep 11 01:31:01 PM UTC 24
Finished Sep 11 01:31:22 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806452405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1806452405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.995404908
Short name T14
Test name
Test status
Simulation time 3265085013 ps
CPU time 33.25 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:31:38 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995404908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.995404908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.173543465
Short name T257
Test name
Test status
Simulation time 44003260399 ps
CPU time 361.25 seconds
Started Sep 11 01:31:01 PM UTC 24
Finished Sep 11 01:37:06 PM UTC 24
Peak memory 477412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173543465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.173543465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_error.4294425222
Short name T59
Test name
Test status
Simulation time 2917316551 ps
CPU time 166.19 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:33:52 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294425222 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4294425222
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_long_msg.3669575934
Short name T180
Test name
Test status
Simulation time 2819135749 ps
CPU time 156.14 seconds
Started Sep 11 01:31:00 PM UTC 24
Finished Sep 11 01:33:39 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669575934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3669575934
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.3811054620
Short name T28
Test name
Test status
Simulation time 327699009 ps
CPU time 1.02 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:31:05 PM UTC 24
Peak memory 235560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811054620 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3811054620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_smoke.3579751497
Short name T9
Test name
Test status
Simulation time 3834203613 ps
CPU time 10.67 seconds
Started Sep 11 01:30:58 PM UTC 24
Finished Sep 11 01:31:10 PM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579751497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3579751497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.2819413230
Short name T57
Test name
Test status
Simulation time 18048361190 ps
CPU time 68.7 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:32:14 PM UTC 24
Peak memory 206880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819413230 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2819413230
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.3564331151
Short name T50
Test name
Test status
Simulation time 58358216651 ps
CPU time 96.94 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:32:42 PM UTC 24
Peak memory 207484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564331151 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3564331151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.3006458315
Short name T199
Test name
Test status
Simulation time 16700809219 ps
CPU time 149.24 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:33:35 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006458315 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3006458315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.647898880
Short name T328
Test name
Test status
Simulation time 165357880234 ps
CPU time 662.3 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:42:14 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647898880 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.647898880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.2155592179
Short name T530
Test name
Test status
Simulation time 1233641894986 ps
CPU time 2854.88 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 02:19:13 PM UTC 24
Peak memory 227320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155592179 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2155592179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.3152657803
Short name T533
Test name
Test status
Simulation time 947214384100 ps
CPU time 3312.97 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 02:26:55 PM UTC 24
Peak memory 221152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152657803 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3152657803
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.3756188381
Short name T52
Test name
Test status
Simulation time 2185158963 ps
CPU time 100.79 seconds
Started Sep 11 01:31:03 PM UTC 24
Finished Sep 11 01:32:46 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756188381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3756188381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_alert_test.2473146417
Short name T262
Test name
Test status
Simulation time 35502063 ps
CPU time 0.83 seconds
Started Sep 11 01:37:12 PM UTC 24
Finished Sep 11 01:37:15 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473146417 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2473146417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.57247732
Short name T260
Test name
Test status
Simulation time 144842306 ps
CPU time 9.35 seconds
Started Sep 11 01:37:01 PM UTC 24
Finished Sep 11 01:37:12 PM UTC 24
Peak memory 207372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57247732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.57247732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.2113573270
Short name T173
Test name
Test status
Simulation time 2109107274 ps
CPU time 31.53 seconds
Started Sep 11 01:37:08 PM UTC 24
Finished Sep 11 01:37:41 PM UTC 24
Peak memory 207260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113573270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2113573270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2789927342
Short name T457
Test name
Test status
Simulation time 9082349185 ps
CPU time 949.41 seconds
Started Sep 11 01:37:04 PM UTC 24
Finished Sep 11 01:53:04 PM UTC 24
Peak memory 757984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789927342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2789927342
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_error.5294682
Short name T278
Test name
Test status
Simulation time 5707490856 ps
CPU time 95.59 seconds
Started Sep 11 01:37:08 PM UTC 24
Finished Sep 11 01:38:46 PM UTC 24
Peak memory 207272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5294682 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.5294682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_long_msg.936547629
Short name T256
Test name
Test status
Simulation time 19955452 ps
CPU time 1.02 seconds
Started Sep 11 01:37:01 PM UTC 24
Finished Sep 11 01:37:03 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936547629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.936547629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_smoke.2942137495
Short name T258
Test name
Test status
Simulation time 609831069 ps
CPU time 6.27 seconds
Started Sep 11 01:37:00 PM UTC 24
Finished Sep 11 01:37:07 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942137495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2942137495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_stress_all.787892513
Short name T388
Test name
Test status
Simulation time 58728342570 ps
CPU time 584.87 seconds
Started Sep 11 01:37:10 PM UTC 24
Finished Sep 11 01:47:03 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787892513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.787892513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3958146370
Short name T270
Test name
Test status
Simulation time 2338361584 ps
CPU time 39.65 seconds
Started Sep 11 01:37:10 PM UTC 24
Finished Sep 11 01:37:52 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958146370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3958146370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2932719752
Short name T268
Test name
Test status
Simulation time 20549498 ps
CPU time 0.82 seconds
Started Sep 11 01:37:38 PM UTC 24
Finished Sep 11 01:37:39 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932719752 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2932719752
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.3757256966
Short name T242
Test name
Test status
Simulation time 3625361560 ps
CPU time 51.6 seconds
Started Sep 11 01:37:16 PM UTC 24
Finished Sep 11 01:38:09 PM UTC 24
Peak memory 223596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757256966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3757256966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.1096292787
Short name T266
Test name
Test status
Simulation time 77873847 ps
CPU time 2.52 seconds
Started Sep 11 01:37:26 PM UTC 24
Finished Sep 11 01:37:30 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096292787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1096292787
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3514536594
Short name T494
Test name
Test status
Simulation time 21631441744 ps
CPU time 1152.92 seconds
Started Sep 11 01:37:21 PM UTC 24
Finished Sep 11 01:56:47 PM UTC 24
Peak memory 772452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514536594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3514536594
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_error.3582635420
Short name T267
Test name
Test status
Simulation time 158299228 ps
CPU time 6.17 seconds
Started Sep 11 01:37:29 PM UTC 24
Finished Sep 11 01:37:36 PM UTC 24
Peak memory 207048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582635420 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3582635420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_long_msg.2196809946
Short name T285
Test name
Test status
Simulation time 5536480544 ps
CPU time 105.81 seconds
Started Sep 11 01:37:16 PM UTC 24
Finished Sep 11 01:39:04 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196809946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2196809946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_smoke.3028346571
Short name T265
Test name
Test status
Simulation time 1099654635 ps
CPU time 12.04 seconds
Started Sep 11 01:37:14 PM UTC 24
Finished Sep 11 01:37:28 PM UTC 24
Peak memory 207260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028346571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3028346571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_stress_all.2455702746
Short name T92
Test name
Test status
Simulation time 192648602624 ps
CPU time 1762.33 seconds
Started Sep 11 01:37:31 PM UTC 24
Finished Sep 11 02:07:13 PM UTC 24
Peak memory 784812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455702746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2455702746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.4223361352
Short name T141
Test name
Test status
Simulation time 883073167 ps
CPU time 47.38 seconds
Started Sep 11 01:37:31 PM UTC 24
Finished Sep 11 01:38:21 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223361352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4223361352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_alert_test.2252381672
Short name T272
Test name
Test status
Simulation time 50026417 ps
CPU time 0.83 seconds
Started Sep 11 01:38:11 PM UTC 24
Finished Sep 11 01:38:12 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252381672 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2252381672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.703455194
Short name T282
Test name
Test status
Simulation time 1121981582 ps
CPU time 69.93 seconds
Started Sep 11 01:37:43 PM UTC 24
Finished Sep 11 01:38:54 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703455194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.703455194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.852763085
Short name T219
Test name
Test status
Simulation time 318568335 ps
CPU time 5.13 seconds
Started Sep 11 01:37:52 PM UTC 24
Finished Sep 11 01:37:59 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852763085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.852763085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.770202194
Short name T423
Test name
Test status
Simulation time 9016926861 ps
CPU time 721.57 seconds
Started Sep 11 01:37:48 PM UTC 24
Finished Sep 11 01:49:57 PM UTC 24
Peak memory 766280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770202194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.770202194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_error.1604689036
Short name T304
Test name
Test status
Simulation time 17294300062 ps
CPU time 156.27 seconds
Started Sep 11 01:37:59 PM UTC 24
Finished Sep 11 01:40:38 PM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604689036 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1604689036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_long_msg.27689646
Short name T303
Test name
Test status
Simulation time 9742065272 ps
CPU time 169.68 seconds
Started Sep 11 01:37:43 PM UTC 24
Finished Sep 11 01:40:35 PM UTC 24
Peak memory 217784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27689646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.27689646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_smoke.3371916575
Short name T81
Test name
Test status
Simulation time 312206619 ps
CPU time 17.04 seconds
Started Sep 11 01:37:41 PM UTC 24
Finished Sep 11 01:37:59 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371916575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3371916575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_stress_all.92028909
Short name T506
Test name
Test status
Simulation time 60270926336 ps
CPU time 1744.03 seconds
Started Sep 11 01:38:07 PM UTC 24
Finished Sep 11 02:07:31 PM UTC 24
Peak memory 721172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92028909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.92028909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.3133217144
Short name T277
Test name
Test status
Simulation time 11768705663 ps
CPU time 32.03 seconds
Started Sep 11 01:38:00 PM UTC 24
Finished Sep 11 01:38:33 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133217144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3133217144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_alert_test.1133359851
Short name T280
Test name
Test status
Simulation time 11051086 ps
CPU time 0.86 seconds
Started Sep 11 01:38:45 PM UTC 24
Finished Sep 11 01:38:47 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133359851 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1133359851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.1067154696
Short name T289
Test name
Test status
Simulation time 883841018 ps
CPU time 66.21 seconds
Started Sep 11 01:38:21 PM UTC 24
Finished Sep 11 01:39:29 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067154696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1067154696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.1946052090
Short name T170
Test name
Test status
Simulation time 464136460 ps
CPU time 28.89 seconds
Started Sep 11 01:38:26 PM UTC 24
Finished Sep 11 01:38:57 PM UTC 24
Peak memory 207384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946052090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1946052090
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.3426384888
Short name T397
Test name
Test status
Simulation time 12601624200 ps
CPU time 577.29 seconds
Started Sep 11 01:38:24 PM UTC 24
Finished Sep 11 01:48:09 PM UTC 24
Peak memory 678164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426384888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3426384888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_error.4096851348
Short name T320
Test name
Test status
Simulation time 167782285263 ps
CPU time 196.05 seconds
Started Sep 11 01:38:31 PM UTC 24
Finished Sep 11 01:41:50 PM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096851348 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.4096851348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_long_msg.3564214983
Short name T300
Test name
Test status
Simulation time 30906663079 ps
CPU time 133.47 seconds
Started Sep 11 01:38:14 PM UTC 24
Finished Sep 11 01:40:30 PM UTC 24
Peak memory 207332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564214983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3564214983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_smoke.2265713218
Short name T276
Test name
Test status
Simulation time 1095283881 ps
CPU time 16.49 seconds
Started Sep 11 01:38:14 PM UTC 24
Finished Sep 11 01:38:32 PM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265713218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2265713218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_stress_all.693873523
Short name T311
Test name
Test status
Simulation time 3026718525 ps
CPU time 165.71 seconds
Started Sep 11 01:38:34 PM UTC 24
Finished Sep 11 01:41:22 PM UTC 24
Peak memory 217808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693873523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.693873523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.2544620415
Short name T284
Test name
Test status
Simulation time 1508677128 ps
CPU time 27.84 seconds
Started Sep 11 01:38:32 PM UTC 24
Finished Sep 11 01:39:02 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544620415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2544620415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_alert_test.3785190008
Short name T286
Test name
Test status
Simulation time 19533214 ps
CPU time 0.88 seconds
Started Sep 11 01:39:03 PM UTC 24
Finished Sep 11 01:39:05 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785190008 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3785190008
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.3695907982
Short name T297
Test name
Test status
Simulation time 2429515536 ps
CPU time 84.43 seconds
Started Sep 11 01:38:50 PM UTC 24
Finished Sep 11 01:40:16 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695907982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3695907982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2689022010
Short name T176
Test name
Test status
Simulation time 720268466 ps
CPU time 39.96 seconds
Started Sep 11 01:38:57 PM UTC 24
Finished Sep 11 01:39:38 PM UTC 24
Peak memory 207456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689022010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2689022010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.1331230031
Short name T498
Test name
Test status
Simulation time 5975726124 ps
CPU time 1136.01 seconds
Started Sep 11 01:38:53 PM UTC 24
Finished Sep 11 01:58:02 PM UTC 24
Peak memory 758244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331230031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1331230031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_error.1553637425
Short name T295
Test name
Test status
Simulation time 4483562434 ps
CPU time 74.89 seconds
Started Sep 11 01:38:57 PM UTC 24
Finished Sep 11 01:40:14 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553637425 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1553637425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_long_msg.2216098224
Short name T332
Test name
Test status
Simulation time 61808771504 ps
CPU time 217.73 seconds
Started Sep 11 01:38:48 PM UTC 24
Finished Sep 11 01:42:29 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216098224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2216098224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_smoke.3008575654
Short name T281
Test name
Test status
Simulation time 144266006 ps
CPU time 2.67 seconds
Started Sep 11 01:38:48 PM UTC 24
Finished Sep 11 01:38:51 PM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008575654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3008575654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_stress_all.2092052489
Short name T144
Test name
Test status
Simulation time 26653315007 ps
CPU time 131.7 seconds
Started Sep 11 01:39:03 PM UTC 24
Finished Sep 11 01:41:17 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092052489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2092052489
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.963109910
Short name T110
Test name
Test status
Simulation time 10589356991 ps
CPU time 152.83 seconds
Started Sep 11 01:38:58 PM UTC 24
Finished Sep 11 01:41:34 PM UTC 24
Peak memory 207508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963109910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.963109910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_alert_test.2840795109
Short name T294
Test name
Test status
Simulation time 15127328 ps
CPU time 0.93 seconds
Started Sep 11 01:40:08 PM UTC 24
Finished Sep 11 01:40:10 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840795109 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2840795109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.3408236955
Short name T291
Test name
Test status
Simulation time 3394758221 ps
CPU time 45.98 seconds
Started Sep 11 01:39:15 PM UTC 24
Finished Sep 11 01:40:02 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408236955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3408236955
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.433307343
Short name T177
Test name
Test status
Simulation time 679175371 ps
CPU time 49.09 seconds
Started Sep 11 01:39:31 PM UTC 24
Finished Sep 11 01:40:21 PM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433307343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.433307343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2485455202
Short name T407
Test name
Test status
Simulation time 15057819352 ps
CPU time 554.88 seconds
Started Sep 11 01:39:22 PM UTC 24
Finished Sep 11 01:48:43 PM UTC 24
Peak memory 678112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485455202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2485455202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_error.1466110626
Short name T333
Test name
Test status
Simulation time 10692104139 ps
CPU time 168.33 seconds
Started Sep 11 01:39:40 PM UTC 24
Finished Sep 11 01:42:31 PM UTC 24
Peak memory 207372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466110626 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1466110626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_long_msg.920111478
Short name T293
Test name
Test status
Simulation time 4256523729 ps
CPU time 60.11 seconds
Started Sep 11 01:39:06 PM UTC 24
Finished Sep 11 01:40:07 PM UTC 24
Peak memory 207508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920111478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.920111478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_smoke.2121476297
Short name T288
Test name
Test status
Simulation time 3265668308 ps
CPU time 14.28 seconds
Started Sep 11 01:39:06 PM UTC 24
Finished Sep 11 01:39:21 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121476297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2121476297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_stress_all.1391456952
Short name T296
Test name
Test status
Simulation time 1194288691 ps
CPU time 8.9 seconds
Started Sep 11 01:40:05 PM UTC 24
Finished Sep 11 01:40:15 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391456952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1391456952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.839115583
Short name T317
Test name
Test status
Simulation time 17417724753 ps
CPU time 113.03 seconds
Started Sep 11 01:39:51 PM UTC 24
Finished Sep 11 01:41:47 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839115583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.839115583
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_alert_test.1062935676
Short name T302
Test name
Test status
Simulation time 41521244 ps
CPU time 0.91 seconds
Started Sep 11 01:40:33 PM UTC 24
Finished Sep 11 01:40:35 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062935676 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1062935676
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.1763258510
Short name T323
Test name
Test status
Simulation time 5734690670 ps
CPU time 99.94 seconds
Started Sep 11 01:40:15 PM UTC 24
Finished Sep 11 01:41:57 PM UTC 24
Peak memory 223664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763258510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1763258510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.3648889984
Short name T301
Test name
Test status
Simulation time 665718657 ps
CPU time 12.52 seconds
Started Sep 11 01:40:18 PM UTC 24
Finished Sep 11 01:40:31 PM UTC 24
Peak memory 207392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648889984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3648889984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.1258107312
Short name T487
Test name
Test status
Simulation time 5863060857 ps
CPU time 904.79 seconds
Started Sep 11 01:40:18 PM UTC 24
Finished Sep 11 01:55:32 PM UTC 24
Peak memory 729624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258107312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1258107312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_error.3648261280
Short name T346
Test name
Test status
Simulation time 26588183129 ps
CPU time 181.68 seconds
Started Sep 11 01:40:24 PM UTC 24
Finished Sep 11 01:43:29 PM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648261280 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3648261280
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_long_msg.1249451868
Short name T306
Test name
Test status
Simulation time 6128577878 ps
CPU time 32.01 seconds
Started Sep 11 01:40:12 PM UTC 24
Finished Sep 11 01:40:46 PM UTC 24
Peak memory 215620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249451868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1249451868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_smoke.3634268389
Short name T298
Test name
Test status
Simulation time 2445914313 ps
CPU time 16.08 seconds
Started Sep 11 01:40:08 PM UTC 24
Finished Sep 11 01:40:26 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634268389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3634268389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_stress_all.3724281455
Short name T508
Test name
Test status
Simulation time 57409564389 ps
CPU time 1310.52 seconds
Started Sep 11 01:40:33 PM UTC 24
Finished Sep 11 02:02:38 PM UTC 24
Peak memory 760160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724281455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3724281455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.2697055054
Short name T309
Test name
Test status
Simulation time 2523499411 ps
CPU time 48.16 seconds
Started Sep 11 01:40:28 PM UTC 24
Finished Sep 11 01:41:18 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697055054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2697055054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_alert_test.2464367309
Short name T310
Test name
Test status
Simulation time 144730954 ps
CPU time 0.76 seconds
Started Sep 11 01:41:18 PM UTC 24
Finished Sep 11 01:41:20 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464367309 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2464367309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3023023479
Short name T324
Test name
Test status
Simulation time 1059771030 ps
CPU time 78.19 seconds
Started Sep 11 01:40:41 PM UTC 24
Finished Sep 11 01:42:01 PM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023023479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3023023479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1101279815
Short name T313
Test name
Test status
Simulation time 706736927 ps
CPU time 43.15 seconds
Started Sep 11 01:40:49 PM UTC 24
Finished Sep 11 01:41:33 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101279815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1101279815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.1488655771
Short name T364
Test name
Test status
Simulation time 5704887256 ps
CPU time 223.47 seconds
Started Sep 11 01:40:48 PM UTC 24
Finished Sep 11 01:44:35 PM UTC 24
Peak memory 465324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488655771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1488655771
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_error.3592183130
Short name T337
Test name
Test status
Simulation time 1851221636 ps
CPU time 105.97 seconds
Started Sep 11 01:40:51 PM UTC 24
Finished Sep 11 01:42:39 PM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592183130 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3592183130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_long_msg.1556846409
Short name T321
Test name
Test status
Simulation time 16597128019 ps
CPU time 74.55 seconds
Started Sep 11 01:40:36 PM UTC 24
Finished Sep 11 01:41:53 PM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556846409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1556846409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_smoke.3505556728
Short name T307
Test name
Test status
Simulation time 1192228326 ps
CPU time 12.22 seconds
Started Sep 11 01:40:36 PM UTC 24
Finished Sep 11 01:40:50 PM UTC 24
Peak memory 207384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505556728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3505556728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_stress_all.1482708533
Short name T404
Test name
Test status
Simulation time 60454182865 ps
CPU time 434.72 seconds
Started Sep 11 01:41:18 PM UTC 24
Finished Sep 11 01:48:39 PM UTC 24
Peak memory 207512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482708533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1482708533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.1690595628
Short name T358
Test name
Test status
Simulation time 40329096316 ps
CPU time 179.24 seconds
Started Sep 11 01:41:16 PM UTC 24
Finished Sep 11 01:44:18 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690595628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1690595628
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_alert_test.721123695
Short name T318
Test name
Test status
Simulation time 21303411 ps
CPU time 0.83 seconds
Started Sep 11 01:41:47 PM UTC 24
Finished Sep 11 01:41:49 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721123695 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.721123695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2629528262
Short name T334
Test name
Test status
Simulation time 796383661 ps
CPU time 63.34 seconds
Started Sep 11 01:41:29 PM UTC 24
Finished Sep 11 01:42:34 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629528262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2629528262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.851315788
Short name T319
Test name
Test status
Simulation time 1107382247 ps
CPU time 20.05 seconds
Started Sep 11 01:41:29 PM UTC 24
Finished Sep 11 01:41:50 PM UTC 24
Peak memory 207388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851315788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.851315788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.932934659
Short name T386
Test name
Test status
Simulation time 1973664465 ps
CPU time 325.5 seconds
Started Sep 11 01:41:29 PM UTC 24
Finished Sep 11 01:46:59 PM UTC 24
Peak memory 710816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932934659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.932934659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_error.96248835
Short name T361
Test name
Test status
Simulation time 12042290814 ps
CPU time 170.51 seconds
Started Sep 11 01:41:35 PM UTC 24
Finished Sep 11 01:44:28 PM UTC 24
Peak memory 207216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96248835 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.96248835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_long_msg.514997036
Short name T314
Test name
Test status
Simulation time 97572439 ps
CPU time 7.57 seconds
Started Sep 11 01:41:26 PM UTC 24
Finished Sep 11 01:41:34 PM UTC 24
Peak memory 207392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514997036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.514997036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_smoke.1181520055
Short name T316
Test name
Test status
Simulation time 336302716 ps
CPU time 15.92 seconds
Started Sep 11 01:41:26 PM UTC 24
Finished Sep 11 01:41:43 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181520055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1181520055
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_stress_all.1744033072
Short name T440
Test name
Test status
Simulation time 33632402879 ps
CPU time 604.47 seconds
Started Sep 11 01:41:35 PM UTC 24
Finished Sep 11 01:51:47 PM UTC 24
Peak memory 264352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744033072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1744033072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.2365469757
Short name T353
Test name
Test status
Simulation time 16785409154 ps
CPU time 137.58 seconds
Started Sep 11 01:41:35 PM UTC 24
Finished Sep 11 01:43:55 PM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365469757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2365469757
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_alert_test.3849055597
Short name T326
Test name
Test status
Simulation time 40689599 ps
CPU time 0.88 seconds
Started Sep 11 01:42:03 PM UTC 24
Finished Sep 11 01:42:05 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849055597 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3849055597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.3718881749
Short name T338
Test name
Test status
Simulation time 2132962824 ps
CPU time 55.29 seconds
Started Sep 11 01:41:50 PM UTC 24
Finished Sep 11 01:42:47 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718881749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3718881749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.3882872438
Short name T330
Test name
Test status
Simulation time 5113979188 ps
CPU time 27.59 seconds
Started Sep 11 01:41:52 PM UTC 24
Finished Sep 11 01:42:21 PM UTC 24
Peak memory 207512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882872438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3882872438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.3706762297
Short name T460
Test name
Test status
Simulation time 28170193825 ps
CPU time 690.01 seconds
Started Sep 11 01:41:52 PM UTC 24
Finished Sep 11 01:53:31 PM UTC 24
Peak memory 706836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706762297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3706762297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_error.572272361
Short name T104
Test name
Test status
Simulation time 12730536679 ps
CPU time 211.15 seconds
Started Sep 11 01:41:54 PM UTC 24
Finished Sep 11 01:45:29 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572272361 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.572272361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_long_msg.3528448308
Short name T299
Test name
Test status
Simulation time 12470079813 ps
CPU time 96.63 seconds
Started Sep 11 01:41:49 PM UTC 24
Finished Sep 11 01:43:28 PM UTC 24
Peak memory 215748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528448308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3528448308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_smoke.4139990027
Short name T322
Test name
Test status
Simulation time 1081818430 ps
CPU time 8.34 seconds
Started Sep 11 01:41:47 PM UTC 24
Finished Sep 11 01:41:57 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139990027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4139990027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.621579277
Short name T325
Test name
Test status
Simulation time 303791690 ps
CPU time 4.5 seconds
Started Sep 11 01:41:58 PM UTC 24
Finished Sep 11 01:42:03 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621579277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.621579277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3462033435
Short name T8
Test name
Test status
Simulation time 1640434194 ps
CPU time 25.63 seconds
Started Sep 11 01:31:08 PM UTC 24
Finished Sep 11 01:31:35 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462033435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3462033435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.3947022228
Short name T11
Test name
Test status
Simulation time 688945999 ps
CPU time 8.77 seconds
Started Sep 11 01:31:08 PM UTC 24
Finished Sep 11 01:31:18 PM UTC 24
Peak memory 207388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947022228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3947022228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.492699070
Short name T197
Test name
Test status
Simulation time 5014387027 ps
CPU time 137.61 seconds
Started Sep 11 01:31:08 PM UTC 24
Finished Sep 11 01:33:28 PM UTC 24
Peak memory 647500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492699070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.492699070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2339370124
Short name T55
Test name
Test status
Simulation time 7579121404 ps
CPU time 105.39 seconds
Started Sep 11 01:31:06 PM UTC 24
Finished Sep 11 01:32:53 PM UTC 24
Peak memory 207300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339370124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2339370124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2437177803
Short name T64
Test name
Test status
Simulation time 111170955 ps
CPU time 1.68 seconds
Started Sep 11 01:31:16 PM UTC 24
Finished Sep 11 01:31:18 PM UTC 24
Peak memory 235560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437177803 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2437177803
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_smoke.612838860
Short name T6
Test name
Test status
Simulation time 1833926325 ps
CPU time 8.13 seconds
Started Sep 11 01:31:06 PM UTC 24
Finished Sep 11 01:31:15 PM UTC 24
Peak memory 207152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612838860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.612838860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3256889319
Short name T46
Test name
Test status
Simulation time 14452049431 ps
CPU time 82.69 seconds
Started Sep 11 01:31:14 PM UTC 24
Finished Sep 11 01:32:38 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256889319 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3256889319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.1640922104
Short name T135
Test name
Test status
Simulation time 4401269579 ps
CPU time 59.13 seconds
Started Sep 11 01:31:14 PM UTC 24
Finished Sep 11 01:32:15 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640922104 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1640922104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.64793595
Short name T189
Test name
Test status
Simulation time 12150072657 ps
CPU time 107.03 seconds
Started Sep 11 01:31:14 PM UTC 24
Finished Sep 11 01:33:03 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64793595 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.64793595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.321119774
Short name T315
Test name
Test status
Simulation time 50141202515 ps
CPU time 623.77 seconds
Started Sep 11 01:31:11 PM UTC 24
Finished Sep 11 01:41:43 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321119774 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.321119774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.650671499
Short name T520
Test name
Test status
Simulation time 85106017238 ps
CPU time 2511.51 seconds
Started Sep 11 01:31:11 PM UTC 24
Finished Sep 11 02:13:33 PM UTC 24
Peak memory 227316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650671499 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.650671499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.3040474345
Short name T525
Test name
Test status
Simulation time 85033212109 ps
CPU time 2650.13 seconds
Started Sep 11 01:31:12 PM UTC 24
Finished Sep 11 02:15:52 PM UTC 24
Peak memory 227380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040474345 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3040474345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.2307178203
Short name T34
Test name
Test status
Simulation time 5086183577 ps
CPU time 54.02 seconds
Started Sep 11 01:31:09 PM UTC 24
Finished Sep 11 01:32:05 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307178203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2307178203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_alert_test.2899121401
Short name T335
Test name
Test status
Simulation time 35665665 ps
CPU time 0.86 seconds
Started Sep 11 01:42:32 PM UTC 24
Finished Sep 11 01:42:34 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899121401 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2899121401
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3906846549
Short name T342
Test name
Test status
Simulation time 894295297 ps
CPU time 58.87 seconds
Started Sep 11 01:42:11 PM UTC 24
Finished Sep 11 01:43:11 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906846549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3906846549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.3037128250
Short name T178
Test name
Test status
Simulation time 4424118190 ps
CPU time 39.5 seconds
Started Sep 11 01:42:18 PM UTC 24
Finished Sep 11 01:42:59 PM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037128250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3037128250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.2387976579
Short name T500
Test name
Test status
Simulation time 21362263887 ps
CPU time 994.54 seconds
Started Sep 11 01:42:17 PM UTC 24
Finished Sep 11 01:59:03 PM UTC 24
Peak memory 745804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387976579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2387976579
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_error.1546021847
Short name T339
Test name
Test status
Simulation time 2426866376 ps
CPU time 31.45 seconds
Started Sep 11 01:42:21 PM UTC 24
Finished Sep 11 01:42:54 PM UTC 24
Peak memory 207368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546021847 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1546021847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_long_msg.2163419436
Short name T329
Test name
Test status
Simulation time 2698865904 ps
CPU time 8.01 seconds
Started Sep 11 01:42:06 PM UTC 24
Finished Sep 11 01:42:16 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163419436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2163419436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_smoke.3275849770
Short name T327
Test name
Test status
Simulation time 243495926 ps
CPU time 4.01 seconds
Started Sep 11 01:42:04 PM UTC 24
Finished Sep 11 01:42:09 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275849770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3275849770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_stress_all.1774607750
Short name T434
Test name
Test status
Simulation time 3725241634 ps
CPU time 515.01 seconds
Started Sep 11 01:42:30 PM UTC 24
Finished Sep 11 01:51:11 PM UTC 24
Peak memory 717092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774607750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1774607750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.3973706912
Short name T366
Test name
Test status
Simulation time 31505450328 ps
CPU time 152.55 seconds
Started Sep 11 01:42:24 PM UTC 24
Finished Sep 11 01:45:00 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973706912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3973706912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_alert_test.110633837
Short name T341
Test name
Test status
Simulation time 48834207 ps
CPU time 0.8 seconds
Started Sep 11 01:43:05 PM UTC 24
Finished Sep 11 01:43:07 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110633837 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.110633837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.3437372004
Short name T37
Test name
Test status
Simulation time 404890426 ps
CPU time 11.9 seconds
Started Sep 11 01:42:38 PM UTC 24
Finished Sep 11 01:42:51 PM UTC 24
Peak memory 207116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437372004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3437372004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.1972173601
Short name T171
Test name
Test status
Simulation time 3324500829 ps
CPU time 35.85 seconds
Started Sep 11 01:42:48 PM UTC 24
Finished Sep 11 01:43:25 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972173601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1972173601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.1299980298
Short name T405
Test name
Test status
Simulation time 7748563869 ps
CPU time 354.88 seconds
Started Sep 11 01:42:41 PM UTC 24
Finished Sep 11 01:48:40 PM UTC 24
Peak memory 723164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299980298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1299980298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_error.1833458626
Short name T340
Test name
Test status
Simulation time 690611435 ps
CPU time 11.85 seconds
Started Sep 11 01:42:51 PM UTC 24
Finished Sep 11 01:43:04 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833458626 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1833458626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_long_msg.220773973
Short name T352
Test name
Test status
Simulation time 35289544353 ps
CPU time 76.32 seconds
Started Sep 11 01:42:35 PM UTC 24
Finished Sep 11 01:43:53 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220773973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.220773973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_smoke.1290978481
Short name T336
Test name
Test status
Simulation time 565272085 ps
CPU time 1.68 seconds
Started Sep 11 01:42:35 PM UTC 24
Finished Sep 11 01:42:38 PM UTC 24
Peak memory 206524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290978481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1290978481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_stress_all.1522972453
Short name T349
Test name
Test status
Simulation time 2522953853 ps
CPU time 44.81 seconds
Started Sep 11 01:42:56 PM UTC 24
Finished Sep 11 01:43:42 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522972453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1522972453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1196858288
Short name T344
Test name
Test status
Simulation time 355545670 ps
CPU time 22.12 seconds
Started Sep 11 01:42:52 PM UTC 24
Finished Sep 11 01:43:16 PM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196858288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1196858288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_alert_test.3230608242
Short name T347
Test name
Test status
Simulation time 11718286 ps
CPU time 0.88 seconds
Started Sep 11 01:43:29 PM UTC 24
Finished Sep 11 01:43:31 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230608242 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3230608242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.2863694788
Short name T355
Test name
Test status
Simulation time 1441704826 ps
CPU time 54.54 seconds
Started Sep 11 01:43:06 PM UTC 24
Finished Sep 11 01:44:02 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863694788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2863694788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.2414013808
Short name T356
Test name
Test status
Simulation time 17471953373 ps
CPU time 53.73 seconds
Started Sep 11 01:43:13 PM UTC 24
Finished Sep 11 01:44:08 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414013808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2414013808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.3270669171
Short name T409
Test name
Test status
Simulation time 6326473479 ps
CPU time 339.41 seconds
Started Sep 11 01:43:08 PM UTC 24
Finished Sep 11 01:48:52 PM UTC 24
Peak memory 706988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270669171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3270669171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_error.2740331916
Short name T99
Test name
Test status
Simulation time 9936423282 ps
CPU time 111.24 seconds
Started Sep 11 01:43:16 PM UTC 24
Finished Sep 11 01:45:09 PM UTC 24
Peak memory 207292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740331916 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2740331916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_long_msg.261774004
Short name T359
Test name
Test status
Simulation time 14700879055 ps
CPU time 73.53 seconds
Started Sep 11 01:43:05 PM UTC 24
Finished Sep 11 01:44:21 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261774004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.261774004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_smoke.1325602086
Short name T343
Test name
Test status
Simulation time 1041038000 ps
CPU time 8.64 seconds
Started Sep 11 01:43:05 PM UTC 24
Finished Sep 11 01:43:15 PM UTC 24
Peak memory 207384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325602086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1325602086
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_stress_all.1526020097
Short name T175
Test name
Test status
Simulation time 116012757100 ps
CPU time 475.65 seconds
Started Sep 11 01:43:26 PM UTC 24
Finished Sep 11 01:51:28 PM UTC 24
Peak memory 207512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526020097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1526020097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.3095474986
Short name T345
Test name
Test status
Simulation time 676398414 ps
CPU time 9.23 seconds
Started Sep 11 01:43:17 PM UTC 24
Finished Sep 11 01:43:28 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095474986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3095474986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_alert_test.3415122514
Short name T354
Test name
Test status
Simulation time 20958640 ps
CPU time 0.88 seconds
Started Sep 11 01:43:57 PM UTC 24
Finished Sep 11 01:43:59 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415122514 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3415122514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.1491081505
Short name T101
Test name
Test status
Simulation time 3362701760 ps
CPU time 108.13 seconds
Started Sep 11 01:43:31 PM UTC 24
Finished Sep 11 01:45:22 PM UTC 24
Peak memory 223572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491081505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1491081505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.1584107765
Short name T174
Test name
Test status
Simulation time 503559493 ps
CPU time 23.38 seconds
Started Sep 11 01:43:44 PM UTC 24
Finished Sep 11 01:44:09 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584107765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1584107765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.1477995572
Short name T505
Test name
Test status
Simulation time 5199638153 ps
CPU time 1057.72 seconds
Started Sep 11 01:43:43 PM UTC 24
Finished Sep 11 02:01:32 PM UTC 24
Peak memory 786704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477995572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1477995572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_error.1568864400
Short name T400
Test name
Test status
Simulation time 18817692802 ps
CPU time 267.73 seconds
Started Sep 11 01:43:49 PM UTC 24
Finished Sep 11 01:48:20 PM UTC 24
Peak memory 207364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568864400 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1568864400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_long_msg.991888044
Short name T350
Test name
Test status
Simulation time 233072292 ps
CPU time 16.5 seconds
Started Sep 11 01:43:30 PM UTC 24
Finished Sep 11 01:43:48 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991888044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.991888044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_smoke.3958515823
Short name T351
Test name
Test status
Simulation time 821272842 ps
CPU time 19.65 seconds
Started Sep 11 01:43:29 PM UTC 24
Finished Sep 11 01:43:50 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958515823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3958515823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_stress_all.3599880344
Short name T503
Test name
Test status
Simulation time 11153706990 ps
CPU time 1023.51 seconds
Started Sep 11 01:43:54 PM UTC 24
Finished Sep 11 02:01:08 PM UTC 24
Peak memory 733464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599880344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3599880344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.1400666107
Short name T367
Test name
Test status
Simulation time 4433561249 ps
CPU time 71.62 seconds
Started Sep 11 01:43:51 PM UTC 24
Finished Sep 11 01:45:04 PM UTC 24
Peak memory 207416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400666107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1400666107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_alert_test.953926822
Short name T362
Test name
Test status
Simulation time 12318371 ps
CPU time 0.72 seconds
Started Sep 11 01:44:30 PM UTC 24
Finished Sep 11 01:44:32 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953926822 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.953926822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.539968525
Short name T105
Test name
Test status
Simulation time 1458593326 ps
CPU time 86.62 seconds
Started Sep 11 01:44:09 PM UTC 24
Finished Sep 11 01:45:37 PM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539968525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.539968525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.3635072875
Short name T100
Test name
Test status
Simulation time 16244291889 ps
CPU time 62.06 seconds
Started Sep 11 01:44:16 PM UTC 24
Finished Sep 11 01:45:20 PM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635072875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3635072875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.1080223255
Short name T514
Test name
Test status
Simulation time 6228502778 ps
CPU time 1386.24 seconds
Started Sep 11 01:44:10 PM UTC 24
Finished Sep 11 02:07:30 PM UTC 24
Peak memory 786708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080223255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1080223255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_error.3858175696
Short name T373
Test name
Test status
Simulation time 39783963653 ps
CPU time 113.35 seconds
Started Sep 11 01:44:19 PM UTC 24
Finished Sep 11 01:46:15 PM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858175696 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3858175696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_long_msg.1595796150
Short name T363
Test name
Test status
Simulation time 1426916772 ps
CPU time 27.96 seconds
Started Sep 11 01:44:04 PM UTC 24
Finished Sep 11 01:44:33 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595796150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1595796150
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_smoke.1527496969
Short name T360
Test name
Test status
Simulation time 3410310968 ps
CPU time 20.08 seconds
Started Sep 11 01:44:00 PM UTC 24
Finished Sep 11 01:44:21 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527496969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1527496969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_stress_all.1984054298
Short name T529
Test name
Test status
Simulation time 135193885005 ps
CPU time 2048.08 seconds
Started Sep 11 01:44:22 PM UTC 24
Finished Sep 11 02:18:54 PM UTC 24
Peak memory 772212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984054298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1984054298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.1611197009
Short name T383
Test name
Test status
Simulation time 7320359596 ps
CPU time 145.85 seconds
Started Sep 11 01:44:22 PM UTC 24
Finished Sep 11 01:46:50 PM UTC 24
Peak memory 206984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611197009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1611197009
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_alert_test.853380270
Short name T102
Test name
Test status
Simulation time 15350056 ps
CPU time 0.69 seconds
Started Sep 11 01:45:21 PM UTC 24
Finished Sep 11 01:45:22 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853380270 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.853380270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.2524818435
Short name T374
Test name
Test status
Simulation time 5750222171 ps
CPU time 97.94 seconds
Started Sep 11 01:44:37 PM UTC 24
Finished Sep 11 01:46:17 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524818435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2524818435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.3943804781
Short name T107
Test name
Test status
Simulation time 17309236138 ps
CPU time 49.14 seconds
Started Sep 11 01:45:01 PM UTC 24
Finished Sep 11 01:45:52 PM UTC 24
Peak memory 217800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943804781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3943804781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1936433918
Short name T502
Test name
Test status
Simulation time 5105525847 ps
CPU time 940.24 seconds
Started Sep 11 01:44:41 PM UTC 24
Finished Sep 11 02:00:31 PM UTC 24
Peak memory 727468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936433918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1936433918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_error.753221581
Short name T384
Test name
Test status
Simulation time 10125410429 ps
CPU time 109.23 seconds
Started Sep 11 01:45:05 PM UTC 24
Finished Sep 11 01:46:57 PM UTC 24
Peak memory 207432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753221581 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.753221581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_long_msg.2744636548
Short name T379
Test name
Test status
Simulation time 22497401029 ps
CPU time 125.81 seconds
Started Sep 11 01:44:34 PM UTC 24
Finished Sep 11 01:46:43 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744636548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2744636548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_smoke.733668361
Short name T365
Test name
Test status
Simulation time 284402546 ps
CPU time 7.26 seconds
Started Sep 11 01:44:32 PM UTC 24
Finished Sep 11 01:44:40 PM UTC 24
Peak memory 207320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733668361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.733668361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_stress_all.2315462158
Short name T39
Test name
Test status
Simulation time 71616385112 ps
CPU time 1102.73 seconds
Started Sep 11 01:45:12 PM UTC 24
Finished Sep 11 02:03:47 PM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315462158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2315462158
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.873027956
Short name T106
Test name
Test status
Simulation time 8820490277 ps
CPU time 28.06 seconds
Started Sep 11 01:45:10 PM UTC 24
Finished Sep 11 01:45:40 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873027956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.873027956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_alert_test.2971893500
Short name T372
Test name
Test status
Simulation time 47406754 ps
CPU time 0.82 seconds
Started Sep 11 01:46:13 PM UTC 24
Finished Sep 11 01:46:14 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971893500 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2971893500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.520633413
Short name T371
Test name
Test status
Simulation time 2391609834 ps
CPU time 44.46 seconds
Started Sep 11 01:45:28 PM UTC 24
Finished Sep 11 01:46:14 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520633413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.520633413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3923643295
Short name T368
Test name
Test status
Simulation time 5338870580 ps
CPU time 26.06 seconds
Started Sep 11 01:45:39 PM UTC 24
Finished Sep 11 01:46:06 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923643295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3923643295
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.3197943499
Short name T464
Test name
Test status
Simulation time 3142451286 ps
CPU time 493.88 seconds
Started Sep 11 01:45:31 PM UTC 24
Finished Sep 11 01:53:50 PM UTC 24
Peak memory 649484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197943499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3197943499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_error.3709751498
Short name T410
Test name
Test status
Simulation time 3270397404 ps
CPU time 203.83 seconds
Started Sep 11 01:45:40 PM UTC 24
Finished Sep 11 01:49:07 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709751498 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3709751498
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_long_msg.2967162500
Short name T392
Test name
Test status
Simulation time 81093792310 ps
CPU time 117.97 seconds
Started Sep 11 01:45:24 PM UTC 24
Finished Sep 11 01:47:24 PM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967162500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2967162500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_smoke.2904432739
Short name T103
Test name
Test status
Simulation time 31337609 ps
CPU time 1.83 seconds
Started Sep 11 01:45:24 PM UTC 24
Finished Sep 11 01:45:27 PM UTC 24
Peak memory 206212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904432739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2904432739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_stress_all.780748630
Short name T465
Test name
Test status
Simulation time 40778538650 ps
CPU time 457.2 seconds
Started Sep 11 01:46:08 PM UTC 24
Finished Sep 11 01:53:51 PM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780748630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.780748630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.1110072168
Short name T382
Test name
Test status
Simulation time 3465693777 ps
CPU time 55.6 seconds
Started Sep 11 01:45:52 PM UTC 24
Finished Sep 11 01:46:50 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110072168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1110072168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_alert_test.3783867543
Short name T378
Test name
Test status
Simulation time 15834264 ps
CPU time 0.85 seconds
Started Sep 11 01:46:39 PM UTC 24
Finished Sep 11 01:46:41 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783867543 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3783867543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.54398386
Short name T380
Test name
Test status
Simulation time 3662867152 ps
CPU time 25.02 seconds
Started Sep 11 01:46:17 PM UTC 24
Finished Sep 11 01:46:43 PM UTC 24
Peak memory 207300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54398386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.54398386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2331271440
Short name T385
Test name
Test status
Simulation time 2019552421 ps
CPU time 36.53 seconds
Started Sep 11 01:46:19 PM UTC 24
Finished Sep 11 01:46:57 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331271440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2331271440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.3601974641
Short name T375
Test name
Test status
Simulation time 24526155 ps
CPU time 0.98 seconds
Started Sep 11 01:46:17 PM UTC 24
Finished Sep 11 01:46:19 PM UTC 24
Peak memory 206796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601974641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3601974641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_error.516015228
Short name T376
Test name
Test status
Simulation time 229909365 ps
CPU time 9.57 seconds
Started Sep 11 01:46:20 PM UTC 24
Finished Sep 11 01:46:31 PM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516015228 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.516015228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_long_msg.2710940538
Short name T408
Test name
Test status
Simulation time 15660585162 ps
CPU time 150.31 seconds
Started Sep 11 01:46:17 PM UTC 24
Finished Sep 11 01:48:50 PM UTC 24
Peak memory 207520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710940538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2710940538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_smoke.3935920817
Short name T377
Test name
Test status
Simulation time 632742067 ps
CPU time 15.08 seconds
Started Sep 11 01:46:15 PM UTC 24
Finished Sep 11 01:46:32 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935920817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3935920817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_stress_all.2769536487
Short name T513
Test name
Test status
Simulation time 13206051301 ps
CPU time 1097.17 seconds
Started Sep 11 01:46:32 PM UTC 24
Finished Sep 11 02:05:03 PM UTC 24
Peak memory 665876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769536487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2769536487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.3994227898
Short name T111
Test name
Test status
Simulation time 5501357009 ps
CPU time 68.16 seconds
Started Sep 11 01:46:31 PM UTC 24
Finished Sep 11 01:47:42 PM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994227898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3994227898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_alert_test.3813806577
Short name T387
Test name
Test status
Simulation time 13575396 ps
CPU time 0.82 seconds
Started Sep 11 01:47:00 PM UTC 24
Finished Sep 11 01:47:02 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813806577 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3813806577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.1013336514
Short name T394
Test name
Test status
Simulation time 816295032 ps
CPU time 58.08 seconds
Started Sep 11 01:46:45 PM UTC 24
Finished Sep 11 01:47:45 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013336514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1013336514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.1281824312
Short name T172
Test name
Test status
Simulation time 3078904109 ps
CPU time 56.14 seconds
Started Sep 11 01:46:50 PM UTC 24
Finished Sep 11 01:47:48 PM UTC 24
Peak memory 207512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281824312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1281824312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.1909272911
Short name T493
Test name
Test status
Simulation time 11015879219 ps
CPU time 588.63 seconds
Started Sep 11 01:46:48 PM UTC 24
Finished Sep 11 01:56:44 PM UTC 24
Peak memory 708888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909272911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1909272911
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_error.3369568808
Short name T418
Test name
Test status
Simulation time 11433103182 ps
CPU time 156.19 seconds
Started Sep 11 01:46:52 PM UTC 24
Finished Sep 11 01:49:31 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369568808 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3369568808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_long_msg.2000571879
Short name T389
Test name
Test status
Simulation time 653926086 ps
CPU time 17.17 seconds
Started Sep 11 01:46:45 PM UTC 24
Finished Sep 11 01:47:03 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000571879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2000571879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_smoke.1645995985
Short name T381
Test name
Test status
Simulation time 877068432 ps
CPU time 3.5 seconds
Started Sep 11 01:46:42 PM UTC 24
Finished Sep 11 01:46:47 PM UTC 24
Peak memory 207116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645995985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1645995985
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_stress_all.2072429746
Short name T179
Test name
Test status
Simulation time 10376407440 ps
CPU time 283.1 seconds
Started Sep 11 01:46:58 PM UTC 24
Finished Sep 11 01:51:45 PM UTC 24
Peak memory 217796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072429746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2072429746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.892550405
Short name T398
Test name
Test status
Simulation time 3746514714 ps
CPU time 71.63 seconds
Started Sep 11 01:46:58 PM UTC 24
Finished Sep 11 01:48:11 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892550405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.892550405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_alert_test.1846448535
Short name T395
Test name
Test status
Simulation time 44111061 ps
CPU time 0.79 seconds
Started Sep 11 01:47:46 PM UTC 24
Finished Sep 11 01:47:48 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846448535 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1846448535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.2154083914
Short name T391
Test name
Test status
Simulation time 334100115 ps
CPU time 10.33 seconds
Started Sep 11 01:47:07 PM UTC 24
Finished Sep 11 01:47:18 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154083914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2154083914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.1792125470
Short name T393
Test name
Test status
Simulation time 2360672430 ps
CPU time 23.75 seconds
Started Sep 11 01:47:19 PM UTC 24
Finished Sep 11 01:47:44 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792125470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1792125470
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.3817360793
Short name T519
Test name
Test status
Simulation time 7386480016 ps
CPU time 1410.22 seconds
Started Sep 11 01:47:11 PM UTC 24
Finished Sep 11 02:10:56 PM UTC 24
Peak memory 794844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817360793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3817360793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_error.2729494125
Short name T429
Test name
Test status
Simulation time 3106584197 ps
CPU time 187.55 seconds
Started Sep 11 01:47:26 PM UTC 24
Finished Sep 11 01:50:36 PM UTC 24
Peak memory 207292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729494125 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2729494125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_long_msg.2537879554
Short name T401
Test name
Test status
Simulation time 4639179701 ps
CPU time 73.27 seconds
Started Sep 11 01:47:06 PM UTC 24
Finished Sep 11 01:48:21 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537879554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2537879554
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_smoke.1810919376
Short name T390
Test name
Test status
Simulation time 506178987 ps
CPU time 3.06 seconds
Started Sep 11 01:47:06 PM UTC 24
Finished Sep 11 01:47:10 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810919376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1810919376
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_stress_all.4225890912
Short name T521
Test name
Test status
Simulation time 108930281519 ps
CPU time 1609.23 seconds
Started Sep 11 01:47:46 PM UTC 24
Finished Sep 11 02:14:52 PM UTC 24
Peak memory 788704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225890912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4225890912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.1794007134
Short name T411
Test name
Test status
Simulation time 3986843300 ps
CPU time 86.66 seconds
Started Sep 11 01:47:43 PM UTC 24
Finished Sep 11 01:49:12 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794007134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1794007134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_alert_test.1713191861
Short name T184
Test name
Test status
Simulation time 48336768 ps
CPU time 0.91 seconds
Started Sep 11 01:31:39 PM UTC 24
Finished Sep 11 01:31:41 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713191861 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1713191861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.3850412521
Short name T12
Test name
Test status
Simulation time 1880450121 ps
CPU time 20.96 seconds
Started Sep 11 01:31:16 PM UTC 24
Finished Sep 11 01:31:38 PM UTC 24
Peak memory 207208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850412521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3850412521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.662558508
Short name T29
Test name
Test status
Simulation time 258853327 ps
CPU time 17.71 seconds
Started Sep 11 01:31:18 PM UTC 24
Finished Sep 11 01:31:37 PM UTC 24
Peak memory 207172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662558508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.662558508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1594513703
Short name T420
Test name
Test status
Simulation time 24117645345 ps
CPU time 1089.4 seconds
Started Sep 11 01:31:16 PM UTC 24
Finished Sep 11 01:49:36 PM UTC 24
Peak memory 768232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594513703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1594513703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_error.2436922696
Short name T156
Test name
Test status
Simulation time 19826089209 ps
CPU time 240.01 seconds
Started Sep 11 01:31:19 PM UTC 24
Finished Sep 11 01:35:23 PM UTC 24
Peak memory 207300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436922696 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2436922696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.1231514425
Short name T65
Test name
Test status
Simulation time 318064251 ps
CPU time 1.48 seconds
Started Sep 11 01:31:39 PM UTC 24
Finished Sep 11 01:31:42 PM UTC 24
Peak memory 235556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231514425 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1231514425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_stress_all.2450435972
Short name T290
Test name
Test status
Simulation time 4163824571 ps
CPU time 486.51 seconds
Started Sep 11 01:31:36 PM UTC 24
Finished Sep 11 01:39:49 PM UTC 24
Peak memory 727340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450435972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2450435972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.3496386451
Short name T20
Test name
Test status
Simulation time 4712485168 ps
CPU time 132.29 seconds
Started Sep 11 01:31:37 PM UTC 24
Finished Sep 11 01:33:52 PM UTC 24
Peak memory 362472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34963864
51 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3496386451
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.1121413528
Short name T187
Test name
Test status
Simulation time 26136927619 ps
CPU time 84.27 seconds
Started Sep 11 01:31:29 PM UTC 24
Finished Sep 11 01:32:55 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121413528 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1121413528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.1411398292
Short name T49
Test name
Test status
Simulation time 1780504553 ps
CPU time 61.61 seconds
Started Sep 11 01:31:36 PM UTC 24
Finished Sep 11 01:32:40 PM UTC 24
Peak memory 207316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411398292 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1411398292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.763656917
Short name T200
Test name
Test status
Simulation time 13300274159 ps
CPU time 120.05 seconds
Started Sep 11 01:31:36 PM UTC 24
Finished Sep 11 01:33:39 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763656917 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.763656917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.2425856867
Short name T161
Test name
Test status
Simulation time 90249013071 ps
CPU time 693.35 seconds
Started Sep 11 01:31:19 PM UTC 24
Finished Sep 11 01:43:01 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425856867 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2425856867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.2143852571
Short name T524
Test name
Test status
Simulation time 137351222473 ps
CPU time 2621.45 seconds
Started Sep 11 01:31:23 PM UTC 24
Finished Sep 11 02:15:36 PM UTC 24
Peak memory 221432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143852571 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2143852571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1947105661
Short name T531
Test name
Test status
Simulation time 148375222024 ps
CPU time 2870.85 seconds
Started Sep 11 01:31:26 PM UTC 24
Finished Sep 11 02:19:50 PM UTC 24
Peak memory 221248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947105661 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1947105661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.681427889
Short name T109
Test name
Test status
Simulation time 6117251405 ps
CPU time 92.16 seconds
Started Sep 11 01:31:19 PM UTC 24
Finished Sep 11 01:32:53 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681427889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.681427889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_alert_test.629996604
Short name T403
Test name
Test status
Simulation time 67231298 ps
CPU time 0.83 seconds
Started Sep 11 01:48:23 PM UTC 24
Finished Sep 11 01:48:25 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629996604 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.629996604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.1340008535
Short name T402
Test name
Test status
Simulation time 907785182 ps
CPU time 23.21 seconds
Started Sep 11 01:47:58 PM UTC 24
Finished Sep 11 01:48:22 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340008535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1340008535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.4077792439
Short name T413
Test name
Test status
Simulation time 5121424328 ps
CPU time 60.2 seconds
Started Sep 11 01:48:12 PM UTC 24
Finished Sep 11 01:49:14 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077792439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4077792439
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.3868834090
Short name T507
Test name
Test status
Simulation time 8363906288 ps
CPU time 823.14 seconds
Started Sep 11 01:48:12 PM UTC 24
Finished Sep 11 02:02:05 PM UTC 24
Peak memory 712924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868834090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3868834090
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_error.2956623983
Short name T444
Test name
Test status
Simulation time 18195488576 ps
CPU time 226.4 seconds
Started Sep 11 01:48:18 PM UTC 24
Finished Sep 11 01:52:08 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956623983 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2956623983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_long_msg.4065400509
Short name T422
Test name
Test status
Simulation time 7612367722 ps
CPU time 118.73 seconds
Started Sep 11 01:47:49 PM UTC 24
Finished Sep 11 01:49:50 PM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065400509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4065400509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_smoke.3301691772
Short name T396
Test name
Test status
Simulation time 406349984 ps
CPU time 7.63 seconds
Started Sep 11 01:47:49 PM UTC 24
Finished Sep 11 01:47:58 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301691772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3301691772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_stress_all.3888531252
Short name T442
Test name
Test status
Simulation time 46455277863 ps
CPU time 220.54 seconds
Started Sep 11 01:48:23 PM UTC 24
Finished Sep 11 01:52:07 PM UTC 24
Peak memory 207320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888531252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3888531252
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.1763014869
Short name T416
Test name
Test status
Simulation time 5459994961 ps
CPU time 61.04 seconds
Started Sep 11 01:48:23 PM UTC 24
Finished Sep 11 01:49:26 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763014869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1763014869
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_alert_test.188968577
Short name T414
Test name
Test status
Simulation time 14233207 ps
CPU time 0.81 seconds
Started Sep 11 01:49:13 PM UTC 24
Finished Sep 11 01:49:15 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188968577 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.188968577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.2218047773
Short name T35
Test name
Test status
Simulation time 17584899420 ps
CPU time 112.22 seconds
Started Sep 11 01:48:41 PM UTC 24
Finished Sep 11 01:50:36 PM UTC 24
Peak memory 215752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218047773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2218047773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.3001042713
Short name T415
Test name
Test status
Simulation time 2439721215 ps
CPU time 28.28 seconds
Started Sep 11 01:48:46 PM UTC 24
Finished Sep 11 01:49:16 PM UTC 24
Peak memory 207384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001042713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3001042713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.1707841403
Short name T509
Test name
Test status
Simulation time 8980053206 ps
CPU time 891.98 seconds
Started Sep 11 01:48:42 PM UTC 24
Finished Sep 11 02:03:45 PM UTC 24
Peak memory 735576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707841403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1707841403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_error.4085206507
Short name T412
Test name
Test status
Simulation time 547455233 ps
CPU time 20.01 seconds
Started Sep 11 01:48:52 PM UTC 24
Finished Sep 11 01:49:13 PM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085206507 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4085206507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_long_msg.2113682524
Short name T426
Test name
Test status
Simulation time 21523070943 ps
CPU time 85.73 seconds
Started Sep 11 01:48:41 PM UTC 24
Finished Sep 11 01:50:09 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113682524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2113682524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_smoke.1431521069
Short name T406
Test name
Test status
Simulation time 2350476845 ps
CPU time 13.87 seconds
Started Sep 11 01:48:26 PM UTC 24
Finished Sep 11 01:48:42 PM UTC 24
Peak memory 207512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431521069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1431521069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_stress_all.143972898
Short name T528
Test name
Test status
Simulation time 80545094426 ps
CPU time 1712.88 seconds
Started Sep 11 01:49:10 PM UTC 24
Finished Sep 11 02:18:01 PM UTC 24
Peak memory 739620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143972898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.143972898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.2785094328
Short name T417
Test name
Test status
Simulation time 6514360124 ps
CPU time 31.39 seconds
Started Sep 11 01:48:54 PM UTC 24
Finished Sep 11 01:49:26 PM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785094328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2785094328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_alert_test.2168653674
Short name T421
Test name
Test status
Simulation time 94471592 ps
CPU time 0.77 seconds
Started Sep 11 01:49:40 PM UTC 24
Finished Sep 11 01:49:41 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168653674 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2168653674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.24949513
Short name T428
Test name
Test status
Simulation time 1270889256 ps
CPU time 76.23 seconds
Started Sep 11 01:49:16 PM UTC 24
Finished Sep 11 01:50:34 PM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24949513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.24949513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.281306848
Short name T425
Test name
Test status
Simulation time 2452228539 ps
CPU time 35.89 seconds
Started Sep 11 01:49:27 PM UTC 24
Finished Sep 11 01:50:05 PM UTC 24
Peak memory 207488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281306848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.281306848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.2275631092
Short name T504
Test name
Test status
Simulation time 9731628001 ps
CPU time 717.64 seconds
Started Sep 11 01:49:17 PM UTC 24
Finished Sep 11 02:01:22 PM UTC 24
Peak memory 719136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275631092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2275631092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_error.3267887843
Short name T447
Test name
Test status
Simulation time 8243520372 ps
CPU time 166.02 seconds
Started Sep 11 01:49:27 PM UTC 24
Finished Sep 11 01:52:16 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267887843 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3267887843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2883311886
Short name T427
Test name
Test status
Simulation time 943743076 ps
CPU time 63.83 seconds
Started Sep 11 01:49:16 PM UTC 24
Finished Sep 11 01:50:21 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883311886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2883311886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_smoke.2210636372
Short name T419
Test name
Test status
Simulation time 4977410730 ps
CPU time 20.25 seconds
Started Sep 11 01:49:14 PM UTC 24
Finished Sep 11 01:49:36 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210636372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2210636372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_stress_all.2525178765
Short name T527
Test name
Test status
Simulation time 27904471440 ps
CPU time 1644.3 seconds
Started Sep 11 01:49:40 PM UTC 24
Finished Sep 11 02:17:21 PM UTC 24
Peak memory 764128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525178765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2525178765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.1492259671
Short name T430
Test name
Test status
Simulation time 5497049153 ps
CPU time 63.46 seconds
Started Sep 11 01:49:32 PM UTC 24
Finished Sep 11 01:50:37 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492259671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1492259671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_alert_test.166957341
Short name T431
Test name
Test status
Simulation time 38037692 ps
CPU time 0.8 seconds
Started Sep 11 01:50:38 PM UTC 24
Finished Sep 11 01:50:39 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166957341 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.166957341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.2150730804
Short name T438
Test name
Test status
Simulation time 7765076104 ps
CPU time 97 seconds
Started Sep 11 01:50:00 PM UTC 24
Finished Sep 11 01:51:39 PM UTC 24
Peak memory 223696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150730804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2150730804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.2504721827
Short name T433
Test name
Test status
Simulation time 3936939374 ps
CPU time 49.56 seconds
Started Sep 11 01:50:05 PM UTC 24
Finished Sep 11 01:50:57 PM UTC 24
Peak memory 207324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504721827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2504721827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.629630437
Short name T510
Test name
Test status
Simulation time 10318271983 ps
CPU time 817.45 seconds
Started Sep 11 01:50:04 PM UTC 24
Finished Sep 11 02:03:51 PM UTC 24
Peak memory 696536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629630437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.629630437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_error.3883051644
Short name T439
Test name
Test status
Simulation time 2589865929 ps
CPU time 89.96 seconds
Started Sep 11 01:50:10 PM UTC 24
Finished Sep 11 01:51:42 PM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883051644 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3883051644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_long_msg.3608114861
Short name T436
Test name
Test status
Simulation time 4367784573 ps
CPU time 95.21 seconds
Started Sep 11 01:49:51 PM UTC 24
Finished Sep 11 01:51:29 PM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608114861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3608114861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_smoke.397179636
Short name T424
Test name
Test status
Simulation time 1119962806 ps
CPU time 18.41 seconds
Started Sep 11 01:49:43 PM UTC 24
Finished Sep 11 01:50:03 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397179636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.397179636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_stress_all.530476214
Short name T459
Test name
Test status
Simulation time 2698919987 ps
CPU time 168.69 seconds
Started Sep 11 01:50:35 PM UTC 24
Finished Sep 11 01:53:27 PM UTC 24
Peak memory 207228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530476214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.530476214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.3358332279
Short name T112
Test name
Test status
Simulation time 7247896820 ps
CPU time 108.26 seconds
Started Sep 11 01:50:22 PM UTC 24
Finished Sep 11 01:52:13 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358332279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3358332279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2582127909
Short name T437
Test name
Test status
Simulation time 14296495 ps
CPU time 0.88 seconds
Started Sep 11 01:51:33 PM UTC 24
Finished Sep 11 01:51:35 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582127909 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2582127909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.3291275026
Short name T449
Test name
Test status
Simulation time 5450041831 ps
CPU time 99.06 seconds
Started Sep 11 01:50:40 PM UTC 24
Finished Sep 11 01:52:21 PM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291275026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3291275026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.3328484460
Short name T443
Test name
Test status
Simulation time 2353728191 ps
CPU time 68.74 seconds
Started Sep 11 01:50:57 PM UTC 24
Finished Sep 11 01:52:08 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328484460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3328484460
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.482289004
Short name T523
Test name
Test status
Simulation time 42775519190 ps
CPU time 1469.47 seconds
Started Sep 11 01:50:45 PM UTC 24
Finished Sep 11 02:15:31 PM UTC 24
Peak memory 782812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482289004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.482289004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_error.569971473
Short name T472
Test name
Test status
Simulation time 21274413948 ps
CPU time 187.04 seconds
Started Sep 11 01:51:11 PM UTC 24
Finished Sep 11 01:54:21 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569971473 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.569971473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_long_msg.966714919
Short name T435
Test name
Test status
Simulation time 18434629579 ps
CPU time 41.59 seconds
Started Sep 11 01:50:40 PM UTC 24
Finished Sep 11 01:51:23 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966714919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.966714919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_smoke.3050534710
Short name T432
Test name
Test status
Simulation time 616632369 ps
CPU time 3.47 seconds
Started Sep 11 01:50:40 PM UTC 24
Finished Sep 11 01:50:44 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050534710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3050534710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_stress_all.2918842431
Short name T511
Test name
Test status
Simulation time 13147759304 ps
CPU time 790.48 seconds
Started Sep 11 01:51:24 PM UTC 24
Finished Sep 11 02:04:43 PM UTC 24
Peak memory 756060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918842431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2918842431
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.1091540296
Short name T458
Test name
Test status
Simulation time 12720826338 ps
CPU time 126.96 seconds
Started Sep 11 01:51:13 PM UTC 24
Finished Sep 11 01:53:23 PM UTC 24
Peak memory 207324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091540296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1091540296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_alert_test.2367545284
Short name T446
Test name
Test status
Simulation time 21429658 ps
CPU time 0.9 seconds
Started Sep 11 01:52:09 PM UTC 24
Finished Sep 11 01:52:11 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367545284 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2367545284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.941075274
Short name T456
Test name
Test status
Simulation time 1317672778 ps
CPU time 76.19 seconds
Started Sep 11 01:51:41 PM UTC 24
Finished Sep 11 01:52:59 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941075274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.941075274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.3963158832
Short name T451
Test name
Test status
Simulation time 14715269972 ps
CPU time 47.3 seconds
Started Sep 11 01:51:47 PM UTC 24
Finished Sep 11 01:52:36 PM UTC 24
Peak memory 215684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963158832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3963158832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.3384470700
Short name T470
Test name
Test status
Simulation time 6382132208 ps
CPU time 150.44 seconds
Started Sep 11 01:51:43 PM UTC 24
Finished Sep 11 01:54:17 PM UTC 24
Peak memory 422108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384470700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3384470700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_error.2928505175
Short name T488
Test name
Test status
Simulation time 38941042480 ps
CPU time 225.3 seconds
Started Sep 11 01:51:51 PM UTC 24
Finished Sep 11 01:55:40 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928505175 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2928505175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_long_msg.877878908
Short name T462
Test name
Test status
Simulation time 9519328290 ps
CPU time 127.28 seconds
Started Sep 11 01:51:36 PM UTC 24
Finished Sep 11 01:53:46 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877878908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.877878908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_smoke.33941478
Short name T441
Test name
Test status
Simulation time 1793192661 ps
CPU time 17.48 seconds
Started Sep 11 01:51:33 PM UTC 24
Finished Sep 11 01:51:51 PM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33941478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.hmac_smoke.33941478
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_stress_all.3197742217
Short name T40
Test name
Test status
Simulation time 50529527957 ps
CPU time 3405.43 seconds
Started Sep 11 01:52:09 PM UTC 24
Finished Sep 11 02:49:31 PM UTC 24
Peak memory 839796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197742217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3197742217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.1301740444
Short name T477
Test name
Test status
Simulation time 16211143325 ps
CPU time 166.52 seconds
Started Sep 11 01:51:52 PM UTC 24
Finished Sep 11 01:54:41 PM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301740444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1301740444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_alert_test.2797961009
Short name T452
Test name
Test status
Simulation time 18329492 ps
CPU time 0.89 seconds
Started Sep 11 01:52:38 PM UTC 24
Finished Sep 11 01:52:40 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797961009 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2797961009
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.2677682353
Short name T48
Test name
Test status
Simulation time 1620714536 ps
CPU time 95.03 seconds
Started Sep 11 01:52:14 PM UTC 24
Finished Sep 11 01:53:52 PM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677682353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2677682353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.256796335
Short name T455
Test name
Test status
Simulation time 579821356 ps
CPU time 39.05 seconds
Started Sep 11 01:52:18 PM UTC 24
Finished Sep 11 01:52:59 PM UTC 24
Peak memory 207220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256796335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.256796335
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.162294009
Short name T474
Test name
Test status
Simulation time 1381443427 ps
CPU time 131.37 seconds
Started Sep 11 01:52:16 PM UTC 24
Finished Sep 11 01:54:30 PM UTC 24
Peak memory 393376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162294009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.162294009
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_error.2208760482
Short name T476
Test name
Test status
Simulation time 11589305150 ps
CPU time 138.34 seconds
Started Sep 11 01:52:18 PM UTC 24
Finished Sep 11 01:54:39 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208760482 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2208760482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_long_msg.1293631101
Short name T467
Test name
Test status
Simulation time 5838817070 ps
CPU time 101.36 seconds
Started Sep 11 01:52:14 PM UTC 24
Finished Sep 11 01:53:58 PM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293631101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1293631101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_smoke.1895185724
Short name T448
Test name
Test status
Simulation time 181513358 ps
CPU time 4.42 seconds
Started Sep 11 01:52:11 PM UTC 24
Finished Sep 11 01:52:17 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895185724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1895185724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_stress_all.1940201144
Short name T93
Test name
Test status
Simulation time 88009167704 ps
CPU time 2807.74 seconds
Started Sep 11 01:52:37 PM UTC 24
Finished Sep 11 02:39:56 PM UTC 24
Peak memory 815292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940201144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1940201144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.796247249
Short name T453
Test name
Test status
Simulation time 478187339 ps
CPU time 30.49 seconds
Started Sep 11 01:52:23 PM UTC 24
Finished Sep 11 01:52:55 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796247249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.796247249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_alert_test.3171026183
Short name T461
Test name
Test status
Simulation time 13284524 ps
CPU time 0.89 seconds
Started Sep 11 01:53:32 PM UTC 24
Finished Sep 11 01:53:34 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171026183 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3171026183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.2468152531
Short name T36
Test name
Test status
Simulation time 1661488587 ps
CPU time 103.44 seconds
Started Sep 11 01:52:58 PM UTC 24
Finished Sep 11 01:54:43 PM UTC 24
Peak memory 207436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468152531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2468152531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.3502998477
Short name T483
Test name
Test status
Simulation time 11491874404 ps
CPU time 108.28 seconds
Started Sep 11 01:53:00 PM UTC 24
Finished Sep 11 01:54:51 PM UTC 24
Peak memory 223612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502998477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3502998477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2593473372
Short name T499
Test name
Test status
Simulation time 3638949726 ps
CPU time 315.58 seconds
Started Sep 11 01:53:00 PM UTC 24
Finished Sep 11 01:58:20 PM UTC 24
Peak memory 465164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593473372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2593473372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_error.1707569570
Short name T485
Test name
Test status
Simulation time 8622985989 ps
CPU time 130.56 seconds
Started Sep 11 01:53:07 PM UTC 24
Finished Sep 11 01:55:20 PM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707569570 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1707569570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_long_msg.1158349363
Short name T463
Test name
Test status
Simulation time 3725700207 ps
CPU time 51.04 seconds
Started Sep 11 01:52:56 PM UTC 24
Finished Sep 11 01:53:49 PM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158349363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1158349363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_smoke.1286900049
Short name T454
Test name
Test status
Simulation time 1084675878 ps
CPU time 14.16 seconds
Started Sep 11 01:52:41 PM UTC 24
Finished Sep 11 01:52:56 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286900049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1286900049
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2703084760
Short name T473
Test name
Test status
Simulation time 3532745369 ps
CPU time 54.18 seconds
Started Sep 11 01:53:29 PM UTC 24
Finished Sep 11 01:54:25 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703084760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2703084760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.108808001
Short name T466
Test name
Test status
Simulation time 3057984904 ps
CPU time 31.27 seconds
Started Sep 11 01:53:24 PM UTC 24
Finished Sep 11 01:53:57 PM UTC 24
Peak memory 207320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108808001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.108808001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_alert_test.3890360597
Short name T469
Test name
Test status
Simulation time 15384779 ps
CPU time 0.87 seconds
Started Sep 11 01:54:00 PM UTC 24
Finished Sep 11 01:54:02 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890360597 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3890360597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.2403595676
Short name T484
Test name
Test status
Simulation time 1060686600 ps
CPU time 77.52 seconds
Started Sep 11 01:53:50 PM UTC 24
Finished Sep 11 01:55:10 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403595676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2403595676
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.691275607
Short name T481
Test name
Test status
Simulation time 16612675638 ps
CPU time 51.98 seconds
Started Sep 11 01:53:57 PM UTC 24
Finished Sep 11 01:54:50 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691275607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.691275607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.221484918
Short name T475
Test name
Test status
Simulation time 330872019 ps
CPU time 40.21 seconds
Started Sep 11 01:53:57 PM UTC 24
Finished Sep 11 01:54:38 PM UTC 24
Peak memory 345292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221484918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.221484918
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_error.4239009576
Short name T486
Test name
Test status
Simulation time 3705629981 ps
CPU time 81.83 seconds
Started Sep 11 01:53:57 PM UTC 24
Finished Sep 11 01:55:21 PM UTC 24
Peak memory 207436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239009576 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.4239009576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_long_msg.3240944591
Short name T496
Test name
Test status
Simulation time 3435455063 ps
CPU time 232.79 seconds
Started Sep 11 01:53:47 PM UTC 24
Finished Sep 11 01:57:43 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240944591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3240944591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_smoke.2582833841
Short name T468
Test name
Test status
Simulation time 1349553129 ps
CPU time 22.36 seconds
Started Sep 11 01:53:35 PM UTC 24
Finished Sep 11 01:53:59 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582833841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2582833841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_stress_all.2952653707
Short name T94
Test name
Test status
Simulation time 128626807470 ps
CPU time 3616.74 seconds
Started Sep 11 01:54:00 PM UTC 24
Finished Sep 11 02:54:58 PM UTC 24
Peak memory 788664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952653707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2952653707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.2958581874
Short name T480
Test name
Test status
Simulation time 3190698339 ps
CPU time 48.06 seconds
Started Sep 11 01:53:58 PM UTC 24
Finished Sep 11 01:54:48 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958581874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2958581874
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_alert_test.617959258
Short name T479
Test name
Test status
Simulation time 75043352 ps
CPU time 0.9 seconds
Started Sep 11 01:54:43 PM UTC 24
Finished Sep 11 01:54:46 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617959258 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.617959258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.1403101178
Short name T490
Test name
Test status
Simulation time 2742357639 ps
CPU time 96.56 seconds
Started Sep 11 01:54:18 PM UTC 24
Finished Sep 11 01:55:57 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403101178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1403101178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.4158120531
Short name T478
Test name
Test status
Simulation time 3012666653 ps
CPU time 17.83 seconds
Started Sep 11 01:54:26 PM UTC 24
Finished Sep 11 01:54:46 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158120531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4158120531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.3523770687
Short name T492
Test name
Test status
Simulation time 5459835072 ps
CPU time 136.72 seconds
Started Sep 11 01:54:23 PM UTC 24
Finished Sep 11 01:56:42 PM UTC 24
Peak memory 633056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523770687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3523770687
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_error.3711580442
Short name T489
Test name
Test status
Simulation time 4320174437 ps
CPU time 80.72 seconds
Started Sep 11 01:54:31 PM UTC 24
Finished Sep 11 01:55:54 PM UTC 24
Peak memory 207372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711580442 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3711580442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_long_msg.1018604033
Short name T497
Test name
Test status
Simulation time 63828974463 ps
CPU time 213.51 seconds
Started Sep 11 01:54:18 PM UTC 24
Finished Sep 11 01:57:55 PM UTC 24
Peak memory 215956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018604033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1018604033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_smoke.1811571525
Short name T471
Test name
Test status
Simulation time 2824353258 ps
CPU time 13.21 seconds
Started Sep 11 01:54:03 PM UTC 24
Finished Sep 11 01:54:17 PM UTC 24
Peak memory 207324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811571525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1811571525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2971559641
Short name T534
Test name
Test status
Simulation time 139515923863 ps
CPU time 1921.88 seconds
Started Sep 11 01:54:40 PM UTC 24
Finished Sep 11 02:27:02 PM UTC 24
Peak memory 756012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971559641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2971559641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.2979763318
Short name T491
Test name
Test status
Simulation time 22955573577 ps
CPU time 112.96 seconds
Started Sep 11 01:54:39 PM UTC 24
Finished Sep 11 01:56:35 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979763318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2979763318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_alert_test.977344087
Short name T186
Test name
Test status
Simulation time 35472699 ps
CPU time 0.9 seconds
Started Sep 11 01:32:02 PM UTC 24
Finished Sep 11 01:32:04 PM UTC 24
Peak memory 203656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977344087 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.977344087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.1083974729
Short name T17
Test name
Test status
Simulation time 1412936403 ps
CPU time 48.54 seconds
Started Sep 11 01:31:46 PM UTC 24
Finished Sep 11 01:32:36 PM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083974729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1083974729
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.306513847
Short name T41
Test name
Test status
Simulation time 4648414944 ps
CPU time 26.93 seconds
Started Sep 11 01:31:52 PM UTC 24
Finished Sep 11 01:32:20 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306513847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.306513847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.28150379
Short name T143
Test name
Test status
Simulation time 452217916 ps
CPU time 10.34 seconds
Started Sep 11 01:31:48 PM UTC 24
Finished Sep 11 01:32:00 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28150379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.28150379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_error.1789593872
Short name T157
Test name
Test status
Simulation time 3244285692 ps
CPU time 204.04 seconds
Started Sep 11 01:31:55 PM UTC 24
Finished Sep 11 01:35:23 PM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789593872 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1789593872
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_long_msg.644385258
Short name T165
Test name
Test status
Simulation time 15956244395 ps
CPU time 82.69 seconds
Started Sep 11 01:31:43 PM UTC 24
Finished Sep 11 01:33:08 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644385258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.644385258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_smoke.1231850559
Short name T13
Test name
Test status
Simulation time 1647401979 ps
CPU time 18.02 seconds
Started Sep 11 01:31:42 PM UTC 24
Finished Sep 11 01:32:02 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231850559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1231850559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3572751121
Short name T91
Test name
Test status
Simulation time 240423751304 ps
CPU time 1129.72 seconds
Started Sep 11 01:32:01 PM UTC 24
Finished Sep 11 01:51:04 PM UTC 24
Peak memory 708892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572751121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3572751121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.956529893
Short name T137
Test name
Test status
Simulation time 4340587561 ps
CPU time 65.29 seconds
Started Sep 11 01:31:59 PM UTC 24
Finished Sep 11 01:33:07 PM UTC 24
Peak memory 207308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956529893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.956529893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_alert_test.813447809
Short name T44
Test name
Test status
Simulation time 13468538 ps
CPU time 0.88 seconds
Started Sep 11 01:32:22 PM UTC 24
Finished Sep 11 01:32:24 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813447809 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.813447809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.3295743338
Short name T163
Test name
Test status
Simulation time 4400509495 ps
CPU time 57.52 seconds
Started Sep 11 01:32:06 PM UTC 24
Finished Sep 11 01:33:06 PM UTC 24
Peak memory 215680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295743338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3295743338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.90008215
Short name T166
Test name
Test status
Simulation time 10804099909 ps
CPU time 76.88 seconds
Started Sep 11 01:32:15 PM UTC 24
Finished Sep 11 01:33:34 PM UTC 24
Peak memory 215740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90008215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.90008215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.879801845
Short name T42
Test name
Test status
Simulation time 332063164 ps
CPU time 11.4 seconds
Started Sep 11 01:32:08 PM UTC 24
Finished Sep 11 01:32:20 PM UTC 24
Peak memory 207028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879801845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.879801845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_error.2247883385
Short name T231
Test name
Test status
Simulation time 3336018862 ps
CPU time 218.84 seconds
Started Sep 11 01:32:15 PM UTC 24
Finished Sep 11 01:35:57 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247883385 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2247883385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_long_msg.1429968785
Short name T182
Test name
Test status
Simulation time 4887704021 ps
CPU time 50.33 seconds
Started Sep 11 01:32:06 PM UTC 24
Finished Sep 11 01:32:58 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429968785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1429968785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_smoke.3466332118
Short name T136
Test name
Test status
Simulation time 590516528 ps
CPU time 9.34 seconds
Started Sep 11 01:32:06 PM UTC 24
Finished Sep 11 01:32:17 PM UTC 24
Peak memory 207384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466332118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3466332118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_stress_all.4282853168
Short name T501
Test name
Test status
Simulation time 20478553175 ps
CPU time 1621.12 seconds
Started Sep 11 01:32:18 PM UTC 24
Finished Sep 11 01:59:37 PM UTC 24
Peak memory 755932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282853168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4282853168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.1112940726
Short name T191
Test name
Test status
Simulation time 2329017425 ps
CPU time 49.61 seconds
Started Sep 11 01:32:16 PM UTC 24
Finished Sep 11 01:33:08 PM UTC 24
Peak memory 207508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112940726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1112940726
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_alert_test.3917291245
Short name T51
Test name
Test status
Simulation time 131626590 ps
CPU time 0.84 seconds
Started Sep 11 01:32:41 PM UTC 24
Finished Sep 11 01:32:43 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917291245 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3917291245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.1671728586
Short name T18
Test name
Test status
Simulation time 1477451170 ps
CPU time 88.28 seconds
Started Sep 11 01:32:25 PM UTC 24
Finished Sep 11 01:33:55 PM UTC 24
Peak memory 223640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671728586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1671728586
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.319605207
Short name T53
Test name
Test status
Simulation time 2103713851 ps
CPU time 13.3 seconds
Started Sep 11 01:32:33 PM UTC 24
Finished Sep 11 01:32:47 PM UTC 24
Peak memory 207376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319605207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.319605207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.302962061
Short name T283
Test name
Test status
Simulation time 2347126440 ps
CPU time 387.17 seconds
Started Sep 11 01:32:29 PM UTC 24
Finished Sep 11 01:39:01 PM UTC 24
Peak memory 715232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302962061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.302962061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_error.77388671
Short name T62
Test name
Test status
Simulation time 1965095579 ps
CPU time 25.76 seconds
Started Sep 11 01:32:37 PM UTC 24
Finished Sep 11 01:33:04 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77388671 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.77388671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_long_msg.672423952
Short name T224
Test name
Test status
Simulation time 95857206296 ps
CPU time 193.68 seconds
Started Sep 11 01:32:25 PM UTC 24
Finished Sep 11 01:35:42 PM UTC 24
Peak memory 215944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672423952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.672423952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_smoke.3308817473
Short name T47
Test name
Test status
Simulation time 1546699596 ps
CPU time 15.65 seconds
Started Sep 11 01:32:22 PM UTC 24
Finished Sep 11 01:32:38 PM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308817473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3308817473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_stress_all.4150474214
Short name T517
Test name
Test status
Simulation time 327865381639 ps
CPU time 2107.37 seconds
Started Sep 11 01:32:39 PM UTC 24
Finished Sep 11 02:08:09 PM UTC 24
Peak memory 807072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150474214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.4150474214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.2695958912
Short name T31
Test name
Test status
Simulation time 15071651449 ps
CPU time 44.73 seconds
Started Sep 11 01:32:39 PM UTC 24
Finished Sep 11 01:33:25 PM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695958912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2695958912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1341249047
Short name T190
Test name
Test status
Simulation time 45888691 ps
CPU time 0.76 seconds
Started Sep 11 01:33:04 PM UTC 24
Finished Sep 11 01:33:06 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341249047 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1341249047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.2801639151
Short name T2
Test name
Test status
Simulation time 779247522 ps
CPU time 38.85 seconds
Started Sep 11 01:32:47 PM UTC 24
Finished Sep 11 01:33:27 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801639151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2801639151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.2298236421
Short name T192
Test name
Test status
Simulation time 851179387 ps
CPU time 16.31 seconds
Started Sep 11 01:32:53 PM UTC 24
Finished Sep 11 01:33:11 PM UTC 24
Peak memory 207424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298236421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2298236421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.4006049725
Short name T399
Test name
Test status
Simulation time 5731364084 ps
CPU time 916.7 seconds
Started Sep 11 01:32:48 PM UTC 24
Finished Sep 11 01:48:15 PM UTC 24
Peak memory 700636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006049725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4006049725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_error.3546592334
Short name T60
Test name
Test status
Simulation time 13990723606 ps
CPU time 104.45 seconds
Started Sep 11 01:32:55 PM UTC 24
Finished Sep 11 01:34:42 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546592334 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3546592334
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_long_msg.161051856
Short name T212
Test name
Test status
Simulation time 7846876342 ps
CPU time 130.54 seconds
Started Sep 11 01:32:43 PM UTC 24
Finished Sep 11 01:34:56 PM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161051856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.161051856
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_smoke.1231624198
Short name T54
Test name
Test status
Simulation time 1719836590 ps
CPU time 7.54 seconds
Started Sep 11 01:32:43 PM UTC 24
Finished Sep 11 01:32:52 PM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231624198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1231624198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_stress_all.3647584486
Short name T516
Test name
Test status
Simulation time 56048156359 ps
CPU time 2076 seconds
Started Sep 11 01:32:56 PM UTC 24
Finished Sep 11 02:07:56 PM UTC 24
Peak memory 774436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647584486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3647584486
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.517042053
Short name T188
Test name
Test status
Simulation time 964407358 ps
CPU time 6.87 seconds
Started Sep 11 01:32:55 PM UTC 24
Finished Sep 11 01:33:03 PM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517042053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.517042053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_alert_test.61074471
Short name T194
Test name
Test status
Simulation time 14474867 ps
CPU time 0.95 seconds
Started Sep 11 01:33:11 PM UTC 24
Finished Sep 11 01:33:13 PM UTC 24
Peak memory 203596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61074471 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.61074471
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.616028324
Short name T205
Test name
Test status
Simulation time 774232578 ps
CPU time 41.55 seconds
Started Sep 11 01:33:07 PM UTC 24
Finished Sep 11 01:33:50 PM UTC 24
Peak memory 207024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616028324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.616028324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.3418526411
Short name T202
Test name
Test status
Simulation time 1732958137 ps
CPU time 33.14 seconds
Started Sep 11 01:33:10 PM UTC 24
Finished Sep 11 01:33:45 PM UTC 24
Peak memory 207368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418526411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3418526411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.2740526075
Short name T201
Test name
Test status
Simulation time 2106426267 ps
CPU time 32.1 seconds
Started Sep 11 01:33:07 PM UTC 24
Finished Sep 11 01:33:41 PM UTC 24
Peak memory 334988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740526075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2740526075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_error.3350312472
Short name T243
Test name
Test status
Simulation time 24821506048 ps
CPU time 186.71 seconds
Started Sep 11 01:33:10 PM UTC 24
Finished Sep 11 01:36:20 PM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350312472 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3350312472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_long_msg.3456992183
Short name T195
Test name
Test status
Simulation time 953303924 ps
CPU time 7.68 seconds
Started Sep 11 01:33:06 PM UTC 24
Finished Sep 11 01:33:14 PM UTC 24
Peak memory 207388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456992183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3456992183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_smoke.1473502881
Short name T15
Test name
Test status
Simulation time 3229233711 ps
CPU time 11.19 seconds
Started Sep 11 01:33:04 PM UTC 24
Finished Sep 11 01:33:17 PM UTC 24
Peak memory 207500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473502881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1473502881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_stress_all.395088605
Short name T348
Test name
Test status
Simulation time 35435056466 ps
CPU time 621.43 seconds
Started Sep 11 01:33:10 PM UTC 24
Finished Sep 11 01:43:39 PM UTC 24
Peak memory 215748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_10/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395088605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.395088605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1855595958
Short name T138
Test name
Test status
Simulation time 26282472046 ps
CPU time 92.96 seconds
Started Sep 11 01:33:10 PM UTC 24
Finished Sep 11 01:34:45 PM UTC 24
Peak memory 207300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855595958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1855595958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/hmac-sim-vcs/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%