Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15897977	1			T1	20770		T4	137		T5	1933
all_values[1]	15897977	1			T1	20770		T4	137		T5	1933
all_values[2]	15897977	1			T1	20770		T4	137		T5	1933

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221834

1

T23

2775

T7

22

T9

1978

auto[1]

47472097

1

T1

62310

T4

411

T5

5799

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40838767

1

T1

51924

T4

308

T5

5115

auto[1]

6855164

1

T1

10386

T4

103

T5

684

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	91749	1			T56	3430		T16	254		T34	863
all_values[0]	auto[0]	auto[1]	344	1			T34	2		T44	2		T142	2
all_values[0]	auto[1]	auto[0]	15787741	1			T1	20545		T4	136		T5	1907
all_values[0]	auto[1]	auto[1]	18143	1			T1	225		T4	1		T5	26
all_values[1]	auto[0]	auto[0]	73752	1			T23	2775		T7	22		T9	989
all_values[1]	auto[0]	auto[1]	169	1			T34	1		T63	7		T78	1
all_values[1]	auto[1]	auto[0]	15823787	1			T1	20770		T4	137		T5	1933
all_values[1]	auto[1]	auto[1]	269	1			T17	2		T29	5		T63	4
all_values[2]	auto[0]	auto[0]	26950	1			T9	248		T141	6		T34	1
all_values[2]	auto[0]	auto[1]	28870	1			T9	741		T141	30		T35	33
all_values[2]	auto[1]	auto[0]	9034788	1			T1	10609		T4	35		T5	1275
all_values[2]	auto[1]	auto[1]	6807369	1			T1	10161		T4	102		T5	658