Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113367

1

T5

28

T23

2

T6

48

auto[1]

115160

1

T1

222

T4

8

T5

28

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	88951	1			T9	6		T8	299		T10	10
len_1026_2046	4648	1			T8	81		T13	2		T12	4
len_514_1022	3078	1			T6	1		T8	16		T10	2
len_2_510	3871	1			T5	3		T6	1		T7	2
len_2056	148	1			T6	2		T12	4		T19	3
len_2048	327	1			T6	1		T8	1		T12	2
len_2040	155	1			T5	3		T6	3		T34	2
len_1032	118	1			T5	7		T6	3		T7	2
len_1024	1829	1			T1	111		T5	4		T6	2
len_1016	202	1			T5	1		T6	6		T15	2
len_520	123	1			T12	1		T153	2		T44	7
len_512	359	1			T5	2		T12	4		T14	1
len_504	146	1			T6	1		T7	2		T14	3
len_8	823	1			T154	3		T155	1		T64	4
len_0	9486	1			T4	4		T5	8		T23	3

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

116

1

T10

2

T38

2

T156

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	44977	1			T9	1		T8	53		T10	5
auto[0]	len_1026_2046	2412	1			T8	4		T13	2		T12	3
auto[0]	len_514_1022	1757	1			T6	1		T8	3		T10	2
auto[0]	len_2_510	2808	1			T5	1		T6	1		T7	2
auto[0]	len_2056	78	1			T6	2		T12	1		T19	1
auto[0]	len_2048	181	1			T6	1		T12	2		T24	1
auto[0]	len_2040	90	1			T5	2		T6	2		T44	2
auto[0]	len_1032	71	1			T5	3		T6	3		T7	2
auto[0]	len_1024	257	1			T5	3		T6	2		T10	1
auto[0]	len_1016	128	1			T6	5		T15	2		T12	2
auto[0]	len_520	75	1			T12	1		T153	1		T44	2
auto[0]	len_512	222	1			T12	3		T14	1		T141	3
auto[0]	len_504	92	1			T7	2		T14	3		T44	1
auto[0]	len_8	45	1			T157	2		T158	1		T159	1
auto[0]	len_0	3491	1			T5	5		T23	1		T6	7
auto[1]	len_2050_plus	43974	1			T9	5		T8	246		T10	5
auto[1]	len_1026_2046	2236	1			T8	77		T12	1		T14	4
auto[1]	len_514_1022	1321	1			T8	13		T12	1		T14	2
auto[1]	len_2_510	1063	1			T5	2		T8	12		T12	3
auto[1]	len_2056	70	1			T12	3		T19	2		T35	1
auto[1]	len_2048	146	1			T8	1		T35	2		T17	1
auto[1]	len_2040	65	1			T5	1		T6	1		T34	2
auto[1]	len_1032	47	1			T5	4		T44	1		T160	1
auto[1]	len_1024	1572	1			T1	111		T5	1		T52	60
auto[1]	len_1016	74	1			T5	1		T6	1		T153	1
auto[1]	len_520	48	1			T153	1		T44	5		T161	1
auto[1]	len_512	137	1			T5	2		T12	1		T17	1
auto[1]	len_504	54	1			T6	1		T44	2		T162	1
auto[1]	len_8	778	1			T154	3		T155	1		T64	4
auto[1]	len_0	5995	1			T4	4		T5	3		T23	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

67

1

T10

2

T38

2

T156

2

auto[1]

len_upper

49

1

T45

1

T163

2

T164

1