Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4115313 1 T1 5316 T4 56 T5 506
auto[1] 2329923 1 T4 11 T5 313 T23 1409


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2421326 1 T4 35 T5 412 T23 1410
auto[1] 4023910 1 T1 5316 T4 32 T5 407


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3113647 1 T5 419 T23 1 T6 554
auto[1] 3331589 1 T1 5316 T4 67 T5 400


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4097975 1 T1 5316 T4 54 T5 326
auto[1] 2347261 1 T4 13 T5 493 T23 1410


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 5815905 1 T1 5218 T4 67 T5 724
fifo_depth[1] 112791 1 T1 85 T5 13 T6 7
fifo_depth[2] 86246 1 T1 13 T5 18 T6 2
fifo_depth[3] 67663 1 T5 16 T6 4 T11 1
fifo_depth[4] 60341 1 T5 14 T6 1 T9 1
fifo_depth[5] 46825 1 T5 12 T8 8 T15 19
fifo_depth[6] 37014 1 T5 12 T8 12 T15 24
fifo_depth[7] 24287 1 T5 6 T8 2 T10 1


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 629331 1 T1 98 T5 95 T6 14
auto[1] 5815905 1 T1 5218 T4 67 T5 724


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6438451 1 T1 5316 T4 67 T5 819
auto[1] 6785 1 T17 105 T29 58 T165 50


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 17999 1 T10 2 T30 72 T141 102
auto[0] auto[0] auto[0] auto[0] auto[1] 21130 1 T5 17 T8 24 T12 1
auto[0] auto[0] auto[0] auto[1] auto[0] 32056 1 T6 2 T10 1 T30 238
auto[0] auto[0] auto[0] auto[1] auto[1] 20959 1 T5 6 T15 128 T14 24
auto[0] auto[0] auto[1] auto[0] auto[0] 180276 1 T6 3 T15 75 T14 8
auto[0] auto[0] auto[1] auto[0] auto[1] 29813 1 T8 3 T12 1 T14 25
auto[0] auto[0] auto[1] auto[1] auto[0] 34181 1 T6 1 T8 28 T13 1
auto[0] auto[0] auto[1] auto[1] auto[1] 22428 1 T5 13 T6 4 T11 17
auto[0] auto[1] auto[0] auto[0] auto[0] 35022 1 T5 7 T9 7 T8 18
auto[0] auto[1] auto[0] auto[0] auto[1] 32542 1 T9 15 T132 9 T35 7
auto[0] auto[1] auto[0] auto[1] auto[0] 36539 1 T6 1 T30 183 T31 16
auto[0] auto[1] auto[0] auto[1] auto[1] 36664 1 T12 2 T30 134 T141 256
auto[0] auto[1] auto[1] auto[0] auto[0] 24526 1 T1 98 T5 9 T8 24
auto[0] auto[1] auto[1] auto[0] auto[1] 41280 1 T5 15 T6 3 T9 13
auto[0] auto[1] auto[1] auto[1] auto[0] 35200 1 T5 17 T12 2 T132 4
auto[0] auto[1] auto[1] auto[1] auto[1] 28716 1 T5 11 T8 25 T14 28
auto[1] auto[0] auto[0] auto[0] auto[0] 172365 1 T5 23 T6 1 T7 14
auto[1] auto[0] auto[0] auto[0] auto[1] 148254 1 T5 66 T23 1 T6 113
auto[1] auto[0] auto[0] auto[1] auto[0] 163192 1 T5 17 T6 75 T15 416
auto[1] auto[0] auto[0] auto[1] auto[1] 141872 1 T5 129 T15 325 T12 23
auto[1] auto[0] auto[1] auto[0] auto[0] 1663437 1 T5 47 T6 57 T13 1
auto[1] auto[0] auto[1] auto[0] auto[1] 166805 1 T5 47 T6 142 T8 34
auto[1] auto[0] auto[1] auto[1] auto[0] 152985 1 T5 25 T6 65 T8 83
auto[1] auto[0] auto[1] auto[1] auto[1] 145895 1 T5 29 T6 91 T7 12
auto[1] auto[1] auto[0] auto[0] auto[0] 401073 1 T4 23 T5 109 T6 25
auto[1] auto[1] auto[0] auto[0] auto[1] 391454 1 T4 1 T5 11 T6 73
auto[1] auto[1] auto[0] auto[1] auto[0] 372631 1 T4 10 T6 89 T9 360
auto[1] auto[1] auto[0] auto[1] auto[1] 397574 1 T4 1 T5 27 T23 1409
auto[1] auto[1] auto[1] auto[0] auto[0] 395054 1 T1 5218 T4 21 T5 53
auto[1] auto[1] auto[1] auto[0] auto[1] 394283 1 T4 11 T5 102 T6 49
auto[1] auto[1] auto[1] auto[1] auto[0] 381439 1 T5 19 T6 52 T11 1
auto[1] auto[1] auto[1] auto[1] auto[1] 327592 1 T5 20 T6 1 T8 605


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 190141 1 T5 23 T6 1 T7 14
auto[0] auto[0] auto[0] auto[0] auto[1] 168689 1 T5 83 T23 1 T6 113
auto[0] auto[0] auto[0] auto[1] auto[0] 194511 1 T5 17 T6 77 T10 1
auto[0] auto[0] auto[0] auto[1] auto[1] 162265 1 T5 135 T15 453 T12 23
auto[0] auto[0] auto[1] auto[0] auto[0] 1843356 1 T5 47 T6 60 T13 1
auto[0] auto[0] auto[1] auto[0] auto[1] 195806 1 T5 47 T6 142 T8 37
auto[0] auto[0] auto[1] auto[1] auto[0] 186057 1 T5 25 T6 66 T8 111
auto[0] auto[0] auto[1] auto[1] auto[1] 167946 1 T5 42 T6 95 T7 12
auto[0] auto[1] auto[0] auto[0] auto[0] 435998 1 T4 23 T5 116 T6 25
auto[0] auto[1] auto[0] auto[0] auto[1] 423567 1 T4 1 T5 11 T6 73
auto[0] auto[1] auto[0] auto[1] auto[0] 408751 1 T4 10 T6 90 T9 360
auto[0] auto[1] auto[0] auto[1] auto[1] 433904 1 T4 1 T5 27 T23 1409
auto[0] auto[1] auto[1] auto[0] auto[0] 419449 1 T1 5316 T4 21 T5 62
auto[0] auto[1] auto[1] auto[0] auto[1] 435395 1 T4 11 T5 117 T6 52
auto[0] auto[1] auto[1] auto[1] auto[0] 416506 1 T5 36 T6 52 T11 1
auto[0] auto[1] auto[1] auto[1] auto[1] 356110 1 T5 31 T6 1 T8 630
auto[1] auto[0] auto[0] auto[0] auto[0] 223 1 T17 1 T64 8 T167 5
auto[1] auto[0] auto[0] auto[0] auto[1] 695 1 T168 10 T167 43 T169 510
auto[1] auto[0] auto[0] auto[1] auto[0] 737 1 T17 34 T29 28 T168 13
auto[1] auto[0] auto[0] auto[1] auto[1] 566 1 T170 26 T168 15 T171 87
auto[1] auto[0] auto[1] auto[0] auto[0] 357 1 T172 28 T168 1 T74 1
auto[1] auto[0] auto[1] auto[0] auto[1] 812 1 T17 13 T29 1 T165 1
auto[1] auto[0] auto[1] auto[1] auto[0] 1109 1 T17 10 T165 29 T168 12
auto[1] auto[0] auto[1] auto[1] auto[1] 377 1 T29 6 T172 61 T168 49
auto[1] auto[1] auto[0] auto[0] auto[0] 97 1 T165 10 T173 10 T108 16
auto[1] auto[1] auto[0] auto[0] auto[1] 429 1 T174 2 T172 1 T170 25
auto[1] auto[1] auto[0] auto[1] auto[0] 419 1 T17 17 T172 108 T170 1
auto[1] auto[1] auto[0] auto[1] auto[1] 334 1 T169 24 T175 6 T176 4
auto[1] auto[1] auto[1] auto[0] auto[0] 131 1 T29 22 T167 13 T173 57
auto[1] auto[1] auto[1] auto[0] auto[1] 168 1 T29 1 T170 6 T167 4
auto[1] auto[1] auto[1] auto[1] auto[0] 133 1 T168 61 T171 6 T167 37
auto[1] auto[1] auto[1] auto[1] auto[1] 198 1 T17 30 T165 10 T168 48


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 172365 1 T5 23 T6 1 T7 14
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 148254 1 T5 66 T23 1 T6 113
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 163192 1 T5 17 T6 75 T15 416
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 141872 1 T5 129 T15 325 T12 23
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1663437 1 T5 47 T6 57 T13 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 166805 1 T5 47 T6 142 T8 34
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 152985 1 T5 25 T6 65 T8 83
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 145895 1 T5 29 T6 91 T7 12
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 401073 1 T4 23 T5 109 T6 25
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 391454 1 T4 1 T5 11 T6 73
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 372631 1 T4 10 T6 89 T9 360
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 397574 1 T4 1 T5 27 T23 1409
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 395054 1 T1 5218 T4 21 T5 53
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 394283 1 T4 11 T5 102 T6 49
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 381439 1 T5 19 T6 52 T11 1
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 327592 1 T5 20 T6 1 T8 605
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3242 1 T10 1 T30 9 T141 4
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 2823 1 T5 4 T8 6 T12 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3343 1 T30 42 T141 2 T31 30
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 2867 1 T5 1 T15 24 T14 12
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 47824 1 T6 2 T15 10 T30 41
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3416 1 T12 1 T14 6 T30 14
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3408 1 T8 6 T12 2 T31 8
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 2956 1 T6 2 T11 15 T12 2
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 5372 1 T9 4 T12 3 T141 16
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 4844 1 T9 9 T132 7 T35 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5321 1 T30 28 T31 7 T34 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5578 1 T12 2 T30 26 T141 107
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 5289 1 T1 85 T5 2 T52 138
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6731 1 T5 2 T6 3 T9 11
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5478 1 T5 1 T12 1 T132 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 4299 1 T5 3 T8 18 T14 7
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2256 1 T30 8 T141 34 T31 17
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2054 1 T5 3 T8 4 T14 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2493 1 T30 41 T141 12 T31 10
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 1932 1 T15 21 T14 11 T141 10
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 35707 1 T6 1 T15 9 T30 36
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2604 1 T14 5 T30 12 T141 5
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2768 1 T6 1 T8 4 T31 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 1901 1 T5 4 T11 1 T30 10
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 4500 1 T5 1 T9 3 T8 3
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 3727 1 T9 4 T132 2 T35 1
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4423 1 T30 23 T31 7 T35 5
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4522 1 T30 28 T141 105 T33 8
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 3561 1 T1 13 T8 10 T14 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5666 1 T5 3 T9 1 T8 4
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4659 1 T5 4 T12 1 T132 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 3473 1 T5 3 T8 4 T14 6
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1440 1 T30 8 T141 5 T31 2
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1395 1 T5 1 T8 4 T14 2
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1835 1 T6 2 T30 47 T141 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1429 1 T5 2 T15 21 T14 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 27652 1 T15 18 T14 2 T30 36
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1874 1 T14 5 T30 10 T141 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1908 1 T8 2 T31 4 T131 37
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1395 1 T5 3 T6 2 T11 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3980 1 T5 3 T12 3 T141 13
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 3089 1 T9 1 T177 1 T178 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3780 1 T30 25 T31 1 T34 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3847 1 T30 28 T141 27 T34 32
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 2622 1 T14 1 T52 10 T30 7
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4809 1 T5 3 T9 1 T31 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3974 1 T5 2 T35 3 T37 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 2634 1 T5 2 T14 4 T30 5
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 1511 1 T30 12 T141 28 T31 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1438 1 T5 2 T8 2 T14 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2014 1 T30 33 T141 5 T134 10
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1526 1 T5 2 T15 21 T141 8
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 20468 1 T15 11 T14 6 T30 35
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1989 1 T8 2 T14 3 T30 10
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2152 1 T8 4 T31 1 T131 40
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 1375 1 T5 3 T30 11 T141 6
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 3904 1 T5 1 T8 3 T141 30
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 2900 1 T9 1 T178 1 T174 3
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3542 1 T6 1 T30 31 T31 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3613 1 T30 21 T141 13 T34 28
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 2393 1 T5 1 T8 11 T14 1
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4839 1 T8 9 T31 1 T19 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4054 1 T5 4 T35 1 T37 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 2623 1 T5 1 T8 1 T14 4
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 990 1 T30 11 T34 8 T17 8
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 992 1 T5 1 T8 5 T14 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1321 1 T30 37 T141 6 T134 7
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1227 1 T5 1 T15 16 T141 10
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 14749 1 T15 3 T30 27 T134 19
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1363 1 T8 1 T14 2 T30 12
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1610 1 T8 2 T131 24 T134 37
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1097 1 T5 2 T30 9 T141 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3240 1 T5 1 T141 2 T134 16
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 2535 1 T35 1 T178 1 T174 3
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3043 1 T30 29 T35 1 T17 12
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3198 1 T30 12 T141 4 T34 22
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 1955 1 T5 1 T14 1 T30 14
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3956 1 T5 3 T19 1 T134 11
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3388 1 T5 2 T35 1 T37 1
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2161 1 T5 1 T14 4 T30 4
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 960 1 T30 9 T141 20 T34 9
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 768 1 T5 3 T8 3 T30 6
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1286 1 T30 14 T141 4 T134 8
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1001 1 T15 14 T141 13 T131 10
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 10342 1 T15 10 T30 20 T134 16
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1073 1 T14 2 T30 2 T141 5
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1409 1 T8 3 T131 17 T134 19
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 825 1 T5 1 T30 8 T141 6
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2546 1 T5 1 T8 1 T141 2
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2009 1 T177 1 T178 3 T174 2
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2591 1 T30 16 T34 1 T17 30
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2663 1 T30 11 T34 19 T17 10
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 1631 1 T5 2 T8 3 T30 10
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3224 1 T5 3 T19 2 T134 13
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2864 1 T5 1 T37 3 T17 2
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 1822 1 T5 1 T8 2 T14 2
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 539 1 T30 6 T34 6 T179 6
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 488 1 T5 3 T30 2 T37 15
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 755 1 T10 1 T30 13 T141 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 750 1 T15 5 T141 5 T131 9
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 6205 1 T15 8 T30 6 T134 7
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 850 1 T14 2 T141 1 T131 4
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 945 1 T8 1 T131 7 T134 8
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 627 1 T30 6 T141 1 T134 7
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1720 1 T8 1 T134 3 T34 6
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1412 1 T35 1 T174 2 T160 3
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1661 1 T30 15 T34 2 T17 39
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1814 1 T30 6 T34 12 T35 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 1146 1 T5 1 T30 7 T180 126
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2259 1 T19 1 T134 17 T37 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1868 1 T5 2 T37 3 T17 4
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1248 1 T30 1 T34 14 T181 4

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