Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15897977	1			T1	20770		T4	137		T5	1933
all_pins[1]	15897977	1			T1	20770		T4	137		T5	1933
all_pins[2]	15897977	1			T1	20770		T4	137		T5	1933

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	40867398	1			T1	51924		T4	308		T5	5114
values[0x1]	6826533	1			T1	10386		T4	103		T5	685
transitions[0x0=>0x1]	6826349	1			T1	10386		T4	103		T5	685
transitions[0x1=>0x0]	6826366	1			T1	10386		T4	103		T5	685

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15879096	1			T1	20545		T4	136		T5	1906
all_pins[0]	values[0x1]	18881	1			T1	225		T4	1		T5	27
all_pins[0]	transitions[0x0=>0x1]	18804	1			T1	225		T4	1		T5	27
all_pins[0]	transitions[0x1=>0x0]	6807309	1			T1	10161		T4	102		T5	658
all_pins[1]	values[0x0]	15897694	1			T1	20770		T4	137		T5	1933
all_pins[1]	values[0x1]	283	1			T17	2		T29	5		T63	4
all_pins[1]	transitions[0x0=>0x1]	226	1			T17	2		T29	5		T63	4
all_pins[1]	transitions[0x1=>0x0]	18824	1			T1	225		T4	1		T5	27
all_pins[2]	values[0x0]	9090608	1			T1	10609		T4	35		T5	1275
all_pins[2]	values[0x1]	6807369	1			T1	10161		T4	102		T5	658
all_pins[2]	transitions[0x0=>0x1]	6807319	1			T1	10161		T4	102		T5	658
all_pins[2]	transitions[0x1=>0x0]	233	1			T17	2		T29	5		T63	3