Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 828 1 T34 4 T63 30 T64 7
all_values[1] 828 1 T34 4 T63 30 T64 7
all_values[2] 828 1 T34 4 T63 30 T64 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1239 1 T34 8 T63 51 T64 11
auto[1] 1245 1 T34 4 T63 39 T64 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 827 1 T34 3 T63 32 T64 10
auto[1] 1657 1 T34 9 T63 58 T64 11


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1394 1 T34 6 T63 56 T64 15
auto[1] 1090 1 T34 6 T63 34 T64 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 135 1 T63 5 T143 2 T79 6
all_values[0] auto[0] auto[0] auto[1] 102 1 T34 1 T63 10 T64 2
all_values[0] auto[0] auto[1] auto[0] 141 1 T63 2 T64 1 T78 3
all_values[0] auto[0] auto[1] auto[1] 83 1 T63 2 T64 1 T143 1
all_values[0] auto[1] auto[0] auto[1] 174 1 T34 2 T63 6 T64 1
all_values[0] auto[1] auto[1] auto[1] 193 1 T34 1 T63 5 T64 2
all_values[1] auto[0] auto[0] auto[0] 136 1 T34 2 T63 7 T64 1
all_values[1] auto[0] auto[0] auto[1] 106 1 T34 1 T63 4 T143 1
all_values[1] auto[0] auto[1] auto[0] 125 1 T63 6 T64 6 T78 3
all_values[1] auto[0] auto[1] auto[1] 105 1 T63 2 T78 1 T94 1
all_values[1] auto[1] auto[0] auto[1] 177 1 T34 1 T63 5 T78 2
all_values[1] auto[1] auto[1] auto[1] 179 1 T63 6 T78 1 T94 2
all_values[2] auto[0] auto[0] auto[0] 153 1 T34 1 T63 7 T64 2
all_values[2] auto[0] auto[0] auto[1] 78 1 T63 2 T64 2 T78 2
all_values[2] auto[0] auto[1] auto[0] 137 1 T63 5 T78 2 T94 1
all_values[2] auto[0] auto[1] auto[1] 93 1 T34 1 T63 4 T78 1
all_values[2] auto[1] auto[0] auto[1] 178 1 T63 5 T64 3 T78 2
all_values[2] auto[1] auto[1] auto[1] 189 1 T34 2 T63 7 T78 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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