Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3651	1			T4	1		T5	5		T23	1
sha2_none	3503	1			T4	2		T5	8		T6	9
sha2_512	6956	1			T1	225		T4	1		T5	7
sha2_384	6707	1			T4	1		T5	6		T6	7
sha2_256	5663	1			T4	1		T5	13		T6	11

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17209

1

T1

225

T4

5

T5

21

auto[1]

9590

1

T4

2

T5

19

T23

1

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9670

1

T4

5

T5

20

T23

1

auto[1]

17129

1

T1

225

T4

2

T5

20

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

13483

1

T1

225

T4

7

T5

18

disabled

13316

1

T5

22

T6

28

T7

3

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	3814	1			T4	2		T5	10		T6	9
key_none	7376	1			T4	2		T5	8		T6	8
key_1024	3917	1			T1	225		T5	4		T6	7
key_512	3342	1			T5	2		T23	1		T6	4
key_384	3054	1			T5	3		T6	8		T9	1
key_256	2669	1			T4	3		T5	8		T6	5
key_128	2560	1			T5	5		T6	8		T7	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17292

1

T1

225

T4

4

T5

18

auto[1]

9507

1

T4

3

T5

22

T23

1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

26635

1

T1

225

T4

7

T5

40

disabled

164

1

T11

2

T49

1

T50

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1378

1

T4

2

T5

4

T6

2

enabled

auto[0]

auto[0]

auto[1]

1328

1

T4

1

T5

2

T6

2

enabled

auto[0]

auto[1]

auto[0]

1360

1

T4

1

T6

3

T9

1

enabled

auto[0]

auto[1]

auto[1]

1313

1

T4

1

T5

1

T23

1

enabled

auto[1]

auto[0]

auto[0]

4009

1

T1

225

T4

1

T5

4

enabled

auto[1]

auto[0]

auto[1]

1400

1

T4

1

T5

3

T6

4

enabled

auto[1]

auto[1]

auto[0]

1407

1

T5

3

T6

1

T11

1

enabled

auto[1]

auto[1]

auto[1]

1288

1

T5

1

T6

1

T8

3

disabled

auto[0]

auto[0]

auto[0]

1094

1

T5

1

T6

1

T7

1

disabled

auto[0]

auto[0]

auto[1]

1036

1

T5

4

T6

7

T7

1

disabled

auto[0]

auto[1]

auto[0]

1103

1

T5

2

T6

4

T10

1

disabled

auto[0]

auto[1]

auto[1]

1058

1

T5

6

T8

1

T15

2

disabled

auto[1]

auto[0]

auto[0]

5879

1

T5

1

T6

3

T8

2

disabled

auto[1]

auto[0]

auto[1]

1085

1

T5

2

T6

6

T8

3

disabled

auto[1]

auto[1]

auto[0]

1062

1

T5

3

T6

3

T8

2

disabled

auto[1]

auto[1]

auto[1]

999

1

T5

3

T6

4

T7

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

13417

1

T1

225

T4

7

T5

18

enabled

disabled

66

1

T11

1

T49

1

T152

2

disabled

disabled

98

1

T11

1

T50

1

T152

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13218

1

T5

22

T6

28

T7

3

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	940	1			T5	1		T6	1		T10	1
key_invalid	sha2_none	673	1			T5	3		T6	2		T9	1
key_invalid	sha2_512	689	1			T4	1		T5	2		T6	3
key_invalid	sha2_384	724	1			T5	3		T6	1		T8	2
key_invalid	sha2_256	706	1			T4	1		T5	1		T6	2
key_none	sha2_invalid	452	1			T4	1		T5	2		T6	4
key_none	sha2_none	467	1			T5	1		T6	3		T134	1
key_none	sha2_512	2465	1			T5	1		T8	1		T13	1
key_none	sha2_384	2442	1			T5	2		T6	1		T13	1
key_none	sha2_256	1503	1			T5	1		T10	1		T12	1
key_1024	sha2_invalid	466	1			T6	1		T8	1		T10	2
key_1024	sha2_none	457	1			T5	1		T10	1		T55	1
key_1024	sha2_512	1627	1			T1	225		T5	1		T7	1
key_1024	sha2_384	825	1			T5	1		T6	2		T9	1
key_512	sha2_invalid	451	1			T23	1		T10	1		T12	3
key_512	sha2_none	467	1			T8	1		T12	1		T14	1
key_512	sha2_512	528	1			T6	1		T15	2		T12	2
key_512	sha2_384	1106	1			T6	3		T11	1		T8	1
key_512	sha2_256	753	1			T5	2		T12	1		T52	45
key_384	sha2_invalid	423	1			T6	1		T9	1		T8	2
key_384	sha2_none	472	1			T6	1		T10	1		T14	1
key_384	sha2_512	556	1			T5	1		T6	3		T8	1
key_384	sha2_384	563	1			T8	1		T13	1		T14	1
key_384	sha2_256	1004	1			T5	2		T6	3		T8	1
key_256	sha2_invalid	438	1			T5	2		T6	3		T12	2
key_256	sha2_none	495	1			T4	2		T5	2		T6	1
key_256	sha2_512	547	1			T5	1		T12	1		T14	1
key_256	sha2_384	523	1			T4	1		T9	1		T10	2
key_256	sha2_256	627	1			T5	3		T6	1		T11	2
key_128	sha2_invalid	465	1			T6	2		T8	1		T30	1
key_128	sha2_none	463	1			T5	1		T6	2		T10	1
key_128	sha2_512	530	1			T5	1		T6	2		T13	1
key_128	sha2_384	516	1			T8	2		T10	1		T15	1
key_128	sha2_256	553	1			T5	3		T6	2		T7	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

501

1

T5

1

T6

3

T8

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	940	1			T5	1		T6	1		T10	1
key_invalid	sha2_none	673	1			T5	3		T6	2		T9	1
key_invalid	sha2_512	689	1			T4	1		T5	2		T6	3
key_invalid	sha2_384	724	1			T5	3		T6	1		T8	2
key_invalid	sha2_256	706	1			T4	1		T5	1		T6	2
key_none	sha2_invalid	452	1			T4	1		T5	2		T6	4
key_none	sha2_none	467	1			T5	1		T6	3		T134	1
key_none	sha2_512	2465	1			T5	1		T8	1		T13	1
key_none	sha2_384	2442	1			T5	2		T6	1		T13	1
key_none	sha2_256	1503	1			T5	1		T10	1		T12	1
key_1024	sha2_invalid	466	1			T6	1		T8	1		T10	2
key_1024	sha2_none	457	1			T5	1		T10	1		T55	1
key_1024	sha2_512	1627	1			T1	225		T5	1		T7	1
key_1024	sha2_384	825	1			T5	1		T6	2		T9	1
key_1024	sha2_256	501	1			T5	1		T6	3		T8	1
key_512	sha2_invalid	451	1			T23	1		T10	1		T12	3
key_512	sha2_none	467	1			T8	1		T12	1		T14	1
key_512	sha2_512	528	1			T6	1		T15	2		T12	2
key_512	sha2_384	1106	1			T6	3		T11	1		T8	1
key_512	sha2_256	753	1			T5	2		T12	1		T52	45
key_384	sha2_invalid	423	1			T6	1		T9	1		T8	2
key_384	sha2_none	472	1			T6	1		T10	1		T14	1
key_384	sha2_512	556	1			T5	1		T6	3		T8	1
key_384	sha2_384	563	1			T8	1		T13	1		T14	1
key_384	sha2_256	1004	1			T5	2		T6	3		T8	1
key_256	sha2_invalid	438	1			T5	2		T6	3		T12	2
key_256	sha2_none	495	1			T4	2		T5	2		T6	1
key_256	sha2_512	547	1			T5	1		T12	1		T14	1
key_256	sha2_384	523	1			T4	1		T9	1		T10	2
key_256	sha2_256	627	1			T5	3		T6	1		T11	2
key_128	sha2_invalid	465	1			T6	2		T8	1		T30	1
key_128	sha2_none	463	1			T5	1		T6	2		T10	1
key_128	sha2_512	530	1			T5	1		T6	2		T13	1
key_128	sha2_384	516	1			T8	2		T10	1		T15	1
key_128	sha2_256	553	1			T5	3		T6	2		T7	1