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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 95.37 97.17 100.00 94.12 98.25 98.52 99.85


Total test records in report: 652
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T126 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.618140768 Sep 18 07:44:47 PM UTC 24 Sep 18 07:44:51 PM UTC 24 45238511 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.156401492 Sep 18 07:44:46 PM UTC 24 Sep 18 07:44:52 PM UTC 24 176736648 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.912069289 Sep 18 07:44:29 PM UTC 24 Sep 18 07:44:52 PM UTC 24 4386777362 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2649050011 Sep 18 07:44:53 PM UTC 24 Sep 18 07:44:56 PM UTC 24 761062529 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4290158696 Sep 18 07:44:46 PM UTC 24 Sep 18 07:44:58 PM UTC 24 858306941 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1172413865 Sep 18 07:44:53 PM UTC 24 Sep 18 07:44:58 PM UTC 24 410334800 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3704400792 Sep 18 07:44:57 PM UTC 24 Sep 18 07:44:59 PM UTC 24 233788381 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2071082094 Sep 18 07:45:00 PM UTC 24 Sep 18 07:45:02 PM UTC 24 172579993 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.215887254 Sep 18 07:45:00 PM UTC 24 Sep 18 07:45:02 PM UTC 24 136297474 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2561051200 Sep 18 07:45:00 PM UTC 24 Sep 18 07:45:03 PM UTC 24 38436133 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.422509960 Sep 18 07:45:00 PM UTC 24 Sep 18 07:45:03 PM UTC 24 41917301 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3389266062 Sep 18 07:45:00 PM UTC 24 Sep 18 07:45:04 PM UTC 24 315061423 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3959570652 Sep 18 07:45:04 PM UTC 24 Sep 18 07:45:06 PM UTC 24 20303929 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1181373826 Sep 18 07:45:04 PM UTC 24 Sep 18 07:45:07 PM UTC 24 29030142 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.1005463884 Sep 18 07:45:05 PM UTC 24 Sep 18 07:45:07 PM UTC 24 16156384 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.3437231869 Sep 18 07:45:03 PM UTC 24 Sep 18 07:45:08 PM UTC 24 55120659 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.3225357514 Sep 18 07:45:04 PM UTC 24 Sep 18 07:45:11 PM UTC 24 227076574 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2139836720 Sep 18 07:45:08 PM UTC 24 Sep 18 07:45:11 PM UTC 24 140090426 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.864486930 Sep 18 07:45:08 PM UTC 24 Sep 18 07:45:13 PM UTC 24 119381874 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1802834765 Sep 18 07:45:00 PM UTC 24 Sep 18 07:45:13 PM UTC 24 705541182 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.1794753756 Sep 18 07:45:05 PM UTC 24 Sep 18 07:45:13 PM UTC 24 447808298 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.1390660002 Sep 18 07:45:12 PM UTC 24 Sep 18 07:45:14 PM UTC 24 46524852 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.2479532851 Sep 18 07:45:09 PM UTC 24 Sep 18 07:45:14 PM UTC 24 157081987 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.4022151030 Sep 18 07:45:14 PM UTC 24 Sep 18 07:45:17 PM UTC 24 54628737 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2129613141 Sep 18 07:45:14 PM UTC 24 Sep 18 07:45:17 PM UTC 24 48651639 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1485687920 Sep 18 07:45:11 PM UTC 24 Sep 18 07:45:17 PM UTC 24 222593352 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2258469254 Sep 18 07:45:16 PM UTC 24 Sep 18 07:45:18 PM UTC 24 42958378 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1348593406 Sep 18 07:45:07 PM UTC 24 Sep 18 07:45:21 PM UTC 24 6285930761 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1421204482 Sep 18 07:45:16 PM UTC 24 Sep 18 07:45:24 PM UTC 24 749837849 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.2191151843 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:26 PM UTC 24 33782565 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.3044562042 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:27 PM UTC 24 63034833 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1391201695 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:27 PM UTC 24 35533129 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2073173250 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:28 PM UTC 24 106808425 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.883479444 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:28 PM UTC 24 80894788 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.1183902952 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:29 PM UTC 24 185485001 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1799649966 Sep 18 07:45:28 PM UTC 24 Sep 18 07:45:29 PM UTC 24 13505622 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3133442233 Sep 18 07:45:28 PM UTC 24 Sep 18 07:45:30 PM UTC 24 85136128 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.8982850 Sep 18 07:45:14 PM UTC 24 Sep 18 07:45:31 PM UTC 24 1096130135 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1279215150 Sep 18 07:45:30 PM UTC 24 Sep 18 07:45:32 PM UTC 24 40006094 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.2359929186 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:32 PM UTC 24 550850386 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2109122686 Sep 18 07:45:29 PM UTC 24 Sep 18 07:45:32 PM UTC 24 224712194 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2021386984 Sep 18 07:45:24 PM UTC 24 Sep 18 07:45:32 PM UTC 24 879048742 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1273691664 Sep 18 07:45:28 PM UTC 24 Sep 18 07:45:32 PM UTC 24 107686544 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1554580517 Sep 18 07:45:29 PM UTC 24 Sep 18 07:45:32 PM UTC 24 27054373 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.4290318093 Sep 18 07:45:31 PM UTC 24 Sep 18 07:45:33 PM UTC 24 15157452 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3261463899 Sep 18 07:45:30 PM UTC 24 Sep 18 07:45:34 PM UTC 24 162714391 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3552026611 Sep 18 07:45:37 PM UTC 24 Sep 18 07:45:41 PM UTC 24 198881713 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1321870716 Sep 18 07:45:31 PM UTC 24 Sep 18 07:45:35 PM UTC 24 363525543 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.743194321 Sep 18 07:45:33 PM UTC 24 Sep 18 07:45:35 PM UTC 24 12363292 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.4034652643 Sep 18 07:45:33 PM UTC 24 Sep 18 07:45:36 PM UTC 24 38270834 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2871572973 Sep 18 07:45:32 PM UTC 24 Sep 18 07:45:37 PM UTC 24 44896588 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3765058722 Sep 18 07:45:33 PM UTC 24 Sep 18 07:45:37 PM UTC 24 140253167 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.1815967856 Sep 18 07:45:32 PM UTC 24 Sep 18 07:45:38 PM UTC 24 567714117 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1497334618 Sep 18 07:45:35 PM UTC 24 Sep 18 07:45:39 PM UTC 24 361383154 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.942312553 Sep 18 07:45:34 PM UTC 24 Sep 18 07:45:39 PM UTC 24 380632041 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1366798981 Sep 18 07:45:37 PM UTC 24 Sep 18 07:45:39 PM UTC 24 62285734 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.509583918 Sep 18 07:45:37 PM UTC 24 Sep 18 07:45:39 PM UTC 24 107718060 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3467205715 Sep 18 07:45:33 PM UTC 24 Sep 18 07:45:40 PM UTC 24 270942603 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.469478535 Sep 18 07:45:37 PM UTC 24 Sep 18 07:45:41 PM UTC 24 446405568 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1763925925 Sep 18 07:45:38 PM UTC 24 Sep 18 07:45:41 PM UTC 24 36720017 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3299275127 Sep 18 07:45:39 PM UTC 24 Sep 18 07:45:41 PM UTC 24 13020400 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1463801977 Sep 18 07:45:39 PM UTC 24 Sep 18 07:45:41 PM UTC 24 18970780 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.640228508 Sep 18 07:45:38 PM UTC 24 Sep 18 07:45:42 PM UTC 24 704837270 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2593406130 Sep 18 07:45:39 PM UTC 24 Sep 18 07:45:42 PM UTC 24 112052004 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3238896901 Sep 18 07:45:42 PM UTC 24 Sep 18 07:45:44 PM UTC 24 12218276 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.3376195084 Sep 18 07:45:42 PM UTC 24 Sep 18 07:45:44 PM UTC 24 26649405 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2384883040 Sep 18 07:45:42 PM UTC 24 Sep 18 07:45:45 PM UTC 24 177284160 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2438154379 Sep 18 07:45:38 PM UTC 24 Sep 18 07:45:45 PM UTC 24 924783516 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3202269867 Sep 18 07:45:44 PM UTC 24 Sep 18 07:45:46 PM UTC 24 76375350 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3382823785 Sep 18 07:45:42 PM UTC 24 Sep 18 07:45:47 PM UTC 24 125081033 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.1010880066 Sep 18 07:45:45 PM UTC 24 Sep 18 07:45:47 PM UTC 24 18528428 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3806617542 Sep 18 07:45:45 PM UTC 24 Sep 18 07:45:49 PM UTC 24 32381417 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.533128978 Sep 18 07:45:44 PM UTC 24 Sep 18 07:45:49 PM UTC 24 315441905 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1151452634 Sep 18 07:45:47 PM UTC 24 Sep 18 07:45:49 PM UTC 24 61653846 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.549739453 Sep 18 07:45:44 PM UTC 24 Sep 18 07:45:49 PM UTC 24 250602209 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2066091371 Sep 18 07:45:46 PM UTC 24 Sep 18 07:45:49 PM UTC 24 82261395 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.4191452765 Sep 18 07:45:42 PM UTC 24 Sep 18 07:45:49 PM UTC 24 2371480408 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.3861905486 Sep 18 07:45:48 PM UTC 24 Sep 18 07:45:50 PM UTC 24 17082984 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.71689977 Sep 18 07:45:47 PM UTC 24 Sep 18 07:45:51 PM UTC 24 186397440 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2897988083 Sep 18 07:45:46 PM UTC 24 Sep 18 07:45:52 PM UTC 24 68760063 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2524292615 Sep 18 07:45:51 PM UTC 24 Sep 18 07:45:52 PM UTC 24 23916359 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.2814079230 Sep 18 07:45:51 PM UTC 24 Sep 18 07:45:53 PM UTC 24 81680818 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3375901000 Sep 18 07:45:50 PM UTC 24 Sep 18 07:45:54 PM UTC 24 51001023 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.516300175 Sep 18 07:45:49 PM UTC 24 Sep 18 07:45:54 PM UTC 24 461918064 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3416057417 Sep 18 07:45:51 PM UTC 24 Sep 18 07:45:54 PM UTC 24 320435210 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2751392572 Sep 18 07:45:52 PM UTC 24 Sep 18 07:45:55 PM UTC 24 283951175 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.3422490630 Sep 18 07:45:54 PM UTC 24 Sep 18 07:45:56 PM UTC 24 18626070 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.910864993 Sep 18 07:45:53 PM UTC 24 Sep 18 07:45:57 PM UTC 24 38737907 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.562181112 Sep 18 07:45:55 PM UTC 24 Sep 18 07:45:57 PM UTC 24 20855865 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.1356320704 Sep 18 07:45:53 PM UTC 24 Sep 18 07:45:59 PM UTC 24 1753473552 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.660316407 Sep 18 07:45:55 PM UTC 24 Sep 18 07:45:59 PM UTC 24 143691230 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.3452668088 Sep 18 07:45:57 PM UTC 24 Sep 18 07:45:59 PM UTC 24 59390745 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1313710143 Sep 18 07:45:57 PM UTC 24 Sep 18 07:46:00 PM UTC 24 35385313 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1029864905 Sep 18 07:45:55 PM UTC 24 Sep 18 07:46:01 PM UTC 24 84461420 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1172852605 Sep 18 07:45:56 PM UTC 24 Sep 18 07:46:02 PM UTC 24 163314941 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1962106105 Sep 18 07:46:00 PM UTC 24 Sep 18 07:46:02 PM UTC 24 216896746 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.237293642 Sep 18 07:45:56 PM UTC 24 Sep 18 07:46:02 PM UTC 24 923616250 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1338233261 Sep 18 07:46:01 PM UTC 24 Sep 18 07:46:04 PM UTC 24 643068336 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.181755941 Sep 18 07:46:00 PM UTC 24 Sep 18 07:46:04 PM UTC 24 33577935 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2414327377 Sep 18 07:46:03 PM UTC 24 Sep 18 07:46:04 PM UTC 24 50920559 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2113425421 Sep 18 07:46:03 PM UTC 24 Sep 18 07:46:05 PM UTC 24 17508994 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1050756857 Sep 18 07:46:03 PM UTC 24 Sep 18 07:46:06 PM UTC 24 260602952 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.39473488 Sep 18 07:46:01 PM UTC 24 Sep 18 07:46:06 PM UTC 24 345555111 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2398731778 Sep 18 07:46:04 PM UTC 24 Sep 18 07:46:06 PM UTC 24 67461526 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3692611916 Sep 18 07:46:05 PM UTC 24 Sep 18 07:46:07 PM UTC 24 19013797 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.3976327599 Sep 18 07:46:05 PM UTC 24 Sep 18 07:46:07 PM UTC 24 164359931 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2439214632 Sep 18 07:46:04 PM UTC 24 Sep 18 07:46:07 PM UTC 24 134716528 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.4021190238 Sep 18 07:46:06 PM UTC 24 Sep 18 07:46:09 PM UTC 24 52493484 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.479039804 Sep 18 07:46:07 PM UTC 24 Sep 18 07:46:09 PM UTC 24 21658956 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2002377961 Sep 18 07:46:06 PM UTC 24 Sep 18 07:46:10 PM UTC 24 364375300 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1217351213 Sep 18 07:46:07 PM UTC 24 Sep 18 07:46:11 PM UTC 24 56636264 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2623143318 Sep 18 07:46:08 PM UTC 24 Sep 18 07:46:11 PM UTC 24 26900430 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.563576880 Sep 18 07:46:09 PM UTC 24 Sep 18 07:46:11 PM UTC 24 217473930 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2589211160 Sep 18 07:46:10 PM UTC 24 Sep 18 07:46:12 PM UTC 24 13422427 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.601244912 Sep 18 07:46:05 PM UTC 24 Sep 18 07:46:12 PM UTC 24 1199626742 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1608082727 Sep 18 07:46:10 PM UTC 24 Sep 18 07:46:13 PM UTC 24 29392458 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1436203336 Sep 18 07:46:12 PM UTC 24 Sep 18 07:46:14 PM UTC 24 46070497 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1421782952 Sep 18 07:46:12 PM UTC 24 Sep 18 07:46:14 PM UTC 24 60061234 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3386721884 Sep 18 07:46:12 PM UTC 24 Sep 18 07:46:14 PM UTC 24 11353091 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2733393211 Sep 18 07:46:14 PM UTC 24 Sep 18 07:46:15 PM UTC 24 24716624 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3486524383 Sep 18 07:46:14 PM UTC 24 Sep 18 07:46:15 PM UTC 24 16335456 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1940822657 Sep 18 07:46:14 PM UTC 24 Sep 18 07:46:15 PM UTC 24 18792961 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.4057573283 Sep 18 07:46:14 PM UTC 24 Sep 18 07:46:16 PM UTC 24 13663330 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3418773408 Sep 18 07:46:15 PM UTC 24 Sep 18 07:46:17 PM UTC 24 13547642 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1522759419 Sep 18 07:46:15 PM UTC 24 Sep 18 07:46:17 PM UTC 24 17366893 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.215042773 Sep 18 07:46:15 PM UTC 24 Sep 18 07:46:17 PM UTC 24 27614399 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2681181592 Sep 18 07:46:15 PM UTC 24 Sep 18 07:46:17 PM UTC 24 41777948 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.2139954355 Sep 18 07:46:16 PM UTC 24 Sep 18 07:46:18 PM UTC 24 16740630 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3154862640 Sep 18 07:46:16 PM UTC 24 Sep 18 07:46:18 PM UTC 24 45757678 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.2025196206 Sep 18 07:46:16 PM UTC 24 Sep 18 07:46:18 PM UTC 24 36130070 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.346143555 Sep 18 07:46:16 PM UTC 24 Sep 18 07:46:18 PM UTC 24 15574016 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2815796111 Sep 18 07:46:17 PM UTC 24 Sep 18 07:46:19 PM UTC 24 17535567 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2334069215 Sep 18 07:46:17 PM UTC 24 Sep 18 07:46:19 PM UTC 24 51481692 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3477945441 Sep 18 07:46:17 PM UTC 24 Sep 18 07:46:19 PM UTC 24 88781045 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1391939720 Sep 18 07:46:17 PM UTC 24 Sep 18 07:46:19 PM UTC 24 111130332 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1326678489 Sep 18 07:46:19 PM UTC 24 Sep 18 07:46:21 PM UTC 24 82075300 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.2240696991 Sep 18 07:46:19 PM UTC 24 Sep 18 07:46:21 PM UTC 24 13500882 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.93063667 Sep 18 07:46:19 PM UTC 24 Sep 18 07:46:21 PM UTC 24 16340173 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2922830279 Sep 18 07:46:19 PM UTC 24 Sep 18 07:46:21 PM UTC 24 11899702 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1448856782 Sep 18 07:46:20 PM UTC 24 Sep 18 07:46:22 PM UTC 24 27518210 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.2160072618 Sep 18 07:46:20 PM UTC 24 Sep 18 07:46:22 PM UTC 24 12921623 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.184552307 Sep 18 07:46:20 PM UTC 24 Sep 18 07:46:22 PM UTC 24 13984060 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.371320014 Sep 18 07:46:20 PM UTC 24 Sep 18 07:46:22 PM UTC 24 126208864 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.258510689 Sep 18 07:46:21 PM UTC 24 Sep 18 07:46:23 PM UTC 24 14419493 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1601768470 Sep 18 07:46:21 PM UTC 24 Sep 18 07:46:23 PM UTC 24 16193918 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4028041492 Sep 18 07:45:49 PM UTC 24 Sep 18 07:51:55 PM UTC 24 288651043143 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3906012015 Sep 18 07:45:52 PM UTC 24 Sep 18 07:56:24 PM UTC 24 51437595185 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.201023018 Sep 18 07:45:24 PM UTC 24 Sep 18 07:57:39 PM UTC 24 145575613171 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.739142512 Sep 18 07:45:44 PM UTC 24 Sep 18 07:58:47 PM UTC 24 196870162513 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3925042099 Sep 18 07:44:52 PM UTC 24 Sep 18 07:59:43 PM UTC 24 403847210779 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.695617727 Sep 18 07:46:06 PM UTC 24 Sep 18 07:59:59 PM UTC 24 1698336448983 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4209743902 Sep 18 07:45:41 PM UTC 24 Sep 18 08:03:01 PM UTC 24 471357699352 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_smoke.2752364894
Short name T6
Test name
Test status
Simulation time 910043205 ps
CPU time 14.12 seconds
Started Sep 18 07:20:38 PM UTC 24
Finished Sep 18 07:20:53 PM UTC 24
Peak memory 210656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752364894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2752364894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3495336264
Short name T21
Test name
Test status
Simulation time 81357653104 ps
CPU time 494.3 seconds
Started Sep 18 07:21:45 PM UTC 24
Finished Sep 18 07:30:06 PM UTC 24
Peak memory 685448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34953362
64 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3495336264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.1323574751
Short name T17
Test name
Test status
Simulation time 7451454855 ps
CPU time 71.13 seconds
Started Sep 18 07:20:49 PM UTC 24
Finished Sep 18 07:22:02 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323574751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1323574751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.2333302408
Short name T14
Test name
Test status
Simulation time 7614233588 ps
CPU time 21.95 seconds
Started Sep 18 07:21:07 PM UTC 24
Finished Sep 18 07:21:30 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333302408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2333302408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_stress_all.2116650455
Short name T34
Test name
Test status
Simulation time 3642668025 ps
CPU time 68.83 seconds
Started Sep 18 07:20:46 PM UTC 24
Finished Sep 18 07:21:57 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116650455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2116650455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.366347461
Short name T61
Test name
Test status
Simulation time 151735983 ps
CPU time 4.23 seconds
Started Sep 18 07:44:39 PM UTC 24
Finished Sep 18 07:44:45 PM UTC 24
Peak memory 206796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366347461 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.366347461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_error.1125465656
Short name T50
Test name
Test status
Simulation time 9345583871 ps
CPU time 96.54 seconds
Started Sep 18 07:20:39 PM UTC 24
Finished Sep 18 07:22:17 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125465656 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1125465656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2217111939
Short name T24
Test name
Test status
Simulation time 2682930013 ps
CPU time 75 seconds
Started Sep 18 07:20:38 PM UTC 24
Finished Sep 18 07:21:54 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217111939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2217111939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.3214054698
Short name T3
Test name
Test status
Simulation time 196657480 ps
CPU time 0.77 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:20:42 PM UTC 24
Peak memory 238208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214054698 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3214054698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_smoke.3043402648
Short name T160
Test name
Test status
Simulation time 300080673 ps
CPU time 17.22 seconds
Started Sep 18 07:23:06 PM UTC 24
Finished Sep 18 07:23:24 PM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043402648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3043402648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.3044562042
Short name T118
Test name
Test status
Simulation time 63034833 ps
CPU time 1.2 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:27 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044562042 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3044562042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_stress_all.92816473
Short name T108
Test name
Test status
Simulation time 21019555188 ps
CPU time 769.02 seconds
Started Sep 18 07:29:33 PM UTC 24
Finished Sep 18 07:42:31 PM UTC 24
Peak memory 638528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92816473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.92816473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2408387361
Short name T101
Test name
Test status
Simulation time 3341028987 ps
CPU time 240.79 seconds
Started Sep 18 07:20:53 PM UTC 24
Finished Sep 18 07:24:57 PM UTC 24
Peak memory 219032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408387361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2408387361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_stress_all.3746008178
Short name T64
Test name
Test status
Simulation time 11489944021 ps
CPU time 199.72 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:24:03 PM UTC 24
Peak memory 681220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746008178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3746008178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_smoke.485402685
Short name T12
Test name
Test status
Simulation time 1380014734 ps
CPU time 21.9 seconds
Started Sep 18 07:21:03 PM UTC 24
Finished Sep 18 07:21:26 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485402685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.485402685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_alert_test.3963938963
Short name T2
Test name
Test status
Simulation time 23137897 ps
CPU time 0.55 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:20:42 PM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963938963 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3963938963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2021386984
Short name T144
Test name
Test status
Simulation time 879048742 ps
CPU time 6.52 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:32 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021386984 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2021386984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_stress_all.2730168098
Short name T42
Test name
Test status
Simulation time 24130737313 ps
CPU time 1772.03 seconds
Started Sep 18 07:25:44 PM UTC 24
Finished Sep 18 07:55:35 PM UTC 24
Peak memory 711972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730168098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2730168098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.176617270
Short name T202
Test name
Test status
Simulation time 17436460375 ps
CPU time 36.16 seconds
Started Sep 18 07:23:01 PM UTC 24
Finished Sep 18 07:23:38 PM UTC 24
Peak memory 219004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176617270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.176617270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.4191452765
Short name T145
Test name
Test status
Simulation time 2371480408 ps
CPU time 6.46 seconds
Started Sep 18 07:45:42 PM UTC 24
Finished Sep 18 07:45:49 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191452765 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4191452765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.678057594
Short name T36
Test name
Test status
Simulation time 9743758921 ps
CPU time 76.79 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:21:59 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678057594 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.678057594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.3775155658
Short name T277
Test name
Test status
Simulation time 9151263606 ps
CPU time 333.44 seconds
Started Sep 18 07:23:12 PM UTC 24
Finished Sep 18 07:28:50 PM UTC 24
Peak memory 490812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775155658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3775155658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_stress_all.1091174933
Short name T335
Test name
Test status
Simulation time 22695562271 ps
CPU time 479.36 seconds
Started Sep 18 07:24:19 PM UTC 24
Finished Sep 18 07:32:25 PM UTC 24
Peak memory 703880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091174933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1091174933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_error.1563572256
Short name T247
Test name
Test status
Simulation time 11034320372 ps
CPU time 110.08 seconds
Started Sep 18 07:24:59 PM UTC 24
Finished Sep 18 07:26:52 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563572256 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1563572256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.259870079
Short name T110
Test name
Test status
Simulation time 153111734 ps
CPU time 10.86 seconds
Started Sep 18 07:44:31 PM UTC 24
Finished Sep 18 07:44:43 PM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259870079 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.259870079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.912069289
Short name T534
Test name
Test status
Simulation time 4386777362 ps
CPU time 22.1 seconds
Started Sep 18 07:44:29 PM UTC 24
Finished Sep 18 07:44:52 PM UTC 24
Peak memory 207312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912069289 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.912069289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.1670421963
Short name T529
Test name
Test status
Simulation time 70227152 ps
CPU time 1.06 seconds
Started Sep 18 07:44:28 PM UTC 24
Finished Sep 18 07:44:30 PM UTC 24
Peak memory 205252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670421963 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1670421963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3723789369
Short name T68
Test name
Test status
Simulation time 161190545 ps
CPU time 3.83 seconds
Started Sep 18 07:44:33 PM UTC 24
Finished Sep 18 07:44:38 PM UTC 24
Peak memory 206900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3723789369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.3723789369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.819779187
Short name T530
Test name
Test status
Simulation time 52520382 ps
CPU time 1.18 seconds
Started Sep 18 07:44:29 PM UTC 24
Finished Sep 18 07:44:31 PM UTC 24
Peak memory 206392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819779187 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.819779187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.2896667241
Short name T528
Test name
Test status
Simulation time 25085606 ps
CPU time 0.85 seconds
Started Sep 18 07:44:26 PM UTC 24
Finished Sep 18 07:44:28 PM UTC 24
Peak memory 203968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896667241 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2896667241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3606267972
Short name T124
Test name
Test status
Simulation time 117198558 ps
CPU time 1.67 seconds
Started Sep 18 07:44:32 PM UTC 24
Finished Sep 18 07:44:35 PM UTC 24
Peak memory 205872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606267972 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.3606267972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.382817843
Short name T60
Test name
Test status
Simulation time 657284591 ps
CPU time 5.4 seconds
Started Sep 18 07:44:26 PM UTC 24
Finished Sep 18 07:44:32 PM UTC 24
Peak memory 206828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382817843 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.382817843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3850214050
Short name T57
Test name
Test status
Simulation time 88772562 ps
CPU time 1.9 seconds
Started Sep 18 07:44:26 PM UTC 24
Finished Sep 18 07:44:29 PM UTC 24
Peak memory 205944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850214050 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3850214050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.156401492
Short name T533
Test name
Test status
Simulation time 176736648 ps
CPU time 5.3 seconds
Started Sep 18 07:44:46 PM UTC 24
Finished Sep 18 07:44:52 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156401492 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.156401492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4290158696
Short name T535
Test name
Test status
Simulation time 858306941 ps
CPU time 11.27 seconds
Started Sep 18 07:44:46 PM UTC 24
Finished Sep 18 07:44:58 PM UTC 24
Peak memory 206864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290158696 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4290158696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.3487300588
Short name T532
Test name
Test status
Simulation time 39617753 ps
CPU time 1.13 seconds
Started Sep 18 07:44:43 PM UTC 24
Finished Sep 18 07:44:45 PM UTC 24
Peak memory 205284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487300588 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3487300588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3925042099
Short name T650
Test name
Test status
Simulation time 403847210779 ps
CPU time 881.23 seconds
Started Sep 18 07:44:52 PM UTC 24
Finished Sep 18 07:59:43 PM UTC 24
Peak memory 223356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3925042099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.3925042099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1251280916
Short name T125
Test name
Test status
Simulation time 39780024 ps
CPU time 1.19 seconds
Started Sep 18 07:44:44 PM UTC 24
Finished Sep 18 07:44:46 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251280916 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1251280916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.3990181169
Short name T531
Test name
Test status
Simulation time 26021018 ps
CPU time 1.03 seconds
Started Sep 18 07:44:40 PM UTC 24
Finished Sep 18 07:44:41 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990181169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3990181169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.618140768
Short name T126
Test name
Test status
Simulation time 45238511 ps
CPU time 3.49 seconds
Started Sep 18 07:44:47 PM UTC 24
Finished Sep 18 07:44:51 PM UTC 24
Peak memory 206852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618140768 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.618140768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.1313580454
Short name T67
Test name
Test status
Simulation time 108163840 ps
CPU time 2.19 seconds
Started Sep 18 07:44:35 PM UTC 24
Finished Sep 18 07:44:38 PM UTC 24
Peak memory 206912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313580454 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1313580454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4209743902
Short name T652
Test name
Test status
Simulation time 471357699352 ps
CPU time 1029.01 seconds
Started Sep 18 07:45:41 PM UTC 24
Finished Sep 18 08:03:01 PM UTC 24
Peak memory 221316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4209743902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.4209743902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1463801977
Short name T567
Test name
Test status
Simulation time 18970780 ps
CPU time 1.08 seconds
Started Sep 18 07:45:39 PM UTC 24
Finished Sep 18 07:45:41 PM UTC 24
Peak memory 205308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463801977 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1463801977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3299275127
Short name T566
Test name
Test status
Simulation time 13020400 ps
CPU time 0.87 seconds
Started Sep 18 07:45:39 PM UTC 24
Finished Sep 18 07:45:41 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299275127 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3299275127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2593406130
Short name T568
Test name
Test status
Simulation time 112052004 ps
CPU time 1.81 seconds
Started Sep 18 07:45:39 PM UTC 24
Finished Sep 18 07:45:42 PM UTC 24
Peak memory 206052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593406130 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.2593406130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2438154379
Short name T572
Test name
Test status
Simulation time 924783516 ps
CPU time 5.91 seconds
Started Sep 18 07:45:38 PM UTC 24
Finished Sep 18 07:45:45 PM UTC 24
Peak memory 206908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438154379 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2438154379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.640228508
Short name T146
Test name
Test status
Simulation time 704837270 ps
CPU time 2.81 seconds
Started Sep 18 07:45:38 PM UTC 24
Finished Sep 18 07:45:42 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640228508 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.640228508
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.739142512
Short name T649
Test name
Test status
Simulation time 196870162513 ps
CPU time 773.75 seconds
Started Sep 18 07:45:44 PM UTC 24
Finished Sep 18 07:58:47 PM UTC 24
Peak memory 219408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=739142512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_r
eset.739142512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.3376195084
Short name T570
Test name
Test status
Simulation time 26649405 ps
CPU time 1.18 seconds
Started Sep 18 07:45:42 PM UTC 24
Finished Sep 18 07:45:44 PM UTC 24
Peak memory 206456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376195084 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3376195084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.3238896901
Short name T569
Test name
Test status
Simulation time 12218276 ps
CPU time 0.84 seconds
Started Sep 18 07:45:42 PM UTC 24
Finished Sep 18 07:45:44 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238896901 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3238896901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2384883040
Short name T571
Test name
Test status
Simulation time 177284160 ps
CPU time 1.77 seconds
Started Sep 18 07:45:42 PM UTC 24
Finished Sep 18 07:45:45 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384883040 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.2384883040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3382823785
Short name T574
Test name
Test status
Simulation time 125081033 ps
CPU time 4.05 seconds
Started Sep 18 07:45:42 PM UTC 24
Finished Sep 18 07:45:47 PM UTC 24
Peak memory 206908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382823785 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3382823785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2066091371
Short name T580
Test name
Test status
Simulation time 82261395 ps
CPU time 2.05 seconds
Started Sep 18 07:45:46 PM UTC 24
Finished Sep 18 07:45:49 PM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2066091371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.2066091371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.1010880066
Short name T575
Test name
Test status
Simulation time 18528428 ps
CPU time 1.07 seconds
Started Sep 18 07:45:45 PM UTC 24
Finished Sep 18 07:45:47 PM UTC 24
Peak memory 205664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010880066 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1010880066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3202269867
Short name T573
Test name
Test status
Simulation time 76375350 ps
CPU time 0.98 seconds
Started Sep 18 07:45:44 PM UTC 24
Finished Sep 18 07:45:46 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202269867 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3202269867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3806617542
Short name T576
Test name
Test status
Simulation time 32381417 ps
CPU time 2.61 seconds
Started Sep 18 07:45:45 PM UTC 24
Finished Sep 18 07:45:49 PM UTC 24
Peak memory 206772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806617542 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.3806617542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.549739453
Short name T579
Test name
Test status
Simulation time 250602209 ps
CPU time 4.24 seconds
Started Sep 18 07:45:44 PM UTC 24
Finished Sep 18 07:45:49 PM UTC 24
Peak memory 206836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549739453 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.549739453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.533128978
Short name T577
Test name
Test status
Simulation time 315441905 ps
CPU time 4.09 seconds
Started Sep 18 07:45:44 PM UTC 24
Finished Sep 18 07:45:49 PM UTC 24
Peak memory 206916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533128978 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.533128978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4028041492
Short name T646
Test name
Test status
Simulation time 288651043143 ps
CPU time 360.74 seconds
Started Sep 18 07:45:49 PM UTC 24
Finished Sep 18 07:51:55 PM UTC 24
Peak memory 223688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4028041492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.4028041492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.3861905486
Short name T581
Test name
Test status
Simulation time 17082984 ps
CPU time 1.14 seconds
Started Sep 18 07:45:48 PM UTC 24
Finished Sep 18 07:45:50 PM UTC 24
Peak memory 206040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861905486 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3861905486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1151452634
Short name T578
Test name
Test status
Simulation time 61653846 ps
CPU time 0.86 seconds
Started Sep 18 07:45:47 PM UTC 24
Finished Sep 18 07:45:49 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151452634 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1151452634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.516300175
Short name T587
Test name
Test status
Simulation time 461918064 ps
CPU time 3.6 seconds
Started Sep 18 07:45:49 PM UTC 24
Finished Sep 18 07:45:54 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516300175 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.516300175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2897988083
Short name T583
Test name
Test status
Simulation time 68760063 ps
CPU time 4.57 seconds
Started Sep 18 07:45:46 PM UTC 24
Finished Sep 18 07:45:52 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897988083 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2897988083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.71689977
Short name T582
Test name
Test status
Simulation time 186397440 ps
CPU time 2.42 seconds
Started Sep 18 07:45:47 PM UTC 24
Finished Sep 18 07:45:51 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71689977 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.71689977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3906012015
Short name T647
Test name
Test status
Simulation time 51437595185 ps
CPU time 624.69 seconds
Started Sep 18 07:45:52 PM UTC 24
Finished Sep 18 07:56:24 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3906012015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.3906012015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.2814079230
Short name T585
Test name
Test status
Simulation time 81680818 ps
CPU time 1.11 seconds
Started Sep 18 07:45:51 PM UTC 24
Finished Sep 18 07:45:53 PM UTC 24
Peak memory 206276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814079230 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2814079230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.2524292615
Short name T584
Test name
Test status
Simulation time 23916359 ps
CPU time 0.7 seconds
Started Sep 18 07:45:51 PM UTC 24
Finished Sep 18 07:45:52 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524292615 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2524292615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2751392572
Short name T589
Test name
Test status
Simulation time 283951175 ps
CPU time 2.44 seconds
Started Sep 18 07:45:52 PM UTC 24
Finished Sep 18 07:45:55 PM UTC 24
Peak memory 206800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751392572 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.2751392572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3375901000
Short name T586
Test name
Test status
Simulation time 51001023 ps
CPU time 1.93 seconds
Started Sep 18 07:45:50 PM UTC 24
Finished Sep 18 07:45:54 PM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375901000 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3375901000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3416057417
Short name T588
Test name
Test status
Simulation time 320435210 ps
CPU time 2.52 seconds
Started Sep 18 07:45:51 PM UTC 24
Finished Sep 18 07:45:54 PM UTC 24
Peak memory 206716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416057417 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3416057417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1029864905
Short name T597
Test name
Test status
Simulation time 84461420 ps
CPU time 4.47 seconds
Started Sep 18 07:45:55 PM UTC 24
Finished Sep 18 07:46:01 PM UTC 24
Peak memory 206912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1029864905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.1029864905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.562181112
Short name T592
Test name
Test status
Simulation time 20855865 ps
CPU time 0.99 seconds
Started Sep 18 07:45:55 PM UTC 24
Finished Sep 18 07:45:57 PM UTC 24
Peak memory 206100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562181112 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.562181112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.3422490630
Short name T590
Test name
Test status
Simulation time 18626070 ps
CPU time 0.83 seconds
Started Sep 18 07:45:54 PM UTC 24
Finished Sep 18 07:45:56 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422490630 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3422490630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.660316407
Short name T594
Test name
Test status
Simulation time 143691230 ps
CPU time 2.48 seconds
Started Sep 18 07:45:55 PM UTC 24
Finished Sep 18 07:45:59 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660316407 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.660316407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.910864993
Short name T591
Test name
Test status
Simulation time 38737907 ps
CPU time 2.66 seconds
Started Sep 18 07:45:53 PM UTC 24
Finished Sep 18 07:45:57 PM UTC 24
Peak memory 206828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910864993 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.910864993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.1356320704
Short name T593
Test name
Test status
Simulation time 1753473552 ps
CPU time 4.56 seconds
Started Sep 18 07:45:53 PM UTC 24
Finished Sep 18 07:45:59 PM UTC 24
Peak memory 206844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356320704 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1356320704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.181755941
Short name T602
Test name
Test status
Simulation time 33577935 ps
CPU time 3.29 seconds
Started Sep 18 07:46:00 PM UTC 24
Finished Sep 18 07:46:04 PM UTC 24
Peak memory 206824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=181755941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_r
eset.181755941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1313710143
Short name T596
Test name
Test status
Simulation time 35385313 ps
CPU time 1.28 seconds
Started Sep 18 07:45:57 PM UTC 24
Finished Sep 18 07:46:00 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313710143 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1313710143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.3452668088
Short name T595
Test name
Test status
Simulation time 59390745 ps
CPU time 0.84 seconds
Started Sep 18 07:45:57 PM UTC 24
Finished Sep 18 07:45:59 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452668088 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3452668088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1962106105
Short name T599
Test name
Test status
Simulation time 216896746 ps
CPU time 1.76 seconds
Started Sep 18 07:46:00 PM UTC 24
Finished Sep 18 07:46:02 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962106105 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1962106105
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.237293642
Short name T600
Test name
Test status
Simulation time 923616250 ps
CPU time 5.19 seconds
Started Sep 18 07:45:56 PM UTC 24
Finished Sep 18 07:46:02 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237293642 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.237293642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1172852605
Short name T598
Test name
Test status
Simulation time 163314941 ps
CPU time 4.49 seconds
Started Sep 18 07:45:56 PM UTC 24
Finished Sep 18 07:46:02 PM UTC 24
Peak memory 206780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172852605 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1172852605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2398731778
Short name T606
Test name
Test status
Simulation time 67461526 ps
CPU time 1.54 seconds
Started Sep 18 07:46:04 PM UTC 24
Finished Sep 18 07:46:06 PM UTC 24
Peak memory 206052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2398731778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2398731778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2113425421
Short name T120
Test name
Test status
Simulation time 17508994 ps
CPU time 1.34 seconds
Started Sep 18 07:46:03 PM UTC 24
Finished Sep 18 07:46:05 PM UTC 24
Peak memory 206040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113425421 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2113425421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2414327377
Short name T603
Test name
Test status
Simulation time 50920559 ps
CPU time 0.89 seconds
Started Sep 18 07:46:03 PM UTC 24
Finished Sep 18 07:46:04 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414327377 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2414327377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1050756857
Short name T604
Test name
Test status
Simulation time 260602952 ps
CPU time 1.94 seconds
Started Sep 18 07:46:03 PM UTC 24
Finished Sep 18 07:46:06 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050756857 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.1050756857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1338233261
Short name T601
Test name
Test status
Simulation time 643068336 ps
CPU time 2.1 seconds
Started Sep 18 07:46:01 PM UTC 24
Finished Sep 18 07:46:04 PM UTC 24
Peak memory 206804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338233261 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1338233261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.39473488
Short name T605
Test name
Test status
Simulation time 345555111 ps
CPU time 4 seconds
Started Sep 18 07:46:01 PM UTC 24
Finished Sep 18 07:46:06 PM UTC 24
Peak memory 206752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39473488 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.39473488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.695617727
Short name T651
Test name
Test status
Simulation time 1698336448983 ps
CPU time 822.66 seconds
Started Sep 18 07:46:06 PM UTC 24
Finished Sep 18 07:59:59 PM UTC 24
Peak memory 223420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=695617727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_r
eset.695617727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.3976327599
Short name T122
Test name
Test status
Simulation time 164359931 ps
CPU time 1.11 seconds
Started Sep 18 07:46:05 PM UTC 24
Finished Sep 18 07:46:07 PM UTC 24
Peak memory 206040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976327599 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3976327599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3692611916
Short name T607
Test name
Test status
Simulation time 19013797 ps
CPU time 0.96 seconds
Started Sep 18 07:46:05 PM UTC 24
Finished Sep 18 07:46:07 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692611916 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3692611916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2002377961
Short name T611
Test name
Test status
Simulation time 364375300 ps
CPU time 3.27 seconds
Started Sep 18 07:46:06 PM UTC 24
Finished Sep 18 07:46:10 PM UTC 24
Peak memory 206780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002377961 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.2002377961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.2439214632
Short name T608
Test name
Test status
Simulation time 134716528 ps
CPU time 2.45 seconds
Started Sep 18 07:46:04 PM UTC 24
Finished Sep 18 07:46:07 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439214632 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2439214632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.601244912
Short name T615
Test name
Test status
Simulation time 1199626742 ps
CPU time 5.82 seconds
Started Sep 18 07:46:05 PM UTC 24
Finished Sep 18 07:46:12 PM UTC 24
Peak memory 206668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601244912 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.601244912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1608082727
Short name T616
Test name
Test status
Simulation time 29392458 ps
CPU time 2.67 seconds
Started Sep 18 07:46:10 PM UTC 24
Finished Sep 18 07:46:13 PM UTC 24
Peak memory 215128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1608082727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.1608082727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2623143318
Short name T123
Test name
Test status
Simulation time 26900430 ps
CPU time 1.19 seconds
Started Sep 18 07:46:08 PM UTC 24
Finished Sep 18 07:46:11 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623143318 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2623143318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.479039804
Short name T610
Test name
Test status
Simulation time 21658956 ps
CPU time 0.91 seconds
Started Sep 18 07:46:07 PM UTC 24
Finished Sep 18 07:46:09 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479039804 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.479039804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.563576880
Short name T613
Test name
Test status
Simulation time 217473930 ps
CPU time 1.94 seconds
Started Sep 18 07:46:09 PM UTC 24
Finished Sep 18 07:46:11 PM UTC 24
Peak memory 205832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563576880 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.563576880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.4021190238
Short name T609
Test name
Test status
Simulation time 52493484 ps
CPU time 1.82 seconds
Started Sep 18 07:46:06 PM UTC 24
Finished Sep 18 07:46:09 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021190238 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.4021190238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1217351213
Short name T612
Test name
Test status
Simulation time 56636264 ps
CPU time 2.31 seconds
Started Sep 18 07:46:07 PM UTC 24
Finished Sep 18 07:46:11 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217351213 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1217351213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3389266062
Short name T538
Test name
Test status
Simulation time 315061423 ps
CPU time 3.17 seconds
Started Sep 18 07:45:00 PM UTC 24
Finished Sep 18 07:45:04 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389266062 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3389266062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1802834765
Short name T541
Test name
Test status
Simulation time 705541182 ps
CPU time 11.95 seconds
Started Sep 18 07:45:00 PM UTC 24
Finished Sep 18 07:45:13 PM UTC 24
Peak memory 206740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802834765 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1802834765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2071082094
Short name T111
Test name
Test status
Simulation time 172579993 ps
CPU time 1.3 seconds
Started Sep 18 07:45:00 PM UTC 24
Finished Sep 18 07:45:02 PM UTC 24
Peak memory 205956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071082094 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2071082094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.422509960
Short name T70
Test name
Test status
Simulation time 41917301 ps
CPU time 2.24 seconds
Started Sep 18 07:45:00 PM UTC 24
Finished Sep 18 07:45:03 PM UTC 24
Peak memory 206856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=422509960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_re
set.422509960
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.215887254
Short name T537
Test name
Test status
Simulation time 136297474 ps
CPU time 1.3 seconds
Started Sep 18 07:45:00 PM UTC 24
Finished Sep 18 07:45:02 PM UTC 24
Peak memory 206152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215887254 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.215887254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.3704400792
Short name T536
Test name
Test status
Simulation time 233788381 ps
CPU time 0.92 seconds
Started Sep 18 07:44:57 PM UTC 24
Finished Sep 18 07:44:59 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704400792 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3704400792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2561051200
Short name T127
Test name
Test status
Simulation time 38436133 ps
CPU time 1.6 seconds
Started Sep 18 07:45:00 PM UTC 24
Finished Sep 18 07:45:03 PM UTC 24
Peak memory 206004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561051200 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.2561051200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.2649050011
Short name T69
Test name
Test status
Simulation time 761062529 ps
CPU time 2.23 seconds
Started Sep 18 07:44:53 PM UTC 24
Finished Sep 18 07:44:56 PM UTC 24
Peak memory 206912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649050011 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2649050011
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.1172413865
Short name T62
Test name
Test status
Simulation time 410334800 ps
CPU time 4.38 seconds
Started Sep 18 07:44:53 PM UTC 24
Finished Sep 18 07:44:58 PM UTC 24
Peak memory 206768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172413865 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1172413865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2589211160
Short name T614
Test name
Test status
Simulation time 13422427 ps
CPU time 0.89 seconds
Started Sep 18 07:46:10 PM UTC 24
Finished Sep 18 07:46:12 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589211160 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2589211160
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1421782952
Short name T618
Test name
Test status
Simulation time 60061234 ps
CPU time 0.94 seconds
Started Sep 18 07:46:12 PM UTC 24
Finished Sep 18 07:46:14 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421782952 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1421782952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3386721884
Short name T619
Test name
Test status
Simulation time 11353091 ps
CPU time 0.94 seconds
Started Sep 18 07:46:12 PM UTC 24
Finished Sep 18 07:46:14 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386721884 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3386721884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1436203336
Short name T617
Test name
Test status
Simulation time 46070497 ps
CPU time 0.78 seconds
Started Sep 18 07:46:12 PM UTC 24
Finished Sep 18 07:46:14 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436203336 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1436203336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3486524383
Short name T621
Test name
Test status
Simulation time 16335456 ps
CPU time 0.98 seconds
Started Sep 18 07:46:14 PM UTC 24
Finished Sep 18 07:46:15 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486524383 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3486524383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1940822657
Short name T622
Test name
Test status
Simulation time 18792961 ps
CPU time 0.92 seconds
Started Sep 18 07:46:14 PM UTC 24
Finished Sep 18 07:46:15 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940822657 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1940822657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2733393211
Short name T620
Test name
Test status
Simulation time 24716624 ps
CPU time 0.84 seconds
Started Sep 18 07:46:14 PM UTC 24
Finished Sep 18 07:46:15 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733393211 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2733393211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.4057573283
Short name T623
Test name
Test status
Simulation time 13663330 ps
CPU time 0.93 seconds
Started Sep 18 07:46:14 PM UTC 24
Finished Sep 18 07:46:16 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057573283 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4057573283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3418773408
Short name T624
Test name
Test status
Simulation time 13547642 ps
CPU time 0.88 seconds
Started Sep 18 07:46:15 PM UTC 24
Finished Sep 18 07:46:17 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418773408 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3418773408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.1522759419
Short name T625
Test name
Test status
Simulation time 17366893 ps
CPU time 0.85 seconds
Started Sep 18 07:46:15 PM UTC 24
Finished Sep 18 07:46:17 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522759419 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1522759419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1348593406
Short name T116
Test name
Test status
Simulation time 6285930761 ps
CPU time 12.89 seconds
Started Sep 18 07:45:07 PM UTC 24
Finished Sep 18 07:45:21 PM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348593406 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1348593406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.1794753756
Short name T114
Test name
Test status
Simulation time 447808298 ps
CPU time 6.91 seconds
Started Sep 18 07:45:05 PM UTC 24
Finished Sep 18 07:45:13 PM UTC 24
Peak memory 207116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794753756 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1794753756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.1181373826
Short name T112
Test name
Test status
Simulation time 29030142 ps
CPU time 1.27 seconds
Started Sep 18 07:45:04 PM UTC 24
Finished Sep 18 07:45:07 PM UTC 24
Peak memory 206220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181373826 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1181373826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2139836720
Short name T540
Test name
Test status
Simulation time 140090426 ps
CPU time 2.02 seconds
Started Sep 18 07:45:08 PM UTC 24
Finished Sep 18 07:45:11 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2139836720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.2139836720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.1005463884
Short name T113
Test name
Test status
Simulation time 16156384 ps
CPU time 1.31 seconds
Started Sep 18 07:45:05 PM UTC 24
Finished Sep 18 07:45:07 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005463884 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1005463884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3959570652
Short name T539
Test name
Test status
Simulation time 20303929 ps
CPU time 0.92 seconds
Started Sep 18 07:45:04 PM UTC 24
Finished Sep 18 07:45:06 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959570652 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3959570652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.864486930
Short name T128
Test name
Test status
Simulation time 119381874 ps
CPU time 3.75 seconds
Started Sep 18 07:45:08 PM UTC 24
Finished Sep 18 07:45:13 PM UTC 24
Peak memory 206792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864486930 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.864486930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.3437231869
Short name T65
Test name
Test status
Simulation time 55120659 ps
CPU time 4.01 seconds
Started Sep 18 07:45:03 PM UTC 24
Finished Sep 18 07:45:08 PM UTC 24
Peak memory 206836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437231869 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3437231869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.3225357514
Short name T95
Test name
Test status
Simulation time 227076574 ps
CPU time 5.32 seconds
Started Sep 18 07:45:04 PM UTC 24
Finished Sep 18 07:45:11 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225357514 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3225357514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.215042773
Short name T626
Test name
Test status
Simulation time 27614399 ps
CPU time 0.87 seconds
Started Sep 18 07:46:15 PM UTC 24
Finished Sep 18 07:46:17 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215042773 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.215042773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.2681181592
Short name T627
Test name
Test status
Simulation time 41777948 ps
CPU time 0.88 seconds
Started Sep 18 07:46:15 PM UTC 24
Finished Sep 18 07:46:17 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681181592 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2681181592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.2139954355
Short name T628
Test name
Test status
Simulation time 16740630 ps
CPU time 0.87 seconds
Started Sep 18 07:46:16 PM UTC 24
Finished Sep 18 07:46:18 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139954355 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2139954355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3154862640
Short name T629
Test name
Test status
Simulation time 45757678 ps
CPU time 0.87 seconds
Started Sep 18 07:46:16 PM UTC 24
Finished Sep 18 07:46:18 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154862640 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3154862640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.346143555
Short name T631
Test name
Test status
Simulation time 15574016 ps
CPU time 0.92 seconds
Started Sep 18 07:46:16 PM UTC 24
Finished Sep 18 07:46:18 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346143555 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.346143555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.2025196206
Short name T630
Test name
Test status
Simulation time 36130070 ps
CPU time 0.79 seconds
Started Sep 18 07:46:16 PM UTC 24
Finished Sep 18 07:46:18 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025196206 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2025196206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2334069215
Short name T633
Test name
Test status
Simulation time 51481692 ps
CPU time 0.9 seconds
Started Sep 18 07:46:17 PM UTC 24
Finished Sep 18 07:46:19 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334069215 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2334069215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2815796111
Short name T632
Test name
Test status
Simulation time 17535567 ps
CPU time 0.86 seconds
Started Sep 18 07:46:17 PM UTC 24
Finished Sep 18 07:46:19 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815796111 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2815796111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1391939720
Short name T635
Test name
Test status
Simulation time 111130332 ps
CPU time 0.85 seconds
Started Sep 18 07:46:17 PM UTC 24
Finished Sep 18 07:46:19 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391939720 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1391939720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3477945441
Short name T634
Test name
Test status
Simulation time 88781045 ps
CPU time 0.83 seconds
Started Sep 18 07:46:17 PM UTC 24
Finished Sep 18 07:46:19 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477945441 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3477945441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1421204482
Short name T117
Test name
Test status
Simulation time 749837849 ps
CPU time 7.03 seconds
Started Sep 18 07:45:16 PM UTC 24
Finished Sep 18 07:45:24 PM UTC 24
Peak memory 206768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421204482 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1421204482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.8982850
Short name T119
Test name
Test status
Simulation time 1096130135 ps
CPU time 14.72 seconds
Started Sep 18 07:45:14 PM UTC 24
Finished Sep 18 07:45:31 PM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8982850 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.8982850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2129613141
Short name T543
Test name
Test status
Simulation time 48651639 ps
CPU time 1.32 seconds
Started Sep 18 07:45:14 PM UTC 24
Finished Sep 18 07:45:17 PM UTC 24
Peak memory 204756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129613141 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2129613141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1391201695
Short name T545
Test name
Test status
Simulation time 35533129 ps
CPU time 1.74 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:27 PM UTC 24
Peak memory 206064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1391201695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.1391201695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.4022151030
Short name T115
Test name
Test status
Simulation time 54628737 ps
CPU time 1.07 seconds
Started Sep 18 07:45:14 PM UTC 24
Finished Sep 18 07:45:17 PM UTC 24
Peak memory 205904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022151030 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4022151030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.1390660002
Short name T542
Test name
Test status
Simulation time 46524852 ps
CPU time 0.87 seconds
Started Sep 18 07:45:12 PM UTC 24
Finished Sep 18 07:45:14 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390660002 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1390660002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2258469254
Short name T129
Test name
Test status
Simulation time 42958378 ps
CPU time 1.58 seconds
Started Sep 18 07:45:16 PM UTC 24
Finished Sep 18 07:45:18 PM UTC 24
Peak memory 206164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258469254 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.2258469254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.2479532851
Short name T66
Test name
Test status
Simulation time 157081987 ps
CPU time 4.12 seconds
Started Sep 18 07:45:09 PM UTC 24
Finished Sep 18 07:45:14 PM UTC 24
Peak memory 206828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479532851 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2479532851
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1485687920
Short name T147
Test name
Test status
Simulation time 222593352 ps
CPU time 5.09 seconds
Started Sep 18 07:45:11 PM UTC 24
Finished Sep 18 07:45:17 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485687920 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1485687920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.2240696991
Short name T637
Test name
Test status
Simulation time 13500882 ps
CPU time 0.94 seconds
Started Sep 18 07:46:19 PM UTC 24
Finished Sep 18 07:46:21 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240696991 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2240696991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1326678489
Short name T636
Test name
Test status
Simulation time 82075300 ps
CPU time 0.85 seconds
Started Sep 18 07:46:19 PM UTC 24
Finished Sep 18 07:46:21 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326678489 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1326678489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.93063667
Short name T638
Test name
Test status
Simulation time 16340173 ps
CPU time 0.98 seconds
Started Sep 18 07:46:19 PM UTC 24
Finished Sep 18 07:46:21 PM UTC 24
Peak memory 202916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93063667 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.93063667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2922830279
Short name T639
Test name
Test status
Simulation time 11899702 ps
CPU time 0.88 seconds
Started Sep 18 07:46:19 PM UTC 24
Finished Sep 18 07:46:21 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922830279 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2922830279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.2160072618
Short name T641
Test name
Test status
Simulation time 12921623 ps
CPU time 0.94 seconds
Started Sep 18 07:46:20 PM UTC 24
Finished Sep 18 07:46:22 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160072618 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2160072618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1448856782
Short name T640
Test name
Test status
Simulation time 27518210 ps
CPU time 0.94 seconds
Started Sep 18 07:46:20 PM UTC 24
Finished Sep 18 07:46:22 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448856782 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1448856782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.184552307
Short name T642
Test name
Test status
Simulation time 13984060 ps
CPU time 0.95 seconds
Started Sep 18 07:46:20 PM UTC 24
Finished Sep 18 07:46:22 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184552307 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.184552307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.371320014
Short name T643
Test name
Test status
Simulation time 126208864 ps
CPU time 0.89 seconds
Started Sep 18 07:46:20 PM UTC 24
Finished Sep 18 07:46:22 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371320014 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.371320014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.258510689
Short name T644
Test name
Test status
Simulation time 14419493 ps
CPU time 0.98 seconds
Started Sep 18 07:46:21 PM UTC 24
Finished Sep 18 07:46:23 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258510689 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.258510689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1601768470
Short name T645
Test name
Test status
Simulation time 16193918 ps
CPU time 0.97 seconds
Started Sep 18 07:46:21 PM UTC 24
Finished Sep 18 07:46:23 PM UTC 24
Peak memory 202924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601768470 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1601768470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.201023018
Short name T648
Test name
Test status
Simulation time 145575613171 ps
CPU time 725.94 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:57:39 PM UTC 24
Peak memory 219408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=201023018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_re
set.201023018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.2191151843
Short name T544
Test name
Test status
Simulation time 33782565 ps
CPU time 0.78 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:26 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191151843 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2191151843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.883479444
Short name T130
Test name
Test status
Simulation time 80894788 ps
CPU time 2.14 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:28 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883479444 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.883479444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.1183902952
Short name T547
Test name
Test status
Simulation time 185485001 ps
CPU time 3.6 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:29 PM UTC 24
Peak memory 206932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183902952 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1183902952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1554580517
Short name T553
Test name
Test status
Simulation time 27054373 ps
CPU time 2.49 seconds
Started Sep 18 07:45:29 PM UTC 24
Finished Sep 18 07:45:32 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1554580517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.1554580517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3133442233
Short name T549
Test name
Test status
Simulation time 85136128 ps
CPU time 1.12 seconds
Started Sep 18 07:45:28 PM UTC 24
Finished Sep 18 07:45:30 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133442233 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3133442233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1799649966
Short name T548
Test name
Test status
Simulation time 13505622 ps
CPU time 0.88 seconds
Started Sep 18 07:45:28 PM UTC 24
Finished Sep 18 07:45:29 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799649966 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1799649966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1273691664
Short name T552
Test name
Test status
Simulation time 107686544 ps
CPU time 3.37 seconds
Started Sep 18 07:45:28 PM UTC 24
Finished Sep 18 07:45:32 PM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273691664 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.1273691664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2073173250
Short name T546
Test name
Test status
Simulation time 106808425 ps
CPU time 2.01 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:28 PM UTC 24
Peak memory 207232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073173250 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2073173250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.2359929186
Short name T150
Test name
Test status
Simulation time 550850386 ps
CPU time 5.89 seconds
Started Sep 18 07:45:24 PM UTC 24
Finished Sep 18 07:45:32 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359929186 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2359929186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2871572973
Short name T558
Test name
Test status
Simulation time 44896588 ps
CPU time 3.87 seconds
Started Sep 18 07:45:32 PM UTC 24
Finished Sep 18 07:45:37 PM UTC 24
Peak memory 215036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2871572973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.2871572973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.4290318093
Short name T121
Test name
Test status
Simulation time 15157452 ps
CPU time 1.15 seconds
Started Sep 18 07:45:31 PM UTC 24
Finished Sep 18 07:45:33 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290318093 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4290318093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1279215150
Short name T550
Test name
Test status
Simulation time 40006094 ps
CPU time 0.78 seconds
Started Sep 18 07:45:30 PM UTC 24
Finished Sep 18 07:45:32 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279215150 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1279215150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1321870716
Short name T555
Test name
Test status
Simulation time 363525543 ps
CPU time 2.72 seconds
Started Sep 18 07:45:31 PM UTC 24
Finished Sep 18 07:45:35 PM UTC 24
Peak memory 206852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321870716 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.1321870716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.2109122686
Short name T551
Test name
Test status
Simulation time 224712194 ps
CPU time 2.09 seconds
Started Sep 18 07:45:29 PM UTC 24
Finished Sep 18 07:45:32 PM UTC 24
Peak memory 206976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109122686 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2109122686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3261463899
Short name T149
Test name
Test status
Simulation time 162714391 ps
CPU time 2.84 seconds
Started Sep 18 07:45:30 PM UTC 24
Finished Sep 18 07:45:34 PM UTC 24
Peak memory 206916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261463899 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3261463899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.942312553
Short name T562
Test name
Test status
Simulation time 380632041 ps
CPU time 3.1 seconds
Started Sep 18 07:45:34 PM UTC 24
Finished Sep 18 07:45:39 PM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=942312553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_re
set.942312553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.4034652643
Short name T557
Test name
Test status
Simulation time 38270834 ps
CPU time 1.28 seconds
Started Sep 18 07:45:33 PM UTC 24
Finished Sep 18 07:45:36 PM UTC 24
Peak memory 206040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034652643 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4034652643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.743194321
Short name T556
Test name
Test status
Simulation time 12363292 ps
CPU time 0.75 seconds
Started Sep 18 07:45:33 PM UTC 24
Finished Sep 18 07:45:35 PM UTC 24
Peak memory 202852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743194321 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.743194321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3765058722
Short name T559
Test name
Test status
Simulation time 140253167 ps
CPU time 2.55 seconds
Started Sep 18 07:45:33 PM UTC 24
Finished Sep 18 07:45:37 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765058722 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.3765058722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.1815967856
Short name T560
Test name
Test status
Simulation time 567714117 ps
CPU time 4.53 seconds
Started Sep 18 07:45:32 PM UTC 24
Finished Sep 18 07:45:38 PM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815967856 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1815967856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3467205715
Short name T148
Test name
Test status
Simulation time 270942603 ps
CPU time 5.88 seconds
Started Sep 18 07:45:33 PM UTC 24
Finished Sep 18 07:45:40 PM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467205715 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3467205715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1763925925
Short name T565
Test name
Test status
Simulation time 36720017 ps
CPU time 1.82 seconds
Started Sep 18 07:45:38 PM UTC 24
Finished Sep 18 07:45:41 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1763925925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.1763925925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.509583918
Short name T564
Test name
Test status
Simulation time 107718060 ps
CPU time 1.25 seconds
Started Sep 18 07:45:37 PM UTC 24
Finished Sep 18 07:45:39 PM UTC 24
Peak memory 206036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509583918 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.509583918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1366798981
Short name T563
Test name
Test status
Simulation time 62285734 ps
CPU time 0.87 seconds
Started Sep 18 07:45:37 PM UTC 24
Finished Sep 18 07:45:39 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366798981 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1366798981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3552026611
Short name T554
Test name
Test status
Simulation time 198881713 ps
CPU time 2.71 seconds
Started Sep 18 07:45:37 PM UTC 24
Finished Sep 18 07:45:41 PM UTC 24
Peak memory 206864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552026611 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.3552026611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1497334618
Short name T561
Test name
Test status
Simulation time 361383154 ps
CPU time 2.92 seconds
Started Sep 18 07:45:35 PM UTC 24
Finished Sep 18 07:45:39 PM UTC 24
Peak memory 206984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497334618 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1497334618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.469478535
Short name T151
Test name
Test status
Simulation time 446405568 ps
CPU time 2.73 seconds
Started Sep 18 07:45:37 PM UTC 24
Finished Sep 18 07:45:41 PM UTC 24
Peak memory 207232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469478535 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.469478535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.1833860597
Short name T141
Test name
Test status
Simulation time 21346979534 ps
CPU time 54.48 seconds
Started Sep 18 07:20:39 PM UTC 24
Finished Sep 18 07:21:35 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833860597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1833860597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.1808784042
Short name T56
Test name
Test status
Simulation time 1099252898 ps
CPU time 35.51 seconds
Started Sep 18 07:20:38 PM UTC 24
Finished Sep 18 07:21:14 PM UTC 24
Peak memory 363220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808784042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1808784042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_long_msg.917174874
Short name T9
Test name
Test status
Simulation time 9793832145 ps
CPU time 25.71 seconds
Started Sep 18 07:20:38 PM UTC 24
Finished Sep 18 07:21:05 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917174874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.917174874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.889817870
Short name T184
Test name
Test status
Simulation time 34632253070 ps
CPU time 94.81 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:22:17 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889817870 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.889817870
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.87326561
Short name T197
Test name
Test status
Simulation time 12155108971 ps
CPU time 160.81 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:23:24 PM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87326561 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.87326561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.4093053992
Short name T329
Test name
Test status
Simulation time 133803776329 ps
CPU time 666.4 seconds
Started Sep 18 07:20:39 PM UTC 24
Finished Sep 18 07:31:54 PM UTC 24
Peak memory 214304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093053992 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.4093053992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.357821550
Short name T513
Test name
Test status
Simulation time 44514677358 ps
CPU time 2407.59 seconds
Started Sep 18 07:20:39 PM UTC 24
Finished Sep 18 08:01:14 PM UTC 24
Peak memory 230720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357821550 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.357821550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.185448629
Short name T509
Test name
Test status
Simulation time 84625748822 ps
CPU time 2148.06 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:56:52 PM UTC 24
Peak memory 230584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185448629 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.185448629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.2124569764
Short name T31
Test name
Test status
Simulation time 6847801028 ps
CPU time 55.8 seconds
Started Sep 18 07:20:39 PM UTC 24
Finished Sep 18 07:21:36 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124569764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2124569764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_alert_test.613181257
Short name T22
Test name
Test status
Simulation time 55653294 ps
CPU time 0.65 seconds
Started Sep 18 07:20:47 PM UTC 24
Finished Sep 18 07:20:49 PM UTC 24
Peak memory 207348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613181257 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.613181257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.4162668346
Short name T10
Test name
Test status
Simulation time 456503674 ps
CPU time 23.21 seconds
Started Sep 18 07:20:42 PM UTC 24
Finished Sep 18 07:21:06 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162668346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4162668346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.3258051226
Short name T8
Test name
Test status
Simulation time 1284417657 ps
CPU time 22.11 seconds
Started Sep 18 07:20:42 PM UTC 24
Finished Sep 18 07:21:05 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258051226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3258051226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.531670897
Short name T43
Test name
Test status
Simulation time 4036900872 ps
CPU time 88.52 seconds
Started Sep 18 07:20:42 PM UTC 24
Finished Sep 18 07:22:12 PM UTC 24
Peak memory 623680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531670897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.531670897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_error.215921120
Short name T55
Test name
Test status
Simulation time 10187866525 ps
CPU time 27.88 seconds
Started Sep 18 07:20:42 PM UTC 24
Finished Sep 18 07:21:11 PM UTC 24
Peak memory 210240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215921120 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.215921120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_long_msg.3313631996
Short name T37
Test name
Test status
Simulation time 6267757930 ps
CPU time 78.83 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:22:01 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313631996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3313631996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.258919295
Short name T27
Test name
Test status
Simulation time 320486905 ps
CPU time 1.23 seconds
Started Sep 18 07:20:47 PM UTC 24
Finished Sep 18 07:20:50 PM UTC 24
Peak memory 238212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258919295 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.258919295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_smoke.4265591893
Short name T5
Test name
Test status
Simulation time 4024903019 ps
CPU time 10.92 seconds
Started Sep 18 07:20:40 PM UTC 24
Finished Sep 18 07:20:52 PM UTC 24
Peak memory 210684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265591893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4265591893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.632661253
Short name T52
Test name
Test status
Simulation time 4058658597 ps
CPU time 46.83 seconds
Started Sep 18 07:20:43 PM UTC 24
Finished Sep 18 07:21:31 PM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632661253 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.632661253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.990140322
Short name T187
Test name
Test status
Simulation time 10177143622 ps
CPU time 98.63 seconds
Started Sep 18 07:20:44 PM UTC 24
Finished Sep 18 07:22:25 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990140322 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.990140322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.1986726279
Short name T1
Test name
Test status
Simulation time 12273411796 ps
CPU time 130.85 seconds
Started Sep 18 07:20:46 PM UTC 24
Finished Sep 18 07:22:59 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986726279 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1986726279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.618101890
Short name T159
Test name
Test status
Simulation time 142327557792 ps
CPU time 632.81 seconds
Started Sep 18 07:20:43 PM UTC 24
Finished Sep 18 07:31:24 PM UTC 24
Peak memory 214336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618101890 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.618101890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.2944202320
Short name T515
Test name
Test status
Simulation time 528586876500 ps
CPU time 2475.5 seconds
Started Sep 18 07:20:43 PM UTC 24
Finished Sep 18 08:02:26 PM UTC 24
Peak memory 230464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944202320 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2944202320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.3325158731
Short name T507
Test name
Test status
Simulation time 378268593290 ps
CPU time 2089.89 seconds
Started Sep 18 07:20:43 PM UTC 24
Finished Sep 18 07:55:56 PM UTC 24
Peak memory 224416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325158731 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3325158731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.2010125005
Short name T134
Test name
Test status
Simulation time 1861645979 ps
CPU time 66.58 seconds
Started Sep 18 07:20:42 PM UTC 24
Finished Sep 18 07:21:50 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010125005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2010125005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_alert_test.331127116
Short name T194
Test name
Test status
Simulation time 32427366 ps
CPU time 0.86 seconds
Started Sep 18 07:23:06 PM UTC 24
Finished Sep 18 07:23:08 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331127116 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.331127116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.3167109276
Short name T99
Test name
Test status
Simulation time 1487507537 ps
CPU time 96.21 seconds
Started Sep 18 07:22:51 PM UTC 24
Finished Sep 18 07:24:29 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167109276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3167109276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.1330693873
Short name T154
Test name
Test status
Simulation time 76245768 ps
CPU time 6.59 seconds
Started Sep 18 07:22:56 PM UTC 24
Finished Sep 18 07:23:04 PM UTC 24
Peak memory 225392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330693873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1330693873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_error.196631412
Short name T23
Test name
Test status
Simulation time 1125267591 ps
CPU time 21.2 seconds
Started Sep 18 07:23:01 PM UTC 24
Finished Sep 18 07:23:23 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196631412 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.196631412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_long_msg.1836638501
Short name T223
Test name
Test status
Simulation time 21092419624 ps
CPU time 162.32 seconds
Started Sep 18 07:22:51 PM UTC 24
Finished Sep 18 07:25:36 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836638501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1836638501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_smoke.573328729
Short name T162
Test name
Test status
Simulation time 1927956839 ps
CPU time 9.64 seconds
Started Sep 18 07:22:49 PM UTC 24
Finished Sep 18 07:23:00 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573328729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.573328729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_stress_all.1180524277
Short name T63
Test name
Test status
Simulation time 152721777 ps
CPU time 4.4 seconds
Started Sep 18 07:23:06 PM UTC 24
Finished Sep 18 07:23:11 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180524277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1180524277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.3031809814
Short name T137
Test name
Test status
Simulation time 640367792 ps
CPU time 9.85 seconds
Started Sep 18 07:23:01 PM UTC 24
Finished Sep 18 07:23:12 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031809814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3031809814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_alert_test.702296931
Short name T39
Test name
Test status
Simulation time 27611286 ps
CPU time 0.9 seconds
Started Sep 18 07:23:19 PM UTC 24
Finished Sep 18 07:23:21 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702296931 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.702296931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.380788895
Short name T205
Test name
Test status
Simulation time 888074727 ps
CPU time 33.09 seconds
Started Sep 18 07:23:10 PM UTC 24
Finished Sep 18 07:23:45 PM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380788895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.380788895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.1082375802
Short name T198
Test name
Test status
Simulation time 4209032404 ps
CPU time 15.45 seconds
Started Sep 18 07:23:12 PM UTC 24
Finished Sep 18 07:23:28 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082375802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1082375802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_error.1568677334
Short name T216
Test name
Test status
Simulation time 6513303135 ps
CPU time 111.76 seconds
Started Sep 18 07:23:13 PM UTC 24
Finished Sep 18 07:25:07 PM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568677334 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1568677334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_long_msg.2503222479
Short name T227
Test name
Test status
Simulation time 9470086404 ps
CPU time 153.53 seconds
Started Sep 18 07:23:08 PM UTC 24
Finished Sep 18 07:25:44 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503222479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2503222479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3097062232
Short name T503
Test name
Test status
Simulation time 64744657072 ps
CPU time 1805.27 seconds
Started Sep 18 07:23:19 PM UTC 24
Finished Sep 18 07:53:42 PM UTC 24
Peak memory 795904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097062232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3097062232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.2329639210
Short name T96
Test name
Test status
Simulation time 5056289165 ps
CPU time 61.05 seconds
Started Sep 18 07:23:15 PM UTC 24
Finished Sep 18 07:24:17 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329639210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2329639210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_alert_test.4202562202
Short name T201
Test name
Test status
Simulation time 13530886 ps
CPU time 0.9 seconds
Started Sep 18 07:23:32 PM UTC 24
Finished Sep 18 07:23:34 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202562202 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4202562202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.2859273322
Short name T208
Test name
Test status
Simulation time 1304347747 ps
CPU time 30.58 seconds
Started Sep 18 07:23:24 PM UTC 24
Finished Sep 18 07:23:56 PM UTC 24
Peak memory 218928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859273322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2859273322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.759782276
Short name T207
Test name
Test status
Simulation time 10530241668 ps
CPU time 25.61 seconds
Started Sep 18 07:23:26 PM UTC 24
Finished Sep 18 07:23:53 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759782276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.759782276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.3168837413
Short name T155
Test name
Test status
Simulation time 128750081 ps
CPU time 11.28 seconds
Started Sep 18 07:23:26 PM UTC 24
Finished Sep 18 07:23:39 PM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168837413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3168837413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_error.3072702854
Short name T199
Test name
Test status
Simulation time 17941054 ps
CPU time 1.01 seconds
Started Sep 18 07:23:27 PM UTC 24
Finished Sep 18 07:23:29 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072702854 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3072702854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2832268880
Short name T88
Test name
Test status
Simulation time 77010578056 ps
CPU time 172.29 seconds
Started Sep 18 07:23:22 PM UTC 24
Finished Sep 18 07:26:18 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832268880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2832268880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_smoke.4158758179
Short name T204
Test name
Test status
Simulation time 1814903228 ps
CPU time 20.38 seconds
Started Sep 18 07:23:22 PM UTC 24
Finished Sep 18 07:23:44 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158758179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4158758179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_stress_all.1941780678
Short name T86
Test name
Test status
Simulation time 191746636954 ps
CPU time 2121.6 seconds
Started Sep 18 07:23:31 PM UTC 24
Finished Sep 18 07:59:16 PM UTC 24
Peak memory 753216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941780678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1941780678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.1930479170
Short name T230
Test name
Test status
Simulation time 20929829735 ps
CPU time 136.86 seconds
Started Sep 18 07:23:31 PM UTC 24
Finished Sep 18 07:25:50 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930479170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1930479170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_alert_test.2404983525
Short name T209
Test name
Test status
Simulation time 24954434 ps
CPU time 0.91 seconds
Started Sep 18 07:23:56 PM UTC 24
Finished Sep 18 07:23:58 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404983525 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2404983525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.1586455981
Short name T164
Test name
Test status
Simulation time 12384829401 ps
CPU time 108.89 seconds
Started Sep 18 07:23:40 PM UTC 24
Finished Sep 18 07:25:32 PM UTC 24
Peak memory 219140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586455981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1586455981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.2504725172
Short name T102
Test name
Test status
Simulation time 5742645348 ps
CPU time 74.22 seconds
Started Sep 18 07:23:45 PM UTC 24
Finished Sep 18 07:25:01 PM UTC 24
Peak memory 219064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504725172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2504725172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.3198861941
Short name T425
Test name
Test status
Simulation time 10707725579 ps
CPU time 1009.39 seconds
Started Sep 18 07:23:41 PM UTC 24
Finished Sep 18 07:40:41 PM UTC 24
Peak memory 765504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198861941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3198861941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_error.3263849355
Short name T89
Test name
Test status
Simulation time 31152030880 ps
CPU time 149.27 seconds
Started Sep 18 07:23:47 PM UTC 24
Finished Sep 18 07:26:19 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263849355 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3263849355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_long_msg.4271019015
Short name T254
Test name
Test status
Simulation time 3617029135 ps
CPU time 210.34 seconds
Started Sep 18 07:23:40 PM UTC 24
Finished Sep 18 07:27:14 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271019015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4271019015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_smoke.3507000553
Short name T203
Test name
Test status
Simulation time 36998118 ps
CPU time 1.68 seconds
Started Sep 18 07:23:36 PM UTC 24
Finished Sep 18 07:23:39 PM UTC 24
Peak memory 208872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507000553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3507000553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_stress_all.1710783532
Short name T176
Test name
Test status
Simulation time 262640875961 ps
CPU time 1630.05 seconds
Started Sep 18 07:23:50 PM UTC 24
Finished Sep 18 07:51:18 PM UTC 24
Peak memory 742712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710783532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1710783532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.1927907781
Short name T140
Test name
Test status
Simulation time 16579248130 ps
CPU time 99.76 seconds
Started Sep 18 07:23:49 PM UTC 24
Finished Sep 18 07:25:31 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927907781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1927907781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_alert_test.4031825092
Short name T97
Test name
Test status
Simulation time 25578033 ps
CPU time 0.88 seconds
Started Sep 18 07:24:19 PM UTC 24
Finished Sep 18 07:24:21 PM UTC 24
Peak memory 207416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031825092 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4031825092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.2926534087
Short name T217
Test name
Test status
Simulation time 1254273885 ps
CPU time 63.95 seconds
Started Sep 18 07:24:04 PM UTC 24
Finished Sep 18 07:25:10 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926534087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2926534087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.2708869062
Short name T218
Test name
Test status
Simulation time 12890203480 ps
CPU time 61.4 seconds
Started Sep 18 07:24:08 PM UTC 24
Finished Sep 18 07:25:11 PM UTC 24
Peak memory 219140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708869062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2708869062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.3835629330
Short name T453
Test name
Test status
Simulation time 14203880757 ps
CPU time 1127.68 seconds
Started Sep 18 07:24:08 PM UTC 24
Finished Sep 18 07:43:07 PM UTC 24
Peak memory 781864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835629330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3835629330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_error.2714190956
Short name T253
Test name
Test status
Simulation time 21086221454 ps
CPU time 174.45 seconds
Started Sep 18 07:24:11 PM UTC 24
Finished Sep 18 07:27:09 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714190956 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2714190956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_long_msg.315875431
Short name T229
Test name
Test status
Simulation time 4924662206 ps
CPU time 109.38 seconds
Started Sep 18 07:23:58 PM UTC 24
Finished Sep 18 07:25:50 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315875431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.315875431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_smoke.441044867
Short name T212
Test name
Test status
Simulation time 478464229 ps
CPU time 11.33 seconds
Started Sep 18 07:23:58 PM UTC 24
Finished Sep 18 07:24:10 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441044867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.441044867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.4055461537
Short name T103
Test name
Test status
Simulation time 756494435 ps
CPU time 45 seconds
Started Sep 18 07:24:16 PM UTC 24
Finished Sep 18 07:25:02 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055461537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4055461537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_alert_test.2675471472
Short name T214
Test name
Test status
Simulation time 70047132 ps
CPU time 0.87 seconds
Started Sep 18 07:25:04 PM UTC 24
Finished Sep 18 07:25:06 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675471472 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2675471472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.2980310487
Short name T221
Test name
Test status
Simulation time 4031299749 ps
CPU time 46.94 seconds
Started Sep 18 07:24:32 PM UTC 24
Finished Sep 18 07:25:21 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980310487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2980310487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.1593500567
Short name T170
Test name
Test status
Simulation time 589814687 ps
CPU time 34.92 seconds
Started Sep 18 07:24:59 PM UTC 24
Finished Sep 18 07:25:36 PM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593500567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1593500567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.435950450
Short name T501
Test name
Test status
Simulation time 109298491624 ps
CPU time 1554.48 seconds
Started Sep 18 07:24:35 PM UTC 24
Finished Sep 18 07:50:46 PM UTC 24
Peak memory 779608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435950450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.435950450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_long_msg.2055844616
Short name T245
Test name
Test status
Simulation time 18004672050 ps
CPU time 129.27 seconds
Started Sep 18 07:24:32 PM UTC 24
Finished Sep 18 07:26:44 PM UTC 24
Peak memory 210520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055844616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2055844616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_smoke.3321918018
Short name T98
Test name
Test status
Simulation time 938325972 ps
CPU time 4.89 seconds
Started Sep 18 07:24:23 PM UTC 24
Finished Sep 18 07:24:29 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321918018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3321918018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_stress_all.1019886625
Short name T292
Test name
Test status
Simulation time 29643387930 ps
CPU time 313.2 seconds
Started Sep 18 07:25:02 PM UTC 24
Finished Sep 18 07:30:20 PM UTC 24
Peak memory 219304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019886625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1019886625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.1340063401
Short name T90
Test name
Test status
Simulation time 16741704782 ps
CPU time 76.5 seconds
Started Sep 18 07:25:02 PM UTC 24
Finished Sep 18 07:26:20 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340063401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1340063401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_alert_test.136718708
Short name T222
Test name
Test status
Simulation time 12419241 ps
CPU time 0.9 seconds
Started Sep 18 07:25:20 PM UTC 24
Finished Sep 18 07:25:22 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136718708 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.136718708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1869184070
Short name T220
Test name
Test status
Simulation time 135814870 ps
CPU time 10.72 seconds
Started Sep 18 07:25:07 PM UTC 24
Finished Sep 18 07:25:19 PM UTC 24
Peak memory 210172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869184070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1869184070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.2512044520
Short name T235
Test name
Test status
Simulation time 25435024343 ps
CPU time 51.91 seconds
Started Sep 18 07:25:09 PM UTC 24
Finished Sep 18 07:26:02 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512044520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2512044520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.1180859181
Short name T379
Test name
Test status
Simulation time 3306731664 ps
CPU time 656.71 seconds
Started Sep 18 07:25:09 PM UTC 24
Finished Sep 18 07:36:13 PM UTC 24
Peak memory 750968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180859181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1180859181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_error.3158805659
Short name T219
Test name
Test status
Simulation time 1051689806 ps
CPU time 5.39 seconds
Started Sep 18 07:25:12 PM UTC 24
Finished Sep 18 07:25:18 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158805659 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3158805659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_long_msg.3945591833
Short name T233
Test name
Test status
Simulation time 14425615039 ps
CPU time 51.05 seconds
Started Sep 18 07:25:04 PM UTC 24
Finished Sep 18 07:25:57 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945591833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3945591833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_smoke.2702036987
Short name T215
Test name
Test status
Simulation time 25943758 ps
CPU time 2.12 seconds
Started Sep 18 07:25:04 PM UTC 24
Finished Sep 18 07:25:07 PM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702036987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2702036987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2305261934
Short name T526
Test name
Test status
Simulation time 64403400161 ps
CPU time 4359.35 seconds
Started Sep 18 07:25:19 PM UTC 24
Finished Sep 18 08:38:46 PM UTC 24
Peak memory 830976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305261934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2305261934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2426100129
Short name T241
Test name
Test status
Simulation time 6888449281 ps
CPU time 78.77 seconds
Started Sep 18 07:25:13 PM UTC 24
Finished Sep 18 07:26:34 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426100129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2426100129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_alert_test.3194049923
Short name T228
Test name
Test status
Simulation time 12274473 ps
CPU time 0.85 seconds
Started Sep 18 07:25:47 PM UTC 24
Finished Sep 18 07:25:48 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194049923 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3194049923
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.1989213060
Short name T240
Test name
Test status
Simulation time 3425502623 ps
CPU time 54.86 seconds
Started Sep 18 07:25:34 PM UTC 24
Finished Sep 18 07:26:31 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989213060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1989213060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.3991919213
Short name T231
Test name
Test status
Simulation time 1109960168 ps
CPU time 16.84 seconds
Started Sep 18 07:25:36 PM UTC 24
Finished Sep 18 07:25:54 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991919213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3991919213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.4116459980
Short name T224
Test name
Test status
Simulation time 57466960 ps
CPU time 1.05 seconds
Started Sep 18 07:25:34 PM UTC 24
Finished Sep 18 07:25:36 PM UTC 24
Peak memory 208340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116459980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4116459980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_error.4027878555
Short name T73
Test name
Test status
Simulation time 49468615537 ps
CPU time 209.6 seconds
Started Sep 18 07:25:38 PM UTC 24
Finished Sep 18 07:29:11 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027878555 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4027878555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_long_msg.4177900672
Short name T243
Test name
Test status
Simulation time 5633025924 ps
CPU time 73.88 seconds
Started Sep 18 07:25:23 PM UTC 24
Finished Sep 18 07:26:39 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177900672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4177900672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_smoke.2847084407
Short name T226
Test name
Test status
Simulation time 5124566579 ps
CPU time 20.23 seconds
Started Sep 18 07:25:22 PM UTC 24
Finished Sep 18 07:25:44 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847084407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2847084407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.3555945077
Short name T92
Test name
Test status
Simulation time 3319633831 ps
CPU time 42.14 seconds
Started Sep 18 07:25:38 PM UTC 24
Finished Sep 18 07:26:22 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555945077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3555945077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_alert_test.1340501628
Short name T237
Test name
Test status
Simulation time 12879825 ps
CPU time 0.91 seconds
Started Sep 18 07:26:03 PM UTC 24
Finished Sep 18 07:26:05 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340501628 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1340501628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.3056007338
Short name T25
Test name
Test status
Simulation time 760021142 ps
CPU time 27.79 seconds
Started Sep 18 07:25:52 PM UTC 24
Finished Sep 18 07:26:21 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056007338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3056007338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.833537029
Short name T238
Test name
Test status
Simulation time 974937331 ps
CPU time 9.4 seconds
Started Sep 18 07:25:55 PM UTC 24
Finished Sep 18 07:26:06 PM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833537029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.833537029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.441970244
Short name T481
Test name
Test status
Simulation time 25189132629 ps
CPU time 1169.97 seconds
Started Sep 18 07:25:52 PM UTC 24
Finished Sep 18 07:45:35 PM UTC 24
Peak memory 728312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441970244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.441970244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_error.2890150456
Short name T269
Test name
Test status
Simulation time 9162959732 ps
CPU time 139.28 seconds
Started Sep 18 07:25:56 PM UTC 24
Finished Sep 18 07:28:18 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890150456 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2890150456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_long_msg.205115600
Short name T232
Test name
Test status
Simulation time 97834133 ps
CPU time 5.47 seconds
Started Sep 18 07:25:49 PM UTC 24
Finished Sep 18 07:25:55 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205115600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.205115600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_smoke.1531944200
Short name T236
Test name
Test status
Simulation time 3622745691 ps
CPU time 15.59 seconds
Started Sep 18 07:25:47 PM UTC 24
Finished Sep 18 07:26:03 PM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531944200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1531944200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2871972536
Short name T522
Test name
Test status
Simulation time 127396175334 ps
CPU time 3339.63 seconds
Started Sep 18 07:26:00 PM UTC 24
Finished Sep 18 08:22:17 PM UTC 24
Peak memory 810228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871972536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2871972536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.2383504612
Short name T249
Test name
Test status
Simulation time 8139643264 ps
CPU time 53.27 seconds
Started Sep 18 07:25:58 PM UTC 24
Finished Sep 18 07:26:53 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383504612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2383504612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_alert_test.864730301
Short name T93
Test name
Test status
Simulation time 19849469 ps
CPU time 0.86 seconds
Started Sep 18 07:26:22 PM UTC 24
Finished Sep 18 07:26:24 PM UTC 24
Peak memory 207412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864730301 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.864730301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.1222429500
Short name T259
Test name
Test status
Simulation time 1351182899 ps
CPU time 85.83 seconds
Started Sep 18 07:26:07 PM UTC 24
Finished Sep 18 07:27:34 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222429500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1222429500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.788873911
Short name T242
Test name
Test status
Simulation time 5627284278 ps
CPU time 18.64 seconds
Started Sep 18 07:26:17 PM UTC 24
Finished Sep 18 07:26:37 PM UTC 24
Peak memory 218976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788873911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.788873911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.143149704
Short name T297
Test name
Test status
Simulation time 28742090906 ps
CPU time 257.54 seconds
Started Sep 18 07:26:16 PM UTC 24
Finished Sep 18 07:30:37 PM UTC 24
Peak memory 486648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143149704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.143149704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_error.2445188426
Short name T264
Test name
Test status
Simulation time 6929019064 ps
CPU time 92.96 seconds
Started Sep 18 07:26:20 PM UTC 24
Finished Sep 18 07:27:55 PM UTC 24
Peak memory 210560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445188426 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2445188426
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_long_msg.1934756606
Short name T295
Test name
Test status
Simulation time 16258623975 ps
CPU time 256.06 seconds
Started Sep 18 07:26:07 PM UTC 24
Finished Sep 18 07:30:27 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934756606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1934756606
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_smoke.3292466787
Short name T87
Test name
Test status
Simulation time 226108960 ps
CPU time 8.9 seconds
Started Sep 18 07:26:04 PM UTC 24
Finished Sep 18 07:26:14 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292466787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3292466787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_stress_all.1254410584
Short name T94
Test name
Test status
Simulation time 18820659 ps
CPU time 0.92 seconds
Started Sep 18 07:26:22 PM UTC 24
Finished Sep 18 07:26:24 PM UTC 24
Peak memory 207360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254410584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1254410584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.3130973725
Short name T105
Test name
Test status
Simulation time 35109661488 ps
CPU time 35.17 seconds
Started Sep 18 07:26:20 PM UTC 24
Finished Sep 18 07:26:56 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130973725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3130973725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_alert_test.1499198815
Short name T53
Test name
Test status
Simulation time 25056787 ps
CPU time 0.79 seconds
Started Sep 18 07:20:53 PM UTC 24
Finished Sep 18 07:20:55 PM UTC 24
Peak memory 205364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499198815 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1499198815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.1648193835
Short name T38
Test name
Test status
Simulation time 1251341558 ps
CPU time 72.44 seconds
Started Sep 18 07:20:47 PM UTC 24
Finished Sep 18 07:22:02 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648193835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1648193835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.3475900610
Short name T257
Test name
Test status
Simulation time 9074327320 ps
CPU time 395.83 seconds
Started Sep 18 07:20:48 PM UTC 24
Finished Sep 18 07:27:28 PM UTC 24
Peak memory 679484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475900610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3475900610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_error.2656706564
Short name T11
Test name
Test status
Simulation time 1381860401 ps
CPU time 12.46 seconds
Started Sep 18 07:20:49 PM UTC 24
Finished Sep 18 07:21:02 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656706564 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2656706564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_long_msg.4036182433
Short name T166
Test name
Test status
Simulation time 10950304039 ps
CPU time 105.56 seconds
Started Sep 18 07:20:47 PM UTC 24
Finished Sep 18 07:22:35 PM UTC 24
Peak memory 210520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036182433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4036182433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.2218814920
Short name T28
Test name
Test status
Simulation time 63391667 ps
CPU time 1.04 seconds
Started Sep 18 07:20:51 PM UTC 24
Finished Sep 18 07:20:53 PM UTC 24
Peak memory 238204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218814920 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2218814920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_smoke.1864925885
Short name T4
Test name
Test status
Simulation time 175893587 ps
CPU time 1.99 seconds
Started Sep 18 07:20:47 PM UTC 24
Finished Sep 18 07:20:50 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864925885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1864925885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_stress_all.1766644485
Short name T280
Test name
Test status
Simulation time 150821025999 ps
CPU time 483.23 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 07:29:01 PM UTC 24
Peak memory 273688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766644485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1766644485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.2300946664
Short name T48
Test name
Test status
Simulation time 13843355708 ps
CPU time 80.02 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 07:22:12 PM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300946664 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2300946664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.2472182237
Short name T135
Test name
Test status
Simulation time 9012192112 ps
CPU time 58.44 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 07:21:50 PM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472182237 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2472182237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.3135529635
Short name T195
Test name
Test status
Simulation time 11526389337 ps
CPU time 137.23 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 07:23:10 PM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135529635 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3135529635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.3002329961
Short name T157
Test name
Test status
Simulation time 21127305586 ps
CPU time 608.19 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 07:31:06 PM UTC 24
Peak memory 214332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002329961 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3002329961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1764277662
Short name T512
Test name
Test status
Simulation time 37985331225 ps
CPU time 2380.8 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 08:01:00 PM UTC 24
Peak memory 224304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764277662 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1764277662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1439560097
Short name T514
Test name
Test status
Simulation time 558802424019 ps
CPU time 2399.51 seconds
Started Sep 18 07:20:50 PM UTC 24
Finished Sep 18 08:01:16 PM UTC 24
Peak memory 230512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439560097 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1439560097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.2869890038
Short name T132
Test name
Test status
Simulation time 16531353563 ps
CPU time 53.18 seconds
Started Sep 18 07:20:49 PM UTC 24
Finished Sep 18 07:21:43 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869890038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2869890038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_alert_test.1833879190
Short name T244
Test name
Test status
Simulation time 13407892 ps
CPU time 0.85 seconds
Started Sep 18 07:26:38 PM UTC 24
Finished Sep 18 07:26:40 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833879190 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1833879190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.2562706113
Short name T260
Test name
Test status
Simulation time 1008413274 ps
CPU time 73.9 seconds
Started Sep 18 07:26:25 PM UTC 24
Finished Sep 18 07:27:41 PM UTC 24
Peak memory 210292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562706113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2562706113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3008544504
Short name T252
Test name
Test status
Simulation time 2186975435 ps
CPU time 35.2 seconds
Started Sep 18 07:26:26 PM UTC 24
Finished Sep 18 07:27:03 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008544504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3008544504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.1524692685
Short name T311
Test name
Test status
Simulation time 5833451507 ps
CPU time 288.67 seconds
Started Sep 18 07:26:25 PM UTC 24
Finished Sep 18 07:31:18 PM UTC 24
Peak memory 700040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524692685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1524692685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_error.1279117714
Short name T255
Test name
Test status
Simulation time 11615743122 ps
CPU time 42.94 seconds
Started Sep 18 07:26:30 PM UTC 24
Finished Sep 18 07:27:14 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279117714 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1279117714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_long_msg.2205270624
Short name T274
Test name
Test status
Simulation time 11621096229 ps
CPU time 132.14 seconds
Started Sep 18 07:26:24 PM UTC 24
Finished Sep 18 07:28:38 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205270624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2205270624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_smoke.1596715867
Short name T161
Test name
Test status
Simulation time 696703216 ps
CPU time 12.41 seconds
Started Sep 18 07:26:24 PM UTC 24
Finished Sep 18 07:26:37 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596715867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1596715867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_stress_all.1005750206
Short name T504
Test name
Test status
Simulation time 188381182963 ps
CPU time 1613.88 seconds
Started Sep 18 07:26:35 PM UTC 24
Finished Sep 18 07:53:47 PM UTC 24
Peak memory 773704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005750206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1005750206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3154101920
Short name T266
Test name
Test status
Simulation time 8356455392 ps
CPU time 88.23 seconds
Started Sep 18 07:26:32 PM UTC 24
Finished Sep 18 07:28:03 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154101920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3154101920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_alert_test.3097261939
Short name T250
Test name
Test status
Simulation time 14017053 ps
CPU time 0.84 seconds
Started Sep 18 07:26:58 PM UTC 24
Finished Sep 18 07:27:00 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097261939 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3097261939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.261060054
Short name T268
Test name
Test status
Simulation time 1171019514 ps
CPU time 81.69 seconds
Started Sep 18 07:26:42 PM UTC 24
Finished Sep 18 07:28:07 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261060054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.261060054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.440740926
Short name T248
Test name
Test status
Simulation time 244484611 ps
CPU time 3.28 seconds
Started Sep 18 07:26:47 PM UTC 24
Finished Sep 18 07:26:52 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440740926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.440740926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3625873409
Short name T76
Test name
Test status
Simulation time 4798971078 ps
CPU time 163.39 seconds
Started Sep 18 07:26:45 PM UTC 24
Finished Sep 18 07:29:31 PM UTC 24
Peak memory 408888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625873409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3625873409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_error.804678658
Short name T293
Test name
Test status
Simulation time 178563751028 ps
CPU time 203.08 seconds
Started Sep 18 07:26:53 PM UTC 24
Finished Sep 18 07:30:20 PM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804678658 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.804678658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_long_msg.64810209
Short name T273
Test name
Test status
Simulation time 29538361318 ps
CPU time 112.14 seconds
Started Sep 18 07:26:41 PM UTC 24
Finished Sep 18 07:28:35 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64810209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.64810209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_smoke.642962757
Short name T246
Test name
Test status
Simulation time 287281210 ps
CPU time 7.43 seconds
Started Sep 18 07:26:38 PM UTC 24
Finished Sep 18 07:26:47 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642962757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.642962757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_stress_all.621522601
Short name T79
Test name
Test status
Simulation time 47371195498 ps
CPU time 188.48 seconds
Started Sep 18 07:26:53 PM UTC 24
Finished Sep 18 07:30:05 PM UTC 24
Peak memory 221288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621522601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.621522601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.3935501422
Short name T256
Test name
Test status
Simulation time 36670777719 ps
CPU time 30.51 seconds
Started Sep 18 07:26:53 PM UTC 24
Finished Sep 18 07:27:25 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935501422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3935501422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_alert_test.465684036
Short name T258
Test name
Test status
Simulation time 24406877 ps
CPU time 0.87 seconds
Started Sep 18 07:27:31 PM UTC 24
Finished Sep 18 07:27:33 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465684036 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.465684036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.3519131824
Short name T271
Test name
Test status
Simulation time 2928124338 ps
CPU time 78.61 seconds
Started Sep 18 07:27:04 PM UTC 24
Finished Sep 18 07:28:24 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519131824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3519131824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.2986781713
Short name T168
Test name
Test status
Simulation time 5487526846 ps
CPU time 100.02 seconds
Started Sep 18 07:27:16 PM UTC 24
Finished Sep 18 07:28:58 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986781713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2986781713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.2843156451
Short name T346
Test name
Test status
Simulation time 8854162961 ps
CPU time 362.72 seconds
Started Sep 18 07:27:10 PM UTC 24
Finished Sep 18 07:33:18 PM UTC 24
Peak memory 734736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843156451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2843156451
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_error.1005641758
Short name T296
Test name
Test status
Simulation time 13326847973 ps
CPU time 193.23 seconds
Started Sep 18 07:27:16 PM UTC 24
Finished Sep 18 07:30:33 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005641758 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1005641758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_long_msg.118180327
Short name T278
Test name
Test status
Simulation time 7406032056 ps
CPU time 111.27 seconds
Started Sep 18 07:27:04 PM UTC 24
Finished Sep 18 07:28:57 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118180327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.118180327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_smoke.2408331591
Short name T251
Test name
Test status
Simulation time 23460954 ps
CPU time 1.1 seconds
Started Sep 18 07:27:01 PM UTC 24
Finished Sep 18 07:27:03 PM UTC 24
Peak memory 207348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408331591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2408331591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_stress_all.1116126442
Short name T326
Test name
Test status
Simulation time 79024216791 ps
CPU time 255.23 seconds
Started Sep 18 07:27:29 PM UTC 24
Finished Sep 18 07:31:48 PM UTC 24
Peak memory 219016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116126442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1116126442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.3870569799
Short name T275
Test name
Test status
Simulation time 11969510300 ps
CPU time 69.19 seconds
Started Sep 18 07:27:29 PM UTC 24
Finished Sep 18 07:28:40 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870569799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3870569799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_alert_test.4025673417
Short name T267
Test name
Test status
Simulation time 36311202 ps
CPU time 0.9 seconds
Started Sep 18 07:28:04 PM UTC 24
Finished Sep 18 07:28:06 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025673417 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4025673417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.3582116638
Short name T72
Test name
Test status
Simulation time 5368266296 ps
CPU time 83.09 seconds
Started Sep 18 07:27:42 PM UTC 24
Finished Sep 18 07:29:07 PM UTC 24
Peak memory 221108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582116638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3582116638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.2602999827
Short name T265
Test name
Test status
Simulation time 2335187260 ps
CPU time 10.36 seconds
Started Sep 18 07:27:49 PM UTC 24
Finished Sep 18 07:28:00 PM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602999827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2602999827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.4197708349
Short name T420
Test name
Test status
Simulation time 4638738707 ps
CPU time 736.63 seconds
Started Sep 18 07:27:49 PM UTC 24
Finished Sep 18 07:40:13 PM UTC 24
Peak memory 648836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197708349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4197708349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_error.260998747
Short name T302
Test name
Test status
Simulation time 13269357223 ps
CPU time 186.2 seconds
Started Sep 18 07:27:49 PM UTC 24
Finished Sep 18 07:30:58 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260998747 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.260998747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_long_msg.1410244062
Short name T294
Test name
Test status
Simulation time 10358970119 ps
CPU time 164.39 seconds
Started Sep 18 07:27:36 PM UTC 24
Finished Sep 18 07:30:23 PM UTC 24
Peak memory 219028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410244062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1410244062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_smoke.369008947
Short name T262
Test name
Test status
Simulation time 633257987 ps
CPU time 10.31 seconds
Started Sep 18 07:27:34 PM UTC 24
Finished Sep 18 07:27:46 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369008947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.369008947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_stress_all.3303554130
Short name T487
Test name
Test status
Simulation time 57791072206 ps
CPU time 1102.1 seconds
Started Sep 18 07:28:02 PM UTC 24
Finished Sep 18 07:46:37 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303554130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3303554130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.488334388
Short name T282
Test name
Test status
Simulation time 4007911111 ps
CPU time 65.62 seconds
Started Sep 18 07:27:55 PM UTC 24
Finished Sep 18 07:29:03 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488334388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.488334388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_alert_test.1839001223
Short name T276
Test name
Test status
Simulation time 21349998 ps
CPU time 0.85 seconds
Started Sep 18 07:28:42 PM UTC 24
Finished Sep 18 07:28:44 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839001223 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1839001223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.1173829961
Short name T272
Test name
Test status
Simulation time 391384812 ps
CPU time 7.43 seconds
Started Sep 18 07:28:20 PM UTC 24
Finished Sep 18 07:28:29 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173829961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1173829961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.1899201543
Short name T74
Test name
Test status
Simulation time 746153629 ps
CPU time 50.8 seconds
Started Sep 18 07:28:26 PM UTC 24
Finished Sep 18 07:29:18 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899201543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1899201543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.873047157
Short name T299
Test name
Test status
Simulation time 6845821161 ps
CPU time 137.95 seconds
Started Sep 18 07:28:20 PM UTC 24
Finished Sep 18 07:30:41 PM UTC 24
Peak memory 682960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873047157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.873047157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_error.3056931144
Short name T281
Test name
Test status
Simulation time 10710398521 ps
CPU time 31.53 seconds
Started Sep 18 07:28:30 PM UTC 24
Finished Sep 18 07:29:03 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056931144 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3056931144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_long_msg.2425939321
Short name T318
Test name
Test status
Simulation time 34830282675 ps
CPU time 195.63 seconds
Started Sep 18 07:28:08 PM UTC 24
Finished Sep 18 07:31:27 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425939321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2425939321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_smoke.2070205208
Short name T270
Test name
Test status
Simulation time 565504808 ps
CPU time 9.7 seconds
Started Sep 18 07:28:08 PM UTC 24
Finished Sep 18 07:28:19 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070205208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2070205208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_stress_all.2750170954
Short name T521
Test name
Test status
Simulation time 117919664479 ps
CPU time 2556.8 seconds
Started Sep 18 07:28:40 PM UTC 24
Finished Sep 18 08:11:45 PM UTC 24
Peak memory 779616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750170954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2750170954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.497206566
Short name T288
Test name
Test status
Simulation time 1573429197 ps
CPU time 95.35 seconds
Started Sep 18 07:28:37 PM UTC 24
Finished Sep 18 07:30:14 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497206566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.497206566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_alert_test.4070322913
Short name T71
Test name
Test status
Simulation time 16009121 ps
CPU time 0.82 seconds
Started Sep 18 07:29:05 PM UTC 24
Finished Sep 18 07:29:06 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070322913 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4070322913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.3949329023
Short name T46
Test name
Test status
Simulation time 744841017 ps
CPU time 51.69 seconds
Started Sep 18 07:28:59 PM UTC 24
Finished Sep 18 07:29:52 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949329023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3949329023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.2663815665
Short name T283
Test name
Test status
Simulation time 421044307 ps
CPU time 1.76 seconds
Started Sep 18 07:29:00 PM UTC 24
Finished Sep 18 07:29:03 PM UTC 24
Peak memory 208872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663815665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2663815665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.4168852540
Short name T377
Test name
Test status
Simulation time 9523845498 ps
CPU time 423.34 seconds
Started Sep 18 07:28:59 PM UTC 24
Finished Sep 18 07:36:08 PM UTC 24
Peak memory 683328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168852540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4168852540
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_error.2795593951
Short name T304
Test name
Test status
Simulation time 6692410933 ps
CPU time 114.74 seconds
Started Sep 18 07:29:03 PM UTC 24
Finished Sep 18 07:31:00 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795593951 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2795593951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_long_msg.1247301226
Short name T291
Test name
Test status
Simulation time 5455180410 ps
CPU time 85.28 seconds
Started Sep 18 07:28:51 PM UTC 24
Finished Sep 18 07:30:19 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247301226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1247301226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_smoke.2465449330
Short name T279
Test name
Test status
Simulation time 232291390 ps
CPU time 13.93 seconds
Started Sep 18 07:28:45 PM UTC 24
Finished Sep 18 07:29:00 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465449330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2465449330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_stress_all.2065665392
Short name T83
Test name
Test status
Simulation time 34779360982 ps
CPU time 905.7 seconds
Started Sep 18 07:29:04 PM UTC 24
Finished Sep 18 07:44:21 PM UTC 24
Peak memory 724492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065665392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2065665392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.455847303
Short name T106
Test name
Test status
Simulation time 9393198726 ps
CPU time 111.61 seconds
Started Sep 18 07:29:04 PM UTC 24
Finished Sep 18 07:30:58 PM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455847303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.455847303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_alert_test.3818327765
Short name T284
Test name
Test status
Simulation time 21982908 ps
CPU time 0.86 seconds
Started Sep 18 07:29:55 PM UTC 24
Finished Sep 18 07:29:57 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818327765 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3818327765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.184023549
Short name T77
Test name
Test status
Simulation time 1566225974 ps
CPU time 42.74 seconds
Started Sep 18 07:29:09 PM UTC 24
Finished Sep 18 07:29:53 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184023549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.184023549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.308372656
Short name T285
Test name
Test status
Simulation time 8503000032 ps
CPU time 44.21 seconds
Started Sep 18 07:29:19 PM UTC 24
Finished Sep 18 07:30:05 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308372656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.308372656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.1472159051
Short name T410
Test name
Test status
Simulation time 42391538077 ps
CPU time 570.92 seconds
Started Sep 18 07:29:13 PM UTC 24
Finished Sep 18 07:38:51 PM UTC 24
Peak memory 707904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472159051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1472159051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_error.2607072831
Short name T287
Test name
Test status
Simulation time 2200695434 ps
CPU time 40.79 seconds
Started Sep 18 07:29:31 PM UTC 24
Finished Sep 18 07:30:13 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607072831 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2607072831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_long_msg.3413007715
Short name T313
Test name
Test status
Simulation time 33624428973 ps
CPU time 130.2 seconds
Started Sep 18 07:29:09 PM UTC 24
Finished Sep 18 07:31:21 PM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413007715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3413007715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_smoke.2564647889
Short name T75
Test name
Test status
Simulation time 2512852903 ps
CPU time 19.74 seconds
Started Sep 18 07:29:07 PM UTC 24
Finished Sep 18 07:29:28 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564647889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2564647889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.2289383119
Short name T286
Test name
Test status
Simulation time 674173240 ps
CPU time 36.08 seconds
Started Sep 18 07:29:33 PM UTC 24
Finished Sep 18 07:30:10 PM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289383119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2289383119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_alert_test.2990561929
Short name T290
Test name
Test status
Simulation time 23531324 ps
CPU time 0.87 seconds
Started Sep 18 07:30:16 PM UTC 24
Finished Sep 18 07:30:18 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990561929 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2990561929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.2755188823
Short name T316
Test name
Test status
Simulation time 1265779823 ps
CPU time 75.4 seconds
Started Sep 18 07:30:08 PM UTC 24
Finished Sep 18 07:31:25 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755188823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2755188823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.3830776770
Short name T171
Test name
Test status
Simulation time 4748247667 ps
CPU time 66.96 seconds
Started Sep 18 07:30:08 PM UTC 24
Finished Sep 18 07:31:17 PM UTC 24
Peak memory 219028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830776770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3830776770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.1578786050
Short name T454
Test name
Test status
Simulation time 7964517479 ps
CPU time 774.4 seconds
Started Sep 18 07:30:08 PM UTC 24
Finished Sep 18 07:43:11 PM UTC 24
Peak memory 546052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578786050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1578786050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_error.3920337818
Short name T343
Test name
Test status
Simulation time 21369844831 ps
CPU time 178.12 seconds
Started Sep 18 07:30:11 PM UTC 24
Finished Sep 18 07:33:13 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920337818 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3920337818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_long_msg.2873335512
Short name T306
Test name
Test status
Simulation time 13972426244 ps
CPU time 66.01 seconds
Started Sep 18 07:29:58 PM UTC 24
Finished Sep 18 07:31:06 PM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873335512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2873335512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_smoke.3844329030
Short name T289
Test name
Test status
Simulation time 9628247191 ps
CPU time 18.51 seconds
Started Sep 18 07:29:55 PM UTC 24
Finished Sep 18 07:30:15 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844329030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3844329030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_stress_all.2837825201
Short name T360
Test name
Test status
Simulation time 26603438147 ps
CPU time 266.73 seconds
Started Sep 18 07:30:16 PM UTC 24
Finished Sep 18 07:34:47 PM UTC 24
Peak memory 226844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837825201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2837825201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.638812694
Short name T328
Test name
Test status
Simulation time 1865007459 ps
CPU time 96.63 seconds
Started Sep 18 07:30:14 PM UTC 24
Finished Sep 18 07:31:53 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638812694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.638812694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1884326889
Short name T300
Test name
Test status
Simulation time 21220733 ps
CPU time 0.9 seconds
Started Sep 18 07:30:41 PM UTC 24
Finished Sep 18 07:30:43 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884326889 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1884326889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2468390612
Short name T301
Test name
Test status
Simulation time 319038340 ps
CPU time 25.03 seconds
Started Sep 18 07:30:25 PM UTC 24
Finished Sep 18 07:30:51 PM UTC 24
Peak memory 210280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468390612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2468390612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.1938865773
Short name T305
Test name
Test status
Simulation time 2384765978 ps
CPU time 34.47 seconds
Started Sep 18 07:30:25 PM UTC 24
Finished Sep 18 07:31:01 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938865773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1938865773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.2865594510
Short name T488
Test name
Test status
Simulation time 10586722376 ps
CPU time 964.84 seconds
Started Sep 18 07:30:25 PM UTC 24
Finished Sep 18 07:46:40 PM UTC 24
Peak memory 744672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865594510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2865594510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_error.3485586362
Short name T342
Test name
Test status
Simulation time 15602312771 ps
CPU time 152.07 seconds
Started Sep 18 07:30:28 PM UTC 24
Finished Sep 18 07:33:03 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485586362 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3485586362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_long_msg.3648522413
Short name T319
Test name
Test status
Simulation time 19383572278 ps
CPU time 71.76 seconds
Started Sep 18 07:30:20 PM UTC 24
Finished Sep 18 07:31:34 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648522413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3648522413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_smoke.3377374706
Short name T298
Test name
Test status
Simulation time 1630075346 ps
CPU time 18.58 seconds
Started Sep 18 07:30:20 PM UTC 24
Finished Sep 18 07:30:40 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377374706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3377374706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_stress_all.1582717792
Short name T312
Test name
Test status
Simulation time 11218538370 ps
CPU time 39.29 seconds
Started Sep 18 07:30:39 PM UTC 24
Finished Sep 18 07:31:20 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582717792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1582717792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.410296719
Short name T317
Test name
Test status
Simulation time 2485128721 ps
CPU time 50.29 seconds
Started Sep 18 07:30:34 PM UTC 24
Finished Sep 18 07:31:26 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410296719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.410296719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_alert_test.2437363174
Short name T309
Test name
Test status
Simulation time 46995645 ps
CPU time 0.78 seconds
Started Sep 18 07:31:10 PM UTC 24
Finished Sep 18 07:31:12 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437363174 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2437363174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.2852303769
Short name T320
Test name
Test status
Simulation time 2967990026 ps
CPU time 44.76 seconds
Started Sep 18 07:30:52 PM UTC 24
Finished Sep 18 07:31:38 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852303769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2852303769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.180847322
Short name T167
Test name
Test status
Simulation time 1053433849 ps
CPU time 56.99 seconds
Started Sep 18 07:31:01 PM UTC 24
Finished Sep 18 07:31:59 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180847322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.180847322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.4003187422
Short name T472
Test name
Test status
Simulation time 9689321731 ps
CPU time 794.38 seconds
Started Sep 18 07:31:01 PM UTC 24
Finished Sep 18 07:44:24 PM UTC 24
Peak memory 734628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003187422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4003187422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_error.1151827151
Short name T307
Test name
Test status
Simulation time 1549065598 ps
CPU time 7.44 seconds
Started Sep 18 07:31:01 PM UTC 24
Finished Sep 18 07:31:09 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151827151 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1151827151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_long_msg.426132318
Short name T332
Test name
Test status
Simulation time 9844038990 ps
CPU time 76.54 seconds
Started Sep 18 07:30:43 PM UTC 24
Finished Sep 18 07:32:02 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426132318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.426132318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_smoke.1362130320
Short name T303
Test name
Test status
Simulation time 912327669 ps
CPU time 15.93 seconds
Started Sep 18 07:30:42 PM UTC 24
Finished Sep 18 07:30:59 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362130320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1362130320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_stress_all.305372385
Short name T85
Test name
Test status
Simulation time 201790516056 ps
CPU time 1577.14 seconds
Started Sep 18 07:31:02 PM UTC 24
Finished Sep 18 07:57:36 PM UTC 24
Peak memory 792124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305372385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.305372385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.3777539857
Short name T308
Test name
Test status
Simulation time 857591052 ps
CPU time 8.2 seconds
Started Sep 18 07:31:02 PM UTC 24
Finished Sep 18 07:31:12 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777539857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3777539857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_alert_test.1975464305
Short name T54
Test name
Test status
Simulation time 156965609 ps
CPU time 0.91 seconds
Started Sep 18 07:21:03 PM UTC 24
Finished Sep 18 07:21:05 PM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975464305 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1975464305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.1770538232
Short name T13
Test name
Test status
Simulation time 458334024 ps
CPU time 14.26 seconds
Started Sep 18 07:20:53 PM UTC 24
Finished Sep 18 07:21:08 PM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770538232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1770538232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.994807605
Short name T181
Test name
Test status
Simulation time 17230213090 ps
CPU time 79.46 seconds
Started Sep 18 07:20:54 PM UTC 24
Finished Sep 18 07:22:16 PM UTC 24
Peak memory 219296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994807605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.994807605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.1634111769
Short name T263
Test name
Test status
Simulation time 2272458459 ps
CPU time 407.71 seconds
Started Sep 18 07:20:53 PM UTC 24
Finished Sep 18 07:27:46 PM UTC 24
Peak memory 697680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634111769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1634111769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_error.263342475
Short name T152
Test name
Test status
Simulation time 29309991824 ps
CPU time 86.8 seconds
Started Sep 18 07:20:54 PM UTC 24
Finished Sep 18 07:22:23 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263342475 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.263342475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2762282768
Short name T58
Test name
Test status
Simulation time 169526214 ps
CPU time 1.08 seconds
Started Sep 18 07:21:00 PM UTC 24
Finished Sep 18 07:21:02 PM UTC 24
Peak memory 238208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762282768 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2762282768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_smoke.3674507286
Short name T7
Test name
Test status
Simulation time 316452462 ps
CPU time 1.6 seconds
Started Sep 18 07:20:53 PM UTC 24
Finished Sep 18 07:20:55 PM UTC 24
Peak memory 209244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674507286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3674507286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_stress_all.2233234464
Short name T51
Test name
Test status
Simulation time 14460564892 ps
CPU time 235.61 seconds
Started Sep 18 07:20:57 PM UTC 24
Finished Sep 18 07:24:56 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233234464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2233234464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.4163394672
Short name T20
Test name
Test status
Simulation time 4126621691 ps
CPU time 480.7 seconds
Started Sep 18 07:20:58 PM UTC 24
Finished Sep 18 07:29:04 PM UTC 24
Peak memory 679596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41633946
72 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.4163394672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3371873013
Short name T186
Test name
Test status
Simulation time 10389742380 ps
CPU time 85.6 seconds
Started Sep 18 07:20:55 PM UTC 24
Finished Sep 18 07:22:22 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371873013 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3371873013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.1071601564
Short name T40
Test name
Test status
Simulation time 4286940852 ps
CPU time 65.7 seconds
Started Sep 18 07:20:56 PM UTC 24
Finished Sep 18 07:22:03 PM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071601564 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1071601564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.3677114803
Short name T196
Test name
Test status
Simulation time 24693671784 ps
CPU time 134.09 seconds
Started Sep 18 07:20:57 PM UTC 24
Finished Sep 18 07:23:13 PM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677114803 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3677114803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.1195676197
Short name T324
Test name
Test status
Simulation time 47842797334 ps
CPU time 641.08 seconds
Started Sep 18 07:20:54 PM UTC 24
Finished Sep 18 07:31:43 PM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195676197 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1195676197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.1100571057
Short name T519
Test name
Test status
Simulation time 607477566796 ps
CPU time 2971.39 seconds
Started Sep 18 07:20:54 PM UTC 24
Finished Sep 18 08:11:01 PM UTC 24
Peak memory 230624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100571057 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1100571057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.1813585929
Short name T517
Test name
Test status
Simulation time 704777123625 ps
CPU time 2588.94 seconds
Started Sep 18 07:20:55 PM UTC 24
Finished Sep 18 08:04:32 PM UTC 24
Peak memory 230588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813585929 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1813585929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.1030437061
Short name T15
Test name
Test status
Simulation time 1555997247 ps
CPU time 13.3 seconds
Started Sep 18 07:20:54 PM UTC 24
Finished Sep 18 07:21:09 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030437061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1030437061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_alert_test.814943646
Short name T314
Test name
Test status
Simulation time 13154474 ps
CPU time 0.97 seconds
Started Sep 18 07:31:20 PM UTC 24
Finished Sep 18 07:31:23 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814943646 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.814943646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.1292176881
Short name T325
Test name
Test status
Simulation time 919380484 ps
CPU time 29.17 seconds
Started Sep 18 07:31:15 PM UTC 24
Finished Sep 18 07:31:46 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292176881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1292176881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.2234162755
Short name T315
Test name
Test status
Simulation time 1597808969 ps
CPU time 6.29 seconds
Started Sep 18 07:31:15 PM UTC 24
Finished Sep 18 07:31:23 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234162755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2234162755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.1862486576
Short name T506
Test name
Test status
Simulation time 8195894384 ps
CPU time 1423.57 seconds
Started Sep 18 07:31:15 PM UTC 24
Finished Sep 18 07:55:13 PM UTC 24
Peak memory 746744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862486576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1862486576
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_error.2273619549
Short name T344
Test name
Test status
Simulation time 71797012492 ps
CPU time 113.8 seconds
Started Sep 18 07:31:17 PM UTC 24
Finished Sep 18 07:33:14 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273619549 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2273619549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_long_msg.4004733162
Short name T352
Test name
Test status
Simulation time 10358078389 ps
CPU time 164.82 seconds
Started Sep 18 07:31:12 PM UTC 24
Finished Sep 18 07:33:59 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004733162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.4004733162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_smoke.3121447547
Short name T310
Test name
Test status
Simulation time 232790464 ps
CPU time 4.97 seconds
Started Sep 18 07:31:10 PM UTC 24
Finished Sep 18 07:31:16 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121447547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3121447547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_stress_all.2881792872
Short name T41
Test name
Test status
Simulation time 7429044737 ps
CPU time 767.02 seconds
Started Sep 18 07:31:19 PM UTC 24
Finished Sep 18 07:44:15 PM UTC 24
Peak memory 713984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881792872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2881792872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.4124724349
Short name T357
Test name
Test status
Simulation time 8157234719 ps
CPU time 180.57 seconds
Started Sep 18 07:31:18 PM UTC 24
Finished Sep 18 07:34:21 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124724349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.4124724349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_alert_test.1029573494
Short name T321
Test name
Test status
Simulation time 80609673 ps
CPU time 0.88 seconds
Started Sep 18 07:31:39 PM UTC 24
Finished Sep 18 07:31:41 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029573494 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1029573494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.1489650417
Short name T330
Test name
Test status
Simulation time 1176830357 ps
CPU time 31.63 seconds
Started Sep 18 07:31:23 PM UTC 24
Finished Sep 18 07:31:57 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489650417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1489650417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.1847782551
Short name T173
Test name
Test status
Simulation time 6784414347 ps
CPU time 64.1 seconds
Started Sep 18 07:31:31 PM UTC 24
Finished Sep 18 07:32:37 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847782551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1847782551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.2091191475
Short name T371
Test name
Test status
Simulation time 1369981582 ps
CPU time 257.81 seconds
Started Sep 18 07:31:27 PM UTC 24
Finished Sep 18 07:35:49 PM UTC 24
Peak memory 681092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091191475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2091191475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_error.483294533
Short name T366
Test name
Test status
Simulation time 3853302922 ps
CPU time 229.53 seconds
Started Sep 18 07:31:31 PM UTC 24
Finished Sep 18 07:35:24 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483294533 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.483294533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_long_msg.479880529
Short name T327
Test name
Test status
Simulation time 5129384926 ps
CPU time 23.53 seconds
Started Sep 18 07:31:23 PM UTC 24
Finished Sep 18 07:31:49 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479880529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.479880529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_smoke.1167877503
Short name T323
Test name
Test status
Simulation time 1185387566 ps
CPU time 17.59 seconds
Started Sep 18 07:31:23 PM UTC 24
Finished Sep 18 07:31:43 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167877503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1167877503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_stress_all.1718778097
Short name T417
Test name
Test status
Simulation time 51371937670 ps
CPU time 507.92 seconds
Started Sep 18 07:31:35 PM UTC 24
Finished Sep 18 07:40:10 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718778097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1718778097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.3616002735
Short name T322
Test name
Test status
Simulation time 4099841581 ps
CPU time 10.42 seconds
Started Sep 18 07:31:31 PM UTC 24
Finished Sep 18 07:31:43 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616002735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3616002735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_alert_test.1445963312
Short name T331
Test name
Test status
Simulation time 36574772 ps
CPU time 0.83 seconds
Started Sep 18 07:31:57 PM UTC 24
Finished Sep 18 07:31:59 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445963312 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1445963312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.3436363495
Short name T47
Test name
Test status
Simulation time 684043778 ps
CPU time 26.2 seconds
Started Sep 18 07:31:47 PM UTC 24
Finished Sep 18 07:32:15 PM UTC 24
Peak memory 226616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436363495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3436363495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.2503661082
Short name T169
Test name
Test status
Simulation time 2293360109 ps
CPU time 67.23 seconds
Started Sep 18 07:31:48 PM UTC 24
Finished Sep 18 07:32:58 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503661082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2503661082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.2175142029
Short name T465
Test name
Test status
Simulation time 8437081585 ps
CPU time 723.2 seconds
Started Sep 18 07:31:47 PM UTC 24
Finished Sep 18 07:43:58 PM UTC 24
Peak memory 701688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175142029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2175142029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_error.1065387919
Short name T355
Test name
Test status
Simulation time 18700929716 ps
CPU time 133.62 seconds
Started Sep 18 07:31:51 PM UTC 24
Finished Sep 18 07:34:07 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065387919 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1065387919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_long_msg.1266498240
Short name T338
Test name
Test status
Simulation time 2368710602 ps
CPU time 60.97 seconds
Started Sep 18 07:31:43 PM UTC 24
Finished Sep 18 07:32:46 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266498240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1266498240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_smoke.3256167576
Short name T334
Test name
Test status
Simulation time 9661557461 ps
CPU time 21.56 seconds
Started Sep 18 07:31:42 PM UTC 24
Finished Sep 18 07:32:05 PM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256167576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3256167576
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_stress_all.1649123503
Short name T491
Test name
Test status
Simulation time 72799998361 ps
CPU time 897.71 seconds
Started Sep 18 07:31:57 PM UTC 24
Finished Sep 18 07:47:06 PM UTC 24
Peak memory 691460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649123503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1649123503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.1921292507
Short name T347
Test name
Test status
Simulation time 121961018574 ps
CPU time 89.9 seconds
Started Sep 18 07:31:51 PM UTC 24
Finished Sep 18 07:33:23 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921292507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1921292507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_alert_test.1391190792
Short name T337
Test name
Test status
Simulation time 37775194 ps
CPU time 0.82 seconds
Started Sep 18 07:32:35 PM UTC 24
Finished Sep 18 07:32:37 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391190792 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1391190792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.3822476414
Short name T340
Test name
Test status
Simulation time 1324457153 ps
CPU time 56.21 seconds
Started Sep 18 07:32:00 PM UTC 24
Finished Sep 18 07:32:57 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822476414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3822476414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.4032992145
Short name T336
Test name
Test status
Simulation time 1318918968 ps
CPU time 28.9 seconds
Started Sep 18 07:32:04 PM UTC 24
Finished Sep 18 07:32:34 PM UTC 24
Peak memory 218924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032992145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4032992145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.989416552
Short name T451
Test name
Test status
Simulation time 13034482665 ps
CPU time 642.9 seconds
Started Sep 18 07:32:03 PM UTC 24
Finished Sep 18 07:42:54 PM UTC 24
Peak memory 757068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989416552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.989416552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_error.1767214381
Short name T382
Test name
Test status
Simulation time 17627862390 ps
CPU time 257.25 seconds
Started Sep 18 07:32:05 PM UTC 24
Finished Sep 18 07:36:26 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767214381 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1767214381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_long_msg.3967848626
Short name T359
Test name
Test status
Simulation time 37403387289 ps
CPU time 162.92 seconds
Started Sep 18 07:32:00 PM UTC 24
Finished Sep 18 07:34:45 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967848626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3967848626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_smoke.3473071230
Short name T333
Test name
Test status
Simulation time 93958792 ps
CPU time 3.33 seconds
Started Sep 18 07:31:59 PM UTC 24
Finished Sep 18 07:32:03 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473071230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3473071230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_stress_all.3787269316
Short name T478
Test name
Test status
Simulation time 358294146387 ps
CPU time 760.18 seconds
Started Sep 18 07:32:27 PM UTC 24
Finished Sep 18 07:45:17 PM UTC 24
Peak memory 219036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787269316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3787269316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.1436928996
Short name T107
Test name
Test status
Simulation time 6723909393 ps
CPU time 106.74 seconds
Started Sep 18 07:32:16 PM UTC 24
Finished Sep 18 07:34:05 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436928996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1436928996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_alert_test.3743920358
Short name T345
Test name
Test status
Simulation time 10640623 ps
CPU time 0.77 seconds
Started Sep 18 07:33:15 PM UTC 24
Finished Sep 18 07:33:17 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743920358 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3743920358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.2380958383
Short name T341
Test name
Test status
Simulation time 119805402 ps
CPU time 10.11 seconds
Started Sep 18 07:32:47 PM UTC 24
Finished Sep 18 07:32:58 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380958383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2380958383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.4055317331
Short name T350
Test name
Test status
Simulation time 6093233028 ps
CPU time 48.86 seconds
Started Sep 18 07:32:59 PM UTC 24
Finished Sep 18 07:33:50 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055317331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4055317331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.3863428074
Short name T358
Test name
Test status
Simulation time 717037504 ps
CPU time 102.51 seconds
Started Sep 18 07:32:50 PM UTC 24
Finished Sep 18 07:34:35 PM UTC 24
Peak memory 466172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863428074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3863428074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_error.4119178749
Short name T370
Test name
Test status
Simulation time 2689698880 ps
CPU time 165.55 seconds
Started Sep 18 07:32:59 PM UTC 24
Finished Sep 18 07:35:48 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119178749 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4119178749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_long_msg.1590249535
Short name T365
Test name
Test status
Simulation time 11666009503 ps
CPU time 154.15 seconds
Started Sep 18 07:32:38 PM UTC 24
Finished Sep 18 07:35:14 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590249535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1590249535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_smoke.3811510302
Short name T339
Test name
Test status
Simulation time 721811105 ps
CPU time 10.71 seconds
Started Sep 18 07:32:38 PM UTC 24
Finished Sep 18 07:32:49 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811510302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3811510302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_stress_all.2393906202
Short name T518
Test name
Test status
Simulation time 27025941403 ps
CPU time 2135.04 seconds
Started Sep 18 07:33:05 PM UTC 24
Finished Sep 18 08:09:03 PM UTC 24
Peak memory 720500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393906202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2393906202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.325247959
Short name T349
Test name
Test status
Simulation time 13331226655 ps
CPU time 42.73 seconds
Started Sep 18 07:32:59 PM UTC 24
Finished Sep 18 07:33:43 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325247959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.325247959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_alert_test.3828389945
Short name T353
Test name
Test status
Simulation time 17927894 ps
CPU time 0.84 seconds
Started Sep 18 07:34:01 PM UTC 24
Finished Sep 18 07:34:03 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828389945 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3828389945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.3732521182
Short name T362
Test name
Test status
Simulation time 2975144904 ps
CPU time 109.19 seconds
Started Sep 18 07:33:19 PM UTC 24
Finished Sep 18 07:35:11 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732521182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3732521182
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.2692873226
Short name T175
Test name
Test status
Simulation time 620703509 ps
CPU time 37.68 seconds
Started Sep 18 07:33:36 PM UTC 24
Finished Sep 18 07:34:15 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692873226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2692873226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1615825964
Short name T416
Test name
Test status
Simulation time 4489675096 ps
CPU time 397.47 seconds
Started Sep 18 07:33:25 PM UTC 24
Finished Sep 18 07:40:07 PM UTC 24
Peak memory 482856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615825964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1615825964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_error.305818834
Short name T383
Test name
Test status
Simulation time 35339222825 ps
CPU time 160.36 seconds
Started Sep 18 07:33:44 PM UTC 24
Finished Sep 18 07:36:27 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305818834 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.305818834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_long_msg.678090357
Short name T367
Test name
Test status
Simulation time 6061472660 ps
CPU time 126.47 seconds
Started Sep 18 07:33:19 PM UTC 24
Finished Sep 18 07:35:28 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678090357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.678090357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_smoke.1583209288
Short name T348
Test name
Test status
Simulation time 298156220 ps
CPU time 17.81 seconds
Started Sep 18 07:33:15 PM UTC 24
Finished Sep 18 07:33:34 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583209288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1583209288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_stress_all.3392811124
Short name T81
Test name
Test status
Simulation time 21393876994 ps
CPU time 287.85 seconds
Started Sep 18 07:33:58 PM UTC 24
Finished Sep 18 07:38:50 PM UTC 24
Peak memory 221160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392811124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3392811124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.2192764404
Short name T368
Test name
Test status
Simulation time 3454247861 ps
CPU time 103.58 seconds
Started Sep 18 07:33:50 PM UTC 24
Finished Sep 18 07:35:36 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192764404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2192764404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_alert_test.2345185321
Short name T361
Test name
Test status
Simulation time 41000822 ps
CPU time 0.79 seconds
Started Sep 18 07:34:47 PM UTC 24
Finished Sep 18 07:34:49 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345185321 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2345185321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.2238608781
Short name T32
Test name
Test status
Simulation time 3227722284 ps
CPU time 110.07 seconds
Started Sep 18 07:34:08 PM UTC 24
Finished Sep 18 07:36:00 PM UTC 24
Peak memory 219240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238608781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2238608781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.4180651621
Short name T363
Test name
Test status
Simulation time 9135437490 ps
CPU time 53.67 seconds
Started Sep 18 07:34:16 PM UTC 24
Finished Sep 18 07:35:11 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180651621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.4180651621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.1063440151
Short name T505
Test name
Test status
Simulation time 7463603118 ps
CPU time 1202.2 seconds
Started Sep 18 07:34:09 PM UTC 24
Finished Sep 18 07:54:25 PM UTC 24
Peak memory 763264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063440151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1063440151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_error.3626814615
Short name T376
Test name
Test status
Simulation time 21191918644 ps
CPU time 109.66 seconds
Started Sep 18 07:34:16 PM UTC 24
Finished Sep 18 07:36:07 PM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626814615 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3626814615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_long_msg.2180343524
Short name T374
Test name
Test status
Simulation time 1453579401 ps
CPU time 105.46 seconds
Started Sep 18 07:34:08 PM UTC 24
Finished Sep 18 07:35:55 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180343524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2180343524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_smoke.2938004782
Short name T356
Test name
Test status
Simulation time 258960194 ps
CPU time 9.93 seconds
Started Sep 18 07:34:04 PM UTC 24
Finished Sep 18 07:34:15 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938004782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2938004782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_stress_all.548206179
Short name T523
Test name
Test status
Simulation time 236846871212 ps
CPU time 2839.39 seconds
Started Sep 18 07:34:36 PM UTC 24
Finished Sep 18 08:22:27 PM UTC 24
Peak memory 785648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548206179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.548206179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.1594494520
Short name T375
Test name
Test status
Simulation time 6431150880 ps
CPU time 97.19 seconds
Started Sep 18 07:34:23 PM UTC 24
Finished Sep 18 07:36:02 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594494520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1594494520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_alert_test.1584260218
Short name T369
Test name
Test status
Simulation time 45222455 ps
CPU time 0.88 seconds
Started Sep 18 07:35:38 PM UTC 24
Finished Sep 18 07:35:40 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584260218 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1584260218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.4031376657
Short name T385
Test name
Test status
Simulation time 1922213281 ps
CPU time 91.88 seconds
Started Sep 18 07:35:12 PM UTC 24
Finished Sep 18 07:36:46 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031376657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4031376657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.3746824276
Short name T380
Test name
Test status
Simulation time 2348947333 ps
CPU time 55.02 seconds
Started Sep 18 07:35:16 PM UTC 24
Finished Sep 18 07:36:13 PM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746824276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3746824276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.3500236341
Short name T500
Test name
Test status
Simulation time 5452031138 ps
CPU time 923.48 seconds
Started Sep 18 07:35:12 PM UTC 24
Finished Sep 18 07:50:46 PM UTC 24
Peak memory 706056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500236341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3500236341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_error.219549806
Short name T407
Test name
Test status
Simulation time 13650690381 ps
CPU time 188.29 seconds
Started Sep 18 07:35:16 PM UTC 24
Finished Sep 18 07:38:28 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219549806 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.219549806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_long_msg.3351993387
Short name T399
Test name
Test status
Simulation time 20598450884 ps
CPU time 163.33 seconds
Started Sep 18 07:34:50 PM UTC 24
Finished Sep 18 07:37:37 PM UTC 24
Peak memory 218972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351993387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3351993387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_smoke.3471312770
Short name T364
Test name
Test status
Simulation time 1271703023 ps
CPU time 22.56 seconds
Started Sep 18 07:34:50 PM UTC 24
Finished Sep 18 07:35:14 PM UTC 24
Peak memory 210588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471312770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3471312770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_stress_all.1993243475
Short name T492
Test name
Test status
Simulation time 67168399172 ps
CPU time 692.77 seconds
Started Sep 18 07:35:29 PM UTC 24
Finished Sep 18 07:47:10 PM UTC 24
Peak memory 708116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993243475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1993243475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2382150927
Short name T372
Test name
Test status
Simulation time 975015396 ps
CPU time 23.08 seconds
Started Sep 18 07:35:26 PM UTC 24
Finished Sep 18 07:35:50 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382150927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2382150927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_alert_test.853555941
Short name T378
Test name
Test status
Simulation time 10599313 ps
CPU time 0.89 seconds
Started Sep 18 07:36:09 PM UTC 24
Finished Sep 18 07:36:11 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853555941 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.853555941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.1165203138
Short name T398
Test name
Test status
Simulation time 1687791822 ps
CPU time 93.12 seconds
Started Sep 18 07:35:51 PM UTC 24
Finished Sep 18 07:37:26 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165203138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1165203138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.2121845113
Short name T391
Test name
Test status
Simulation time 14251940057 ps
CPU time 72.25 seconds
Started Sep 18 07:35:51 PM UTC 24
Finished Sep 18 07:37:05 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121845113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2121845113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.2377673251
Short name T462
Test name
Test status
Simulation time 36039114126 ps
CPU time 468.93 seconds
Started Sep 18 07:35:51 PM UTC 24
Finished Sep 18 07:43:45 PM UTC 24
Peak memory 756992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377673251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2377673251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_error.2112969774
Short name T400
Test name
Test status
Simulation time 2738731752 ps
CPU time 104.04 seconds
Started Sep 18 07:35:57 PM UTC 24
Finished Sep 18 07:37:43 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112969774 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2112969774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_long_msg.911777832
Short name T384
Test name
Test status
Simulation time 1728349280 ps
CPU time 53.08 seconds
Started Sep 18 07:35:49 PM UTC 24
Finished Sep 18 07:36:44 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911777832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.911777832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_smoke.1905673090
Short name T373
Test name
Test status
Simulation time 1320943511 ps
CPU time 7.92 seconds
Started Sep 18 07:35:41 PM UTC 24
Finished Sep 18 07:35:50 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905673090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1905673090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_stress_all.1841964026
Short name T520
Test name
Test status
Simulation time 14719865161 ps
CPU time 2092.33 seconds
Started Sep 18 07:36:03 PM UTC 24
Finished Sep 18 08:11:17 PM UTC 24
Peak memory 793868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841964026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1841964026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.4146803852
Short name T388
Test name
Test status
Simulation time 17172762933 ps
CPU time 55 seconds
Started Sep 18 07:36:02 PM UTC 24
Finished Sep 18 07:36:58 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146803852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4146803852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_alert_test.774503796
Short name T386
Test name
Test status
Simulation time 12652654 ps
CPU time 0.78 seconds
Started Sep 18 07:36:48 PM UTC 24
Finished Sep 18 07:36:50 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774503796 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.774503796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.2699379300
Short name T389
Test name
Test status
Simulation time 1912316884 ps
CPU time 41.38 seconds
Started Sep 18 07:36:16 PM UTC 24
Finished Sep 18 07:36:59 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699379300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2699379300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.633963459
Short name T393
Test name
Test status
Simulation time 3980484577 ps
CPU time 38.22 seconds
Started Sep 18 07:36:29 PM UTC 24
Finished Sep 18 07:37:08 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633963459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.633963459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.1935150629
Short name T423
Test name
Test status
Simulation time 1298999783 ps
CPU time 247.82 seconds
Started Sep 18 07:36:16 PM UTC 24
Finished Sep 18 07:40:27 PM UTC 24
Peak memory 709736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935150629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1935150629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_error.1154009750
Short name T387
Test name
Test status
Simulation time 2673953530 ps
CPU time 26.11 seconds
Started Sep 18 07:36:29 PM UTC 24
Finished Sep 18 07:36:56 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154009750 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1154009750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_long_msg.573725592
Short name T401
Test name
Test status
Simulation time 2730610020 ps
CPU time 90.85 seconds
Started Sep 18 07:36:12 PM UTC 24
Finished Sep 18 07:37:45 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573725592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.573725592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_smoke.30170245
Short name T381
Test name
Test status
Simulation time 904108508 ps
CPU time 13.83 seconds
Started Sep 18 07:36:11 PM UTC 24
Finished Sep 18 07:36:26 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30170245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 39.hmac_smoke.30170245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_stress_all.2109788223
Short name T109
Test name
Test status
Simulation time 25535634088 ps
CPU time 418.23 seconds
Started Sep 18 07:36:45 PM UTC 24
Finished Sep 18 07:43:49 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109788223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2109788223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.2114396529
Short name T395
Test name
Test status
Simulation time 725981961 ps
CPU time 40.2 seconds
Started Sep 18 07:36:29 PM UTC 24
Finished Sep 18 07:37:10 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114396529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2114396529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_alert_test.239493098
Short name T182
Test name
Test status
Simulation time 12206797 ps
CPU time 0.92 seconds
Started Sep 18 07:21:32 PM UTC 24
Finished Sep 18 07:21:34 PM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239493098 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.239493098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.52184511
Short name T156
Test name
Test status
Simulation time 5905007083 ps
CPU time 66.1 seconds
Started Sep 18 07:21:06 PM UTC 24
Finished Sep 18 07:22:14 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52184511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.52184511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.2169014580
Short name T354
Test name
Test status
Simulation time 24389695745 ps
CPU time 770.04 seconds
Started Sep 18 07:21:06 PM UTC 24
Finished Sep 18 07:34:05 PM UTC 24
Peak memory 754936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169014580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2169014580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_error.4124694647
Short name T49
Test name
Test status
Simulation time 3742754431 ps
CPU time 67.5 seconds
Started Sep 18 07:21:07 PM UTC 24
Finished Sep 18 07:22:16 PM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124694647 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4124694647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_long_msg.2446000818
Short name T131
Test name
Test status
Simulation time 2264055499 ps
CPU time 36.41 seconds
Started Sep 18 07:21:06 PM UTC 24
Finished Sep 18 07:21:43 PM UTC 24
Peak memory 210356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446000818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2446000818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.1283192071
Short name T59
Test name
Test status
Simulation time 347525003 ps
CPU time 1.3 seconds
Started Sep 18 07:21:32 PM UTC 24
Finished Sep 18 07:21:34 PM UTC 24
Peak memory 238208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283192071 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1283192071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_stress_all.885199682
Short name T143
Test name
Test status
Simulation time 6854718587 ps
CPU time 359.19 seconds
Started Sep 18 07:21:21 PM UTC 24
Finished Sep 18 07:27:25 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885199682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.885199682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.1519327132
Short name T190
Test name
Test status
Simulation time 17727775560 ps
CPU time 77.97 seconds
Started Sep 18 07:21:14 PM UTC 24
Finished Sep 18 07:22:34 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519327132 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1519327132
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.2077603920
Short name T188
Test name
Test status
Simulation time 19615090766 ps
CPU time 68.29 seconds
Started Sep 18 07:21:15 PM UTC 24
Finished Sep 18 07:22:25 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077603920 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2077603920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.1730284208
Short name T180
Test name
Test status
Simulation time 9399832301 ps
CPU time 84.17 seconds
Started Sep 18 07:21:19 PM UTC 24
Finished Sep 18 07:22:45 PM UTC 24
Peak memory 210716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730284208 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1730284208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.1540516017
Short name T158
Test name
Test status
Simulation time 87176878642 ps
CPU time 594.91 seconds
Started Sep 18 07:21:09 PM UTC 24
Finished Sep 18 07:31:11 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540516017 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1540516017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.2363046306
Short name T508
Test name
Test status
Simulation time 36016584794 ps
CPU time 2092.07 seconds
Started Sep 18 07:21:09 PM UTC 24
Finished Sep 18 07:56:25 PM UTC 24
Peak memory 230588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363046306 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2363046306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1262685507
Short name T510
Test name
Test status
Simulation time 173366810020 ps
CPU time 2243.05 seconds
Started Sep 18 07:21:12 PM UTC 24
Finished Sep 18 07:59:01 PM UTC 24
Peak memory 230820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262685507 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1262685507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.3923913891
Short name T138
Test name
Test status
Simulation time 11083865694 ps
CPU time 124.64 seconds
Started Sep 18 07:21:09 PM UTC 24
Finished Sep 18 07:23:16 PM UTC 24
Peak memory 210612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923913891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3923913891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_alert_test.3623778711
Short name T396
Test name
Test status
Simulation time 11680841 ps
CPU time 0.92 seconds
Started Sep 18 07:37:11 PM UTC 24
Finished Sep 18 07:37:13 PM UTC 24
Peak memory 207412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623778711 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3623778711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.409341972
Short name T394
Test name
Test status
Simulation time 343256536 ps
CPU time 6.74 seconds
Started Sep 18 07:37:02 PM UTC 24
Finished Sep 18 07:37:10 PM UTC 24
Peak memory 210360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409341972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.409341972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.1706817488
Short name T405
Test name
Test status
Simulation time 10700297520 ps
CPU time 68.3 seconds
Started Sep 18 07:37:02 PM UTC 24
Finished Sep 18 07:38:12 PM UTC 24
Peak memory 219064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706817488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1706817488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.398706704
Short name T495
Test name
Test status
Simulation time 3300939016 ps
CPU time 697.57 seconds
Started Sep 18 07:37:02 PM UTC 24
Finished Sep 18 07:48:48 PM UTC 24
Peak memory 652628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398706704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.398706704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_error.3212726981
Short name T408
Test name
Test status
Simulation time 17770194519 ps
CPU time 93.5 seconds
Started Sep 18 07:37:06 PM UTC 24
Finished Sep 18 07:38:42 PM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212726981 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3212726981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1744909907
Short name T403
Test name
Test status
Simulation time 4866130858 ps
CPU time 63.88 seconds
Started Sep 18 07:36:57 PM UTC 24
Finished Sep 18 07:38:02 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744909907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1744909907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_smoke.3427351885
Short name T392
Test name
Test status
Simulation time 1989221248 ps
CPU time 16.21 seconds
Started Sep 18 07:36:50 PM UTC 24
Finished Sep 18 07:37:08 PM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427351885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3427351885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_stress_all.4098034139
Short name T525
Test name
Test status
Simulation time 133206720214 ps
CPU time 3046.33 seconds
Started Sep 18 07:37:09 PM UTC 24
Finished Sep 18 08:28:28 PM UTC 24
Peak memory 812288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098034139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4098034139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.1336515569
Short name T414
Test name
Test status
Simulation time 19214149077 ps
CPU time 114.18 seconds
Started Sep 18 07:37:09 PM UTC 24
Finished Sep 18 07:39:06 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336515569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1336515569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_alert_test.2013067609
Short name T404
Test name
Test status
Simulation time 10922114 ps
CPU time 0.8 seconds
Started Sep 18 07:38:00 PM UTC 24
Finished Sep 18 07:38:02 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013067609 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2013067609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.4034046169
Short name T413
Test name
Test status
Simulation time 1373356608 ps
CPU time 99.86 seconds
Started Sep 18 07:37:22 PM UTC 24
Finished Sep 18 07:39:04 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034046169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4034046169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.3130249931
Short name T409
Test name
Test status
Simulation time 919394372 ps
CPU time 63.17 seconds
Started Sep 18 07:37:39 PM UTC 24
Finished Sep 18 07:38:44 PM UTC 24
Peak memory 218948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130249931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3130249931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.2530500439
Short name T499
Test name
Test status
Simulation time 3677624764 ps
CPU time 722.65 seconds
Started Sep 18 07:37:28 PM UTC 24
Finished Sep 18 07:49:39 PM UTC 24
Peak memory 716452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530500439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2530500439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_error.794884000
Short name T402
Test name
Test status
Simulation time 311837053 ps
CPU time 7.68 seconds
Started Sep 18 07:37:44 PM UTC 24
Finished Sep 18 07:37:53 PM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794884000 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.794884000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_long_msg.1355929977
Short name T415
Test name
Test status
Simulation time 28340501171 ps
CPU time 165.34 seconds
Started Sep 18 07:37:13 PM UTC 24
Finished Sep 18 07:40:01 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355929977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1355929977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_smoke.1540471259
Short name T397
Test name
Test status
Simulation time 2177392632 ps
CPU time 8.54 seconds
Started Sep 18 07:37:12 PM UTC 24
Finished Sep 18 07:37:21 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540471259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1540471259
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_stress_all.2920457711
Short name T527
Test name
Test status
Simulation time 259759568737 ps
CPU time 4586.39 seconds
Started Sep 18 07:37:54 PM UTC 24
Finished Sep 18 08:55:09 PM UTC 24
Peak memory 865568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920457711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2920457711
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.4293814439
Short name T419
Test name
Test status
Simulation time 7262811823 ps
CPU time 142.72 seconds
Started Sep 18 07:37:47 PM UTC 24
Finished Sep 18 07:40:13 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293814439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4293814439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_alert_test.1460136716
Short name T411
Test name
Test status
Simulation time 17379398 ps
CPU time 0.89 seconds
Started Sep 18 07:38:54 PM UTC 24
Finished Sep 18 07:38:56 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460136716 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1460136716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.399189352
Short name T427
Test name
Test status
Simulation time 8320677009 ps
CPU time 150.82 seconds
Started Sep 18 07:38:13 PM UTC 24
Finished Sep 18 07:40:47 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399189352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.399189352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.182041917
Short name T418
Test name
Test status
Simulation time 5457981585 ps
CPU time 99.27 seconds
Started Sep 18 07:38:29 PM UTC 24
Finished Sep 18 07:40:11 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182041917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.182041917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.3104989670
Short name T494
Test name
Test status
Simulation time 10669193514 ps
CPU time 534.64 seconds
Started Sep 18 07:38:23 PM UTC 24
Finished Sep 18 07:47:24 PM UTC 24
Peak memory 724224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104989670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3104989670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_error.3203604219
Short name T434
Test name
Test status
Simulation time 2329174837 ps
CPU time 150.67 seconds
Started Sep 18 07:38:44 PM UTC 24
Finished Sep 18 07:41:17 PM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203604219 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3203604219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_long_msg.3240016082
Short name T433
Test name
Test status
Simulation time 32770256991 ps
CPU time 189.68 seconds
Started Sep 18 07:38:03 PM UTC 24
Finished Sep 18 07:41:16 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240016082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3240016082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_smoke.3292223063
Short name T406
Test name
Test status
Simulation time 573689053 ps
CPU time 17.86 seconds
Started Sep 18 07:38:03 PM UTC 24
Finished Sep 18 07:38:22 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292223063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3292223063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_stress_all.432509760
Short name T493
Test name
Test status
Simulation time 25122151256 ps
CPU time 495.52 seconds
Started Sep 18 07:38:52 PM UTC 24
Finished Sep 18 07:47:14 PM UTC 24
Peak memory 221216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432509760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.432509760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.3383481080
Short name T435
Test name
Test status
Simulation time 3082597762 ps
CPU time 159.4 seconds
Started Sep 18 07:38:45 PM UTC 24
Finished Sep 18 07:41:27 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383481080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3383481080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_alert_test.1919173568
Short name T421
Test name
Test status
Simulation time 23690276 ps
CPU time 0.86 seconds
Started Sep 18 07:40:16 PM UTC 24
Finished Sep 18 07:40:18 PM UTC 24
Peak memory 207412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919173568 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1919173568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.882968959
Short name T428
Test name
Test status
Simulation time 2607428603 ps
CPU time 109.7 seconds
Started Sep 18 07:39:06 PM UTC 24
Finished Sep 18 07:40:58 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882968959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.882968959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.3956398454
Short name T431
Test name
Test status
Simulation time 3002443650 ps
CPU time 58.88 seconds
Started Sep 18 07:40:03 PM UTC 24
Finished Sep 18 07:41:03 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956398454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3956398454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.1898905429
Short name T489
Test name
Test status
Simulation time 2645050660 ps
CPU time 454.85 seconds
Started Sep 18 07:39:08 PM UTC 24
Finished Sep 18 07:46:49 PM UTC 24
Peak memory 748860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898905429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1898905429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_error.1365255791
Short name T422
Test name
Test status
Simulation time 2567036520 ps
CPU time 10.07 seconds
Started Sep 18 07:40:09 PM UTC 24
Finished Sep 18 07:40:20 PM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365255791 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1365255791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1465172279
Short name T458
Test name
Test status
Simulation time 16401229025 ps
CPU time 257.06 seconds
Started Sep 18 07:39:03 PM UTC 24
Finished Sep 18 07:43:24 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465172279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1465172279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_smoke.3983062374
Short name T412
Test name
Test status
Simulation time 626510420 ps
CPU time 4.33 seconds
Started Sep 18 07:38:57 PM UTC 24
Finished Sep 18 07:39:02 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983062374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3983062374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_stress_all.2923027836
Short name T516
Test name
Test status
Simulation time 15055945478 ps
CPU time 1345.84 seconds
Started Sep 18 07:40:12 PM UTC 24
Finished Sep 18 08:02:53 PM UTC 24
Peak memory 755272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923027836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2923027836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.3336677439
Short name T429
Test name
Test status
Simulation time 1259852277 ps
CPU time 44.83 seconds
Started Sep 18 07:40:12 PM UTC 24
Finished Sep 18 07:40:59 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336677439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3336677439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_alert_test.1260529769
Short name T430
Test name
Test status
Simulation time 18929519 ps
CPU time 0.91 seconds
Started Sep 18 07:41:01 PM UTC 24
Finished Sep 18 07:41:03 PM UTC 24
Peak memory 207412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260529769 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1260529769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.959192887
Short name T437
Test name
Test status
Simulation time 897273976 ps
CPU time 74.22 seconds
Started Sep 18 07:40:20 PM UTC 24
Finished Sep 18 07:41:37 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959192887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.959192887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.2988829831
Short name T426
Test name
Test status
Simulation time 194058998 ps
CPU time 3.85 seconds
Started Sep 18 07:40:37 PM UTC 24
Finished Sep 18 07:40:43 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988829831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2988829831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.2625107264
Short name T497
Test name
Test status
Simulation time 11436674062 ps
CPU time 522.05 seconds
Started Sep 18 07:40:29 PM UTC 24
Finished Sep 18 07:49:18 PM UTC 24
Peak memory 724320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625107264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2625107264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_error.35512291
Short name T457
Test name
Test status
Simulation time 56681547315 ps
CPU time 153.09 seconds
Started Sep 18 07:40:44 PM UTC 24
Finished Sep 18 07:43:20 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35512291 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.35512291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_long_msg.967256640
Short name T446
Test name
Test status
Simulation time 16590529988 ps
CPU time 137.1 seconds
Started Sep 18 07:40:18 PM UTC 24
Finished Sep 18 07:42:38 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967256640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.967256640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_smoke.255593023
Short name T424
Test name
Test status
Simulation time 1104730961 ps
CPU time 19.27 seconds
Started Sep 18 07:40:16 PM UTC 24
Finished Sep 18 07:40:37 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255593023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.255593023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_stress_all.277254800
Short name T479
Test name
Test status
Simulation time 8070387071 ps
CPU time 265.79 seconds
Started Sep 18 07:40:49 PM UTC 24
Finished Sep 18 07:45:18 PM UTC 24
Peak memory 357564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277254800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.277254800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.565319044
Short name T436
Test name
Test status
Simulation time 3297692862 ps
CPU time 48.96 seconds
Started Sep 18 07:40:44 PM UTC 24
Finished Sep 18 07:41:35 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565319044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.565319044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_alert_test.3666357981
Short name T438
Test name
Test status
Simulation time 48917348 ps
CPU time 0.88 seconds
Started Sep 18 07:41:38 PM UTC 24
Finished Sep 18 07:41:40 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666357981 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3666357981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.3867808695
Short name T439
Test name
Test status
Simulation time 2564768930 ps
CPU time 38.87 seconds
Started Sep 18 07:41:04 PM UTC 24
Finished Sep 18 07:41:44 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867808695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3867808695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.1636279463
Short name T442
Test name
Test status
Simulation time 1196641357 ps
CPU time 37.12 seconds
Started Sep 18 07:41:19 PM UTC 24
Finished Sep 18 07:41:57 PM UTC 24
Peak memory 219192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636279463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1636279463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.4280777144
Short name T466
Test name
Test status
Simulation time 5258886472 ps
CPU time 170.37 seconds
Started Sep 18 07:41:06 PM UTC 24
Finished Sep 18 07:43:59 PM UTC 24
Peak memory 423220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280777144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4280777144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_error.4216679980
Short name T450
Test name
Test status
Simulation time 3768336978 ps
CPU time 88.77 seconds
Started Sep 18 07:41:19 PM UTC 24
Finished Sep 18 07:42:50 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216679980 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4216679980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_long_msg.92389026
Short name T440
Test name
Test status
Simulation time 5479723958 ps
CPU time 39.09 seconds
Started Sep 18 07:41:04 PM UTC 24
Finished Sep 18 07:41:45 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92389026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.92389026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_smoke.2177497730
Short name T432
Test name
Test status
Simulation time 42317902 ps
CPU time 2.82 seconds
Started Sep 18 07:41:01 PM UTC 24
Finished Sep 18 07:41:05 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177497730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2177497730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_stress_all.373526692
Short name T498
Test name
Test status
Simulation time 27585174020 ps
CPU time 458.96 seconds
Started Sep 18 07:41:36 PM UTC 24
Finished Sep 18 07:49:21 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373526692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.373526692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.3239111601
Short name T447
Test name
Test status
Simulation time 19006385858 ps
CPU time 69.43 seconds
Started Sep 18 07:41:29 PM UTC 24
Finished Sep 18 07:42:40 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239111601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3239111601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_alert_test.141790703
Short name T448
Test name
Test status
Simulation time 39185256 ps
CPU time 0.86 seconds
Started Sep 18 07:42:39 PM UTC 24
Finished Sep 18 07:42:41 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141790703 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.141790703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.2054362078
Short name T445
Test name
Test status
Simulation time 675665476 ps
CPU time 49.63 seconds
Started Sep 18 07:41:47 PM UTC 24
Finished Sep 18 07:42:38 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054362078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2054362078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.1994155798
Short name T443
Test name
Test status
Simulation time 504449905 ps
CPU time 9.96 seconds
Started Sep 18 07:41:59 PM UTC 24
Finished Sep 18 07:42:10 PM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994155798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1994155798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.2705322384
Short name T486
Test name
Test status
Simulation time 2813677312 ps
CPU time 270.33 seconds
Started Sep 18 07:41:58 PM UTC 24
Finished Sep 18 07:46:32 PM UTC 24
Peak memory 494852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705322384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2705322384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_error.3721908300
Short name T444
Test name
Test status
Simulation time 81762565 ps
CPU time 6.92 seconds
Started Sep 18 07:42:11 PM UTC 24
Finished Sep 18 07:42:19 PM UTC 24
Peak memory 210108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721908300 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3721908300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_long_msg.2883531304
Short name T449
Test name
Test status
Simulation time 11136478947 ps
CPU time 57.93 seconds
Started Sep 18 07:41:45 PM UTC 24
Finished Sep 18 07:42:45 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883531304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2883531304
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_smoke.661829388
Short name T441
Test name
Test status
Simulation time 853157463 ps
CPU time 15.38 seconds
Started Sep 18 07:41:41 PM UTC 24
Finished Sep 18 07:41:57 PM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661829388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.661829388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_stress_all.108758364
Short name T82
Test name
Test status
Simulation time 131601246389 ps
CPU time 697.93 seconds
Started Sep 18 07:42:34 PM UTC 24
Finished Sep 18 07:54:21 PM UTC 24
Peak memory 689400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108758364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.108758364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.772765435
Short name T471
Test name
Test status
Simulation time 2235068594 ps
CPU time 119.56 seconds
Started Sep 18 07:42:20 PM UTC 24
Finished Sep 18 07:44:22 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772765435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.772765435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1696833597
Short name T455
Test name
Test status
Simulation time 44805021 ps
CPU time 0.83 seconds
Started Sep 18 07:43:14 PM UTC 24
Finished Sep 18 07:43:16 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696833597 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1696833597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.4180314580
Short name T468
Test name
Test status
Simulation time 1424437611 ps
CPU time 82.82 seconds
Started Sep 18 07:42:42 PM UTC 24
Finished Sep 18 07:44:07 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180314580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4180314580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.2174111543
Short name T460
Test name
Test status
Simulation time 3170832634 ps
CPU time 45.38 seconds
Started Sep 18 07:42:51 PM UTC 24
Finished Sep 18 07:43:38 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174111543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2174111543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.3023036305
Short name T502
Test name
Test status
Simulation time 3295612496 ps
CPU time 501.58 seconds
Started Sep 18 07:42:46 PM UTC 24
Finished Sep 18 07:51:13 PM UTC 24
Peak memory 500984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023036305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3023036305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_error.2873901158
Short name T490
Test name
Test status
Simulation time 6455836733 ps
CPU time 237.28 seconds
Started Sep 18 07:42:56 PM UTC 24
Finished Sep 18 07:46:57 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873901158 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2873901158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_long_msg.3704254251
Short name T475
Test name
Test status
Simulation time 5897432299 ps
CPU time 134.06 seconds
Started Sep 18 07:42:41 PM UTC 24
Finished Sep 18 07:44:58 PM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704254251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3704254251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_smoke.1637713838
Short name T452
Test name
Test status
Simulation time 633159352 ps
CPU time 17.4 seconds
Started Sep 18 07:42:41 PM UTC 24
Finished Sep 18 07:43:00 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637713838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1637713838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2024907846
Short name T524
Test name
Test status
Simulation time 20563556254 ps
CPU time 2436.89 seconds
Started Sep 18 07:43:11 PM UTC 24
Finished Sep 18 08:24:14 PM UTC 24
Peak memory 814584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024907846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2024907846
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.2314635325
Short name T456
Test name
Test status
Simulation time 8163538904 ps
CPU time 16.26 seconds
Started Sep 18 07:43:00 PM UTC 24
Finished Sep 18 07:43:18 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314635325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2314635325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2439551331
Short name T464
Test name
Test status
Simulation time 15731621 ps
CPU time 0.82 seconds
Started Sep 18 07:43:54 PM UTC 24
Finished Sep 18 07:43:55 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439551331 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2439551331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.3299159192
Short name T463
Test name
Test status
Simulation time 727062497 ps
CPU time 26.64 seconds
Started Sep 18 07:43:22 PM UTC 24
Finished Sep 18 07:43:50 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299159192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3299159192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.2191373040
Short name T470
Test name
Test status
Simulation time 3039072777 ps
CPU time 46.81 seconds
Started Sep 18 07:43:32 PM UTC 24
Finished Sep 18 07:44:21 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191373040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2191373040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.641220233
Short name T496
Test name
Test status
Simulation time 7648709494 ps
CPU time 321.79 seconds
Started Sep 18 07:43:26 PM UTC 24
Finished Sep 18 07:48:53 PM UTC 24
Peak memory 495108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641220233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.641220233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_error.1767252915
Short name T482
Test name
Test status
Simulation time 12321687504 ps
CPU time 120.67 seconds
Started Sep 18 07:43:39 PM UTC 24
Finished Sep 18 07:45:42 PM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767252915 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1767252915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_long_msg.1912274748
Short name T474
Test name
Test status
Simulation time 22158425884 ps
CPU time 96.36 seconds
Started Sep 18 07:43:19 PM UTC 24
Finished Sep 18 07:44:57 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912274748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1912274748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_smoke.1419499115
Short name T459
Test name
Test status
Simulation time 3544904144 ps
CPU time 12.72 seconds
Started Sep 18 07:43:17 PM UTC 24
Finished Sep 18 07:43:31 PM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419499115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1419499115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_stress_all.4264401181
Short name T480
Test name
Test status
Simulation time 3559451938 ps
CPU time 85.05 seconds
Started Sep 18 07:43:53 PM UTC 24
Finished Sep 18 07:45:21 PM UTC 24
Peak memory 210544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264401181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4264401181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.623999699
Short name T485
Test name
Test status
Simulation time 37061227484 ps
CPU time 155.86 seconds
Started Sep 18 07:43:49 PM UTC 24
Finished Sep 18 07:46:28 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623999699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.623999699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_alert_test.983258483
Short name T473
Test name
Test status
Simulation time 13442041 ps
CPU time 0.87 seconds
Started Sep 18 07:44:26 PM UTC 24
Finished Sep 18 07:44:28 PM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983258483 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.983258483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.760035294
Short name T476
Test name
Test status
Simulation time 795731505 ps
CPU time 55.02 seconds
Started Sep 18 07:44:02 PM UTC 24
Finished Sep 18 07:44:58 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760035294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.760035294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.3313439195
Short name T469
Test name
Test status
Simulation time 895287372 ps
CPU time 10.85 seconds
Started Sep 18 07:44:04 PM UTC 24
Finished Sep 18 07:44:16 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313439195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3313439195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.1770324803
Short name T511
Test name
Test status
Simulation time 5596752970 ps
CPU time 917.02 seconds
Started Sep 18 07:44:02 PM UTC 24
Finished Sep 18 07:59:29 PM UTC 24
Peak memory 750940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770324803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1770324803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_error.3837553519
Short name T477
Test name
Test status
Simulation time 3225761784 ps
CPU time 51.44 seconds
Started Sep 18 07:44:09 PM UTC 24
Finished Sep 18 07:45:02 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837553519 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3837553519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2593656347
Short name T483
Test name
Test status
Simulation time 2246972513 ps
CPU time 121.95 seconds
Started Sep 18 07:43:57 PM UTC 24
Finished Sep 18 07:46:01 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593656347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2593656347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_smoke.3049186145
Short name T467
Test name
Test status
Simulation time 684431003 ps
CPU time 8.2 seconds
Started Sep 18 07:43:54 PM UTC 24
Finished Sep 18 07:44:03 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049186145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3049186145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2201318922
Short name T84
Test name
Test status
Simulation time 60528562758 ps
CPU time 734.53 seconds
Started Sep 18 07:44:18 PM UTC 24
Finished Sep 18 07:56:41 PM UTC 24
Peak memory 219052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201318922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2201318922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.1244497676
Short name T484
Test name
Test status
Simulation time 22136612821 ps
CPU time 111.68 seconds
Started Sep 18 07:44:18 PM UTC 24
Finished Sep 18 07:46:12 PM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244497676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1244497676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_alert_test.3193271235
Short name T133
Test name
Test status
Simulation time 20723319 ps
CPU time 0.88 seconds
Started Sep 18 07:21:48 PM UTC 24
Finished Sep 18 07:21:50 PM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193271235 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3193271235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.3521378014
Short name T16
Test name
Test status
Simulation time 167764145 ps
CPU time 11.7 seconds
Started Sep 18 07:21:35 PM UTC 24
Finished Sep 18 07:21:48 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521378014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3521378014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.1105548884
Short name T165
Test name
Test status
Simulation time 654761950 ps
CPU time 46.19 seconds
Started Sep 18 07:21:37 PM UTC 24
Finished Sep 18 07:22:24 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105548884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1105548884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.3902477555
Short name T261
Test name
Test status
Simulation time 7895417190 ps
CPU time 364.26 seconds
Started Sep 18 07:21:36 PM UTC 24
Finished Sep 18 07:27:46 PM UTC 24
Peak memory 679236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902477555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3902477555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_error.1646722016
Short name T91
Test name
Test status
Simulation time 63289944009 ps
CPU time 277.36 seconds
Started Sep 18 07:21:38 PM UTC 24
Finished Sep 18 07:26:20 PM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646722016 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1646722016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_long_msg.4133898262
Short name T33
Test name
Test status
Simulation time 744934946 ps
CPU time 18.29 seconds
Started Sep 18 07:21:35 PM UTC 24
Finished Sep 18 07:21:55 PM UTC 24
Peak memory 210196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133898262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4133898262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_smoke.4089303825
Short name T19
Test name
Test status
Simulation time 149308434 ps
CPU time 2.21 seconds
Started Sep 18 07:21:35 PM UTC 24
Finished Sep 18 07:21:38 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089303825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4089303825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3505488051
Short name T78
Test name
Test status
Simulation time 21094932067 ps
CPU time 265.5 seconds
Started Sep 18 07:21:44 PM UTC 24
Finished Sep 18 07:26:14 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505488051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3505488051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.916093627
Short name T30
Test name
Test status
Simulation time 15921142645 ps
CPU time 73.19 seconds
Started Sep 18 07:21:39 PM UTC 24
Finished Sep 18 07:22:54 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916093627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.916093627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_alert_test.2629470124
Short name T183
Test name
Test status
Simulation time 36014854 ps
CPU time 0.81 seconds
Started Sep 18 07:22:04 PM UTC 24
Finished Sep 18 07:22:06 PM UTC 24
Peak memory 205364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629470124 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2629470124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.3723314628
Short name T163
Test name
Test status
Simulation time 8722627885 ps
CPU time 55.49 seconds
Started Sep 18 07:21:52 PM UTC 24
Finished Sep 18 07:22:49 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723314628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3723314628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.985090560
Short name T178
Test name
Test status
Simulation time 8195234772 ps
CPU time 36.29 seconds
Started Sep 18 07:21:56 PM UTC 24
Finished Sep 18 07:22:34 PM UTC 24
Peak memory 218976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985090560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.985090560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.3108472448
Short name T351
Test name
Test status
Simulation time 16787635656 ps
CPU time 715.57 seconds
Started Sep 18 07:21:52 PM UTC 24
Finished Sep 18 07:33:55 PM UTC 24
Peak memory 771488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108472448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3108472448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_error.900948546
Short name T239
Test name
Test status
Simulation time 14345889376 ps
CPU time 267.11 seconds
Started Sep 18 07:21:56 PM UTC 24
Finished Sep 18 07:26:27 PM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900948546 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.900948546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_long_msg.56500145
Short name T234
Test name
Test status
Simulation time 74845500394 ps
CPU time 242.38 seconds
Started Sep 18 07:21:52 PM UTC 24
Finished Sep 18 07:25:58 PM UTC 24
Peak memory 219140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56500145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.56500145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_smoke.1119993499
Short name T35
Test name
Test status
Simulation time 118799460 ps
CPU time 7.86 seconds
Started Sep 18 07:21:49 PM UTC 24
Finished Sep 18 07:21:58 PM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119993499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1119993499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_stress_all.466223126
Short name T26
Test name
Test status
Simulation time 31203310285 ps
CPU time 442.93 seconds
Started Sep 18 07:21:59 PM UTC 24
Finished Sep 18 07:29:28 PM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466223126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.466223126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.3613650735
Short name T210
Test name
Test status
Simulation time 39833286210 ps
CPU time 123.5 seconds
Started Sep 18 07:21:59 PM UTC 24
Finished Sep 18 07:24:05 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613650735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3613650735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_alert_test.2712346066
Short name T185
Test name
Test status
Simulation time 20958514 ps
CPU time 0.92 seconds
Started Sep 18 07:22:16 PM UTC 24
Finished Sep 18 07:22:17 PM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712346066 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2712346066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.1099573719
Short name T45
Test name
Test status
Simulation time 2222351239 ps
CPU time 33.41 seconds
Started Sep 18 07:22:04 PM UTC 24
Finished Sep 18 07:22:39 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099573719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1099573719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.2233579446
Short name T29
Test name
Test status
Simulation time 814908962 ps
CPU time 7.7 seconds
Started Sep 18 07:22:06 PM UTC 24
Finished Sep 18 07:22:15 PM UTC 24
Peak memory 210612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233579446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2233579446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.1593671830
Short name T390
Test name
Test status
Simulation time 4250527939 ps
CPU time 885.51 seconds
Started Sep 18 07:22:04 PM UTC 24
Finished Sep 18 07:36:59 PM UTC 24
Peak memory 779604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593671830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1593671830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_error.3962917590
Short name T225
Test name
Test status
Simulation time 23855304389 ps
CPU time 207.24 seconds
Started Sep 18 07:22:12 PM UTC 24
Finished Sep 18 07:25:43 PM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962917590 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3962917590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2259126056
Short name T179
Test name
Test status
Simulation time 375042499 ps
CPU time 10.79 seconds
Started Sep 18 07:22:04 PM UTC 24
Finished Sep 18 07:22:16 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259126056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2259126056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_smoke.2301922781
Short name T153
Test name
Test status
Simulation time 2474387943 ps
CPU time 6.47 seconds
Started Sep 18 07:22:04 PM UTC 24
Finished Sep 18 07:22:11 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301922781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2301922781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_stress_all.124575679
Short name T80
Test name
Test status
Simulation time 50651819891 ps
CPU time 929.23 seconds
Started Sep 18 07:22:14 PM UTC 24
Finished Sep 18 07:37:54 PM UTC 24
Peak memory 669064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124575679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.124575679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.2403936142
Short name T213
Test name
Test status
Simulation time 26311657442 ps
CPU time 120.27 seconds
Started Sep 18 07:22:14 PM UTC 24
Finished Sep 18 07:24:16 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403936142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2403936142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_alert_test.1538269159
Short name T189
Test name
Test status
Simulation time 15147017 ps
CPU time 0.87 seconds
Started Sep 18 07:22:27 PM UTC 24
Finished Sep 18 07:22:29 PM UTC 24
Peak memory 207348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538269159 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1538269159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.3662880963
Short name T18
Test name
Test status
Simulation time 3184954653 ps
CPU time 45.52 seconds
Started Sep 18 07:22:17 PM UTC 24
Finished Sep 18 07:23:04 PM UTC 24
Peak memory 226880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662880963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3662880963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.4226484867
Short name T174
Test name
Test status
Simulation time 294014749 ps
CPU time 17.89 seconds
Started Sep 18 07:22:19 PM UTC 24
Finished Sep 18 07:22:39 PM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226484867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4226484867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.495231346
Short name T100
Test name
Test status
Simulation time 618913593 ps
CPU time 129.56 seconds
Started Sep 18 07:22:19 PM UTC 24
Finished Sep 18 07:24:32 PM UTC 24
Peak memory 652336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495231346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.495231346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_error.571966868
Short name T193
Test name
Test status
Simulation time 1275517070 ps
CPU time 44.19 seconds
Started Sep 18 07:22:19 PM UTC 24
Finished Sep 18 07:23:05 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571966868 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.571966868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_long_msg.3097668078
Short name T211
Test name
Test status
Simulation time 1617904821 ps
CPU time 106.75 seconds
Started Sep 18 07:22:17 PM UTC 24
Finished Sep 18 07:24:06 PM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097668078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3097668078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_smoke.3382632396
Short name T44
Test name
Test status
Simulation time 6541115014 ps
CPU time 12.96 seconds
Started Sep 18 07:22:17 PM UTC 24
Finished Sep 18 07:22:31 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382632396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3382632396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_stress_all.3080404291
Short name T461
Test name
Test status
Simulation time 273416119346 ps
CPU time 1263.6 seconds
Started Sep 18 07:22:25 PM UTC 24
Finished Sep 18 07:43:44 PM UTC 24
Peak memory 214208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080404291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3080404291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.2321739541
Short name T139
Test name
Test status
Simulation time 4901452211 ps
CPU time 106.99 seconds
Started Sep 18 07:22:24 PM UTC 24
Finished Sep 18 07:24:13 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321739541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2321739541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2807962571
Short name T192
Test name
Test status
Simulation time 41554570 ps
CPU time 0.91 seconds
Started Sep 18 07:22:47 PM UTC 24
Finished Sep 18 07:22:49 PM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807962571 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2807962571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.228303442
Short name T142
Test name
Test status
Simulation time 436073736 ps
CPU time 27.2 seconds
Started Sep 18 07:22:32 PM UTC 24
Finished Sep 18 07:23:00 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228303442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.228303442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.2191352217
Short name T172
Test name
Test status
Simulation time 1307781074 ps
CPU time 71.87 seconds
Started Sep 18 07:22:35 PM UTC 24
Finished Sep 18 07:23:49 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191352217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2191352217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.3607632486
Short name T200
Test name
Test status
Simulation time 1579244468 ps
CPU time 56.36 seconds
Started Sep 18 07:22:33 PM UTC 24
Finished Sep 18 07:23:31 PM UTC 24
Peak memory 267456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607632486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3607632486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_error.1935298123
Short name T104
Test name
Test status
Simulation time 14205282360 ps
CPU time 144.97 seconds
Started Sep 18 07:22:35 PM UTC 24
Finished Sep 18 07:25:03 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935298123 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1935298123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_long_msg.1720174676
Short name T206
Test name
Test status
Simulation time 5211427621 ps
CPU time 76.59 seconds
Started Sep 18 07:22:30 PM UTC 24
Finished Sep 18 07:23:49 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720174676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1720174676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_smoke.188843428
Short name T177
Test name
Test status
Simulation time 107518669 ps
CPU time 3.22 seconds
Started Sep 18 07:22:27 PM UTC 24
Finished Sep 18 07:22:32 PM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188843428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.188843428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1959682086
Short name T191
Test name
Test status
Simulation time 2175346129 ps
CPU time 40.92 seconds
Started Sep 18 07:22:39 PM UTC 24
Finished Sep 18 07:23:21 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_17/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959682086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1959682086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.2841891732
Short name T136
Test name
Test status
Simulation time 10971795830 ps
CPU time 31.11 seconds
Started Sep 18 07:22:37 PM UTC 24
Finished Sep 18 07:23:09 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841891732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2841891732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/hmac-sim-vcs/9.hmac_wipe_secret/latest
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