Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17676519	1			T2	335		T4	737		T5	2070
all_values[1]	17676519	1			T2	335		T4	737		T5	2070
all_values[2]	17676519	1			T2	335		T4	737		T5	2070

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297498

1

T11

374

T25

16

T27

2

auto[1]

52732059

1

T2

1005

T4

2211

T5

6210

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45186569

1

T2

972

T4

1828

T5

4958

auto[1]

7842988

1

T2

33

T4

383

T5

1252

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80920	1			T11	371		T13	239		T137	1758
all_values[0]	auto[0]	auto[1]	353	1			T11	3		T13	3		T135	2
all_values[0]	auto[1]	auto[0]	17576156	1			T2	328		T4	728		T5	2065
all_values[0]	auto[1]	auto[1]	19090	1			T2	7		T4	9		T5	5
all_values[1]	auto[0]	auto[0]	124047	1			T28	154		T136	27		T53	602
all_values[1]	auto[0]	auto[1]	184	1			T134	3		T15	2		T66	4
all_values[1]	auto[1]	auto[0]	17551965	1			T2	335		T4	737		T5	2070
all_values[1]	auto[1]	auto[1]	323	1			T25	4		T13	2		T15	2
all_values[2]	auto[0]	auto[0]	54489	1			T25	16		T27	1		T28	41
all_values[2]	auto[0]	auto[1]	37505	1			T27	1		T28	113		T136	23
all_values[2]	auto[1]	auto[0]	9798992	1			T2	309		T4	363		T5	823
all_values[2]	auto[1]	auto[1]	7785533	1			T2	26		T4	374		T5	1247